[Mesa-dev] [PATCH 1/2] R600: Increase number of ArrayBase Reg to 32

[Tom Stellard]

On Thu, Feb 14, 2013 at 05:47:11PM +0100, Vincent Lejeune wrote:

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
> ---
>  lib/Target/R600/R600RegisterInfo.td | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td
> index 3812eb7..0718854 100644
> --- a/lib/Target/R600/R600RegisterInfo.td
> +++ b/lib/Target/R600/R600RegisterInfo.td
> @@ -44,7 +44,7 @@ foreach Index = 0-127 in {
>  }
>  
>  // Array Base Register holding input in FS
> -foreach Index = 448-464 in {
> +foreach Index = 448-480 in {
>    def ArrayBase#Index :  R600Reg<"ARRAY_BASE", Index>;
>  }
>  
> @@ -66,7 +66,7 @@ def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
>  def AR_X : R600Reg<"AR.x", 0>;
>  
>  def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
> -                          (add (sequence "ArrayBase%u", 448, 464))>;
> +                          (add (sequence "ArrayBase%u", 448, 480))>;
>  // special registers for ALU src operands
>  // const buffer reference, SRCx_SEL contains index
>  def ALU_CONST : R600Reg<"CBuf", 0>;
> -- 
> 1.8.1.2
> 
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