[llvm] r175144 - Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).

[Demikhovsky, Elena]

The bug was in lowering shuffle to zero extend. (Deep inside DAG pattern matching).
I attached the test that reproduces the failure.

- Elena

-----Original Message-----
From: Bill Wendling [mailto:wendling at apple.com] 
Sent: Thursday, February 14, 2013 10:28
To: Demikhovsky, Elena
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm] r175144 - Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).

On Feb 14, 2013, at 12:20 AM, Elena Demikhovsky <elena.demikhovsky at intel.com> wrote:

> Author: delena
> Date: Thu Feb 14 02:20:26 2013
> New Revision: 175144
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=175144&view=rev
> Log:
> Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).

Please be more descriptive in your commit messages. For instance, what was the bug that was fixed?

-bw

> Added a test.
> 
> Added:
>    llvm/trunk/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: 
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelL
> owering.cpp?rev=175144&r1=175143&r2=175144&view=diff
> ======================================================================
> ========
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Feb 14 02:20:26 
> +++ 2013
> @@ -6662,9 +6662,10 @@ X86TargetLowering::LowerVectorIntExtend(
>       return SDValue();
>   }
> 
> +  LLVMContext *Context = DAG.getContext();
>   unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
> -  EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits);
> -  EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> 
> Shift);
> +  EVT NeVT = EVT::getIntegerVT(*Context, NBits);  EVT NVT = 
> + EVT::getVectorVT(*Context, NeVT, NumElems >> Shift);
> 
>   if (!isTypeLegal(NVT))
>     return SDValue();
> @@ -6683,8 +6684,21 @@ X86TargetLowering::LowerVectorIntExtend(
>     // If it's foldable, i.e. normal load with single use, we will let code
>     // selection to fold it. Otherwise, we will short the conversion sequence.
>     if (CIdx && CIdx->getZExtValue() == 0 &&
> -        (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse()))
> +        (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
> +      if (V.getValueSizeInBits() > V1.getValueSizeInBits()) {
> +        // The "ext_vec_elt" node is wider than the result node.
> +        // In this case we should extract subvector from V.
> +        // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
> +        unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits();
> +        EVT FullVT = V.getValueType();
> +        EVT SubVecVT = EVT::getVectorVT(*Context, 
> +                                        FullVT.getVectorElementType(),
> +                                        FullVT.getVectorNumElements()/Ratio);
> +        V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V, 
> +                        DAG.getIntPtrConstant(0));
> +      }
>       V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
> +    }
>   }
> 
>   return DAG.getNode(ISD::BITCAST, DL, VT,
> 
> Added: llvm/trunk/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll
> URL: 
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2013-0
> 2-12-ShuffleToZext.ll?rev=175144&view=auto
> ======================================================================
> ========
> --- llvm/trunk/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/2013-02-12-ShuffleToZext.ll Thu Feb 14 
> +++ 02:20:26 2013
> @@ -0,0 +1,14 @@
> +; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx 
> +-mtriple=x86_64-pc-win32 | FileCheck %s
> +
> +; CHECK: test
> +; CHECK: vpmovzxwd
> +; CHECK: vpmovzxwd
> +define void @test(<4 x i64> %a, <4 x i16>* %buf) {
> +  %ex1 = extractelement <4 x i64> %a, i32 0
> +  %ex2 = extractelement <4 x i64> %a, i32 1
> +  %x1 = bitcast i64 %ex1 to <4 x i16>
> +  %x2 = bitcast i64 %ex2 to <4 x i16>
> +  %Sh = shufflevector <4 x i16> %x1, <4 x i16> %x2, <4 x i32> <i32 0, 
> +i32 1, i32 4, i32 5>
> +  store <4 x i16> %Sh, <4 x i16>* %buf, align 1
> +  ret void
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.