[llvm] r175102 - Hexagon: add support for predicate-GPR copies.

[Anshuman Dasgupta]

Author: adasgupt
Date: Wed Feb 13 16:56:34 2013
New Revision: 175102

URL: http://llvm.org/viewvc/llvm-project?rev=175102&view=rev
Log:
Hexagon: add support for predicate-GPR copies.

Added:
    llvm/trunk/test/CodeGen/Hexagon/predicate-copy.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=175102&r1=175101&r2=175102&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Feb 13 16:56:34 2013
@@ -426,6 +426,18 @@ void HexagonInstrInfo::copyPhysReg(Machi
     BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
     return;
   }
+  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
+      Hexagon::IntRegsRegClass.contains(DestReg)) {
+    BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
+      addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  }
+  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
+      Hexagon::PredRegsRegClass.contains(DestReg)) {
+    BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
+      addReg(SrcReg, getKillRegState(KillSrc));
+    return;
+  }
 
   llvm_unreachable("Unimplemented");
 }

Added: llvm/trunk/test/CodeGen/Hexagon/predicate-copy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/predicate-copy.ll?rev=175102&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/predicate-copy.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/predicate-copy.ll Wed Feb 13 16:56:34 2013
@@ -0,0 +1,8 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 < %s | FileCheck %s
+
+; CHECK: r{{[0-9]+}} = p{{[0-9]+}}
+define i1 @foo() {
+entry:
+  ret i1 false
+}
+