[llvm] r174660 - Constrain PowerPC autovectorization to fix bug 15041.

[Nadav Rotem]

Hi Bill, 

This looks much better. 

 - Nadav

On Feb 8, 2013, at 5:20 AM, Bill Schmidt <wschmidt at linux.vnet.ibm.com> wrote:

> 
> 
> On Thu, 2013-02-07 at 12:52 -0800, Nadav Rotem wrote:
>> Hi Bill, 
>> 
>> 
>> Returning a really high constant would prevent vectorization, but we
>> can do better. If you look at the ARM and X86 backend you will see
>> that we have code to estimate the 'scalarization' cost.  You can model
>> the expensive transition of data from scalar to vector registers by
>> assigning a high cost to the 'Insert/ExtractElement' instructions.
>> This is important because in some loops we have perfectly vectorizable
>> code with one 'scalarized' instruction. We still want to catch these
>> cases. Additionally, the vectorizer is not the only user of the cost
>> model. Some other transformations may want to estimate the cost of two
>> alternatives, and in that case 'awful' is not a useful answer.
> 
> Thanks, Nadav!  Now that I'm using the correct opcode space, penalizing
> just the scalarization at least solves the problem for paq8p.  I'll spot
> check some of the other problems I saw, but hopefully this will kill the
> worst offenders.
> 
> Bill
>> 
>> 
>> Thanks,
>> Nadav 
>> 
>> 
>> On Feb 7, 2013, at 12:33 PM, Bill Schmidt
>> <wschmidt at linux.vnet.ibm.com> wrote:
>> 
>>> +  const unsigned Awful = 1000;
>>> +
>>> +  // Vector element insert/extract with Altivec is very expensive.
>>> +  // Until VSX is available, avoid vectorizing loops that require
>>> +  // these operations.
>>> +  if (Opcode == ISD::EXTRACT_VECTOR_ELT ||
>>> +      Opcode == ISD::INSERT_VECTOR_ELT)
>>> +    return Awful;
>>> +
>>> +  // We don't vectorize SREM/UREM so well.  Constrain the
>>> vectorizer
>>> +  // for those as well.
>>> +  if (Opcode == ISD::SREM || Opcode == ISD::UREM)
>>> +    return Awful;
>>> +
>>> +  // VSELECT is not yet implemented, leading to use of
>>> insert/extract
>>> +  // and ISEL, hence not a good idea.
>>> +  if (Opcode == ISD::VSELECT)
>>> +    return Awful;
>>> +
>>>  return TargetTransformInfo::getVectorInstrCost(Opcode, Val,
>>> Index);
>>> }
>>> 
>> 
>