[llvm] r174496 - Add AArch64 CRC32 instructions

[Tim Northover]

Author: tnorthover
Date: Wed Feb  6 03:13:13 2013
New Revision: 174496

URL: http://llvm.org/viewvc/llvm-project?rev=174496&view=rev
Log:
Add AArch64 CRC32 instructions

These instructions are a late addition to the architecture, and may
yet end up behind an optional attribute, but for now they're available
at all times.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
    llvm/trunk/test/MC/AArch64/basic-a64-instructions.s
    llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=174496&r1=174495&r2=174496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Wed Feb  6 03:13:13 2013
@@ -1658,7 +1658,9 @@ def REV16xx : A64I_dp_1src_impl<0b1, 0b0
 //===----------------------------------------------------------------------===//
 // Data Processing (2 sources) instructions
 //===----------------------------------------------------------------------===//
-// Contains: UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL, LSR, ASR, ROR
+// Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
+//           LSR, ASR, ROR
+
 
 class dp_2src_impl<bit sf, bits<6> opcode, string asmop, list<dag> patterns,
                    RegisterClass GPRsp,
@@ -1672,6 +1674,19 @@ class dp_2src_impl<bit sf, bits<6> opcod
                    patterns,
                    itin>;
 
+multiclass dp_2src_crc<bit c, string asmop> {
+  def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
+                           !strconcat(asmop, "b"), [], GPR32, NoItinerary>;
+  def H_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 1},
+                           !strconcat(asmop, "h"), [], GPR32, NoItinerary>;
+  def W_www : dp_2src_impl<0b0, {0, 1, 0, c, 1, 0},
+                           !strconcat(asmop, "w"), [], GPR32, NoItinerary>;
+  def X_wwx : A64I_dp_2src<0b1, {0, 1, 0, c, 1, 1}, 0b0,
+                           !strconcat(asmop, "x\t$Rd, $Rn, $Rm"),
+                           (outs GPR32:$Rd), (ins GPR32:$Rn, GPR64:$Rm), [],
+                           NoItinerary>;
+}
+
 multiclass dp_2src_zext <bits<6> opcode, string asmop, SDPatternOperator op> {
    def www : dp_2src_impl<0b0,
                          opcode,
@@ -1705,6 +1720,9 @@ multiclass dp_2src <bits<6> opcode, stri
 }
 
 // Here we define the data processing 2 source instructions.
+defm CRC32  : dp_2src_crc<0b0, "crc32">;
+defm CRC32C : dp_2src_crc<0b1, "crc32c">;
+
 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
 

Modified: llvm/trunk/test/MC/AArch64/basic-a64-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/basic-a64-instructions.s?rev=174496&r1=174495&r2=174496&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/basic-a64-instructions.s (original)
+++ llvm/trunk/test/MC/AArch64/basic-a64-instructions.s Wed Feb  6 03:13:13 2013
@@ -1435,6 +1435,23 @@ _func:
 // Data-processing (2 source)
 //------------------------------------------------------------------------------
 
+        crc32b  w5, w7, w20
+        crc32h  w28, wzr, w30
+        crc32w  w0, w1, w2
+        crc32x  w7, w9, x20
+        crc32cb w9, w5, w4
+        crc32ch w13, w17, w25
+        crc32cw wzr, w3, w5
+        crc32cx w18, w16, xzr
+// CHECK: crc32b   w5, w7, w20             // encoding: [0xe5,0x40,0xd4,0x1a]
+// CHECK: crc32h   w28, wzr, w30           // encoding: [0xfc,0x47,0xde,0x1a]
+// CHECK: crc32w   w0, w1, w2              // encoding: [0x20,0x48,0xc2,0x1a]
+// CHECK: crc32x   w7, w9, x20             // encoding: [0x27,0x4d,0xd4,0x9a]
+// CHECK: crc32cb  w9, w5, w4              // encoding: [0xa9,0x50,0xc4,0x1a]
+// CHECK: crc32ch  w13, w17, w25           // encoding: [0x2d,0x56,0xd9,0x1a]
+// CHECK: crc32cw  wzr, w3, w5             // encoding: [0x7f,0x58,0xc5,0x1a]
+// CHECK: crc32cx  w18, w16, xzr           // encoding: [0x12,0x5e,0xdf,0x9a]
+
         udiv	w0, w7, w10
         udiv	x9, x22, x4
         sdiv	w12, w21, w0

Modified: llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt?rev=174496&r1=174495&r2=174496&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/basic-a64-instructions.txt Wed Feb  6 03:13:13 2013
@@ -1020,6 +1020,23 @@
 # Data-processing (2 source)
 #------------------------------------------------------------------------------
 
+# CHECK: crc32b  w5, w7, w20
+# CHECK: crc32h  w28, wzr, w30
+# CHECK: crc32w  w0, w1, w2
+# CHECK: crc32x  w7, w9, x20
+# CHECK: crc32cb w9, w5, w4
+# CHECK: crc32ch w13, w17, w25
+# CHECK: crc32cw wzr, w3, w5
+# CHECK: crc32cx w18, w16, xzr
+0xe5 0x40 0xd4 0x1a
+0xfc 0x47 0xde 0x1a
+0x20 0x48 0xc2 0x1a
+0x27 0x4d 0xd4 0x9a
+0xa9 0x50 0xc4 0x1a
+0x2d 0x56 0xd9 0x1a
+0x7f 0x58 0xc5 0x1a
+0x12 0x5e 0xdf 0x9a
+
 # CHECK: udiv	w0, w7, w10
 # CHECK: udiv	x9, x22, x4
 # CHECK: sdiv	w12, w21, w0