[llvm] r174083 - [PEI] Pass the frame index operand number to the eliminateFrameIndex function.
Jim Grosbach
grosbach at apple.com
Thu Jan 31 12:35:33 PST 2013
Hi Chad,
Nice speedup!
One gotcha to be careful of is that the old interface didn't officially assume that there was only one frame-index reference to resolve on a given instruction. Many (all?) in-tree targets assume that since they know if it's true for their ISA, but the general code can support multiple FI operands on an instruction.
-Jim
On Jan 31, 2013, at 12:02 PM, Chad Rosier <mcrosier at apple.com> wrote:
> Author: mcrosier
> Date: Thu Jan 31 14:02:54 2013
> New Revision: 174083
>
> URL: http://llvm.org/viewvc/llvm-project?rev=174083&view=rev
> Log:
> [PEI] Pass the frame index operand number to the eliminateFrameIndex function.
> Each target implementation was needlessly recomputing the index.
> Part of rdar://13076458
>
> Modified:
> llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
> llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
> llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
> llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
> llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
> llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
> llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
> llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h
> llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
> llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
> llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
> llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
> llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
> llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> llvm/trunk/lib/Target/X86/X86RegisterInfo.h
> llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
> llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
>
> Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -767,10 +767,11 @@ public:
> /// referenced by the iterator contains an MO_FrameIndex operand which must be
> /// eliminated by this method. This method may modify or replace the
> /// specified instruction, as long as it keeps the iterator pointing at the
> - /// finished product. SPAdj is the SP adjustment due to call frame setup
> - /// instruction.
> + /// finished product. SPAdj is the SP adjustment due to call frame setup
> + /// instruction. FIOperandNum is the FI operand number.
> virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
> - int SPAdj, RegScavenger *RS=NULL) const = 0;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const = 0;
>
> //===--------------------------------------------------------------------===//
> /// Debug information queries.
>
> Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original)
> +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Thu Jan 31 14:02:54 2013
> @@ -766,7 +766,7 @@ void PEI::replaceFrameIndices(MachineFun
> // If this instruction has a FrameIndex operand, we need to
> // use that target machine register info object to eliminate
> // it.
> - TRI.eliminateFrameIndex(MI, SPAdj,
> + TRI.eliminateFrameIndex(MI, SPAdj, i,
> FrameIndexVirtualScavenging ? NULL : RS);
>
> // Reset the iterator if we were at the beginning of the BB.
>
> Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Thu Jan 31 14:02:54 2013
> @@ -316,6 +316,16 @@ unsigned RegScavenger::findSurvivorReg(M
> return Survivor;
> }
>
> +static unsigned getFrameIndexOperandNum(MachineInstr *MI) {
> + unsigned i = 0;
> + while (!MI->getOperand(i).isFI()) {
> + ++i;
> + assert(i < MI->getNumOperands() &&
> + "Instr doesn't have FrameIndex operand!");
> + }
> + return i;
> +}
> +
> unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
> MachineBasicBlock::iterator I,
> int SPAdj) {
> @@ -364,12 +374,16 @@ unsigned RegScavenger::scavengeRegister(
> "Cannot scavenge register without an emergency spill slot!");
> TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
> MachineBasicBlock::iterator II = prior(I);
> - TRI->eliminateFrameIndex(II, SPAdj, this);
> +
> + unsigned FIOperandNum = getFrameIndexOperandNum(II);
> + TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
>
> // Restore the scavenged register before its use (or first terminator).
> TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
> II = prior(UseMI);
> - TRI->eliminateFrameIndex(II, SPAdj, this);
> +
> + FIOperandNum = getFrameIndexOperandNum(II);
> + TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
> }
>
> ScavengeRestore = prior(UseMI);
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -717,8 +717,8 @@ bool ARMBaseRegisterInfo::isFrameOffsetL
>
> void
> ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS) const {
> - unsigned i = 0;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS) const {
> MachineInstr &MI = *II;
> MachineBasicBlock &MBB = *MI.getParent();
> MachineFunction &MF = *MBB.getParent();
> @@ -727,13 +727,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex
> ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
> assert(!AFI->isThumb1OnlyFunction() &&
> "This eliminateFrameIndex does not support Thumb1!");
> -
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
> - }
> -
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
> unsigned FrameReg;
>
> int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
> @@ -755,18 +749,18 @@ ARMBaseRegisterInfo::eliminateFrameIndex
>
> // Special handling of dbg_value instructions.
> if (MI.isDebugValue()) {
> - MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
> - MI.getOperand(i+1).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
> + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
> return;
> }
>
> // Modify MI as necessary to handle as much of 'Offset' as possible
> bool Done = false;
> if (!AFI->isThumbFunction())
> - Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
> + Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
> else {
> assert(AFI->isThumb2Function());
> - Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
> + Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
> }
> if (Done)
> return;
> @@ -786,7 +780,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex
> unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
> if (Offset == 0)
> // Must be addrmode4/6.
> - MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
> + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
> else {
> ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
> if (!AFI->isThumbFunction())
> @@ -798,6 +792,6 @@ ARMBaseRegisterInfo::eliminateFrameIndex
> Offset, Pred, PredReg, TII);
> }
> // Update the original instruction to use the scratch register.
> - MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
> + MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
> }
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -173,7 +173,8 @@ public:
> MachineBasicBlock::iterator I) const;
>
> virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
> };
>
> } // end namespace llvm
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -593,9 +593,9 @@ Thumb1RegisterInfo::saveScavengerRegiste
>
> void
> Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS) const {
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS) const {
> unsigned VReg = 0;
> - unsigned i = 0;
> MachineInstr &MI = *II;
> MachineBasicBlock &MBB = *MI.getParent();
> MachineFunction &MF = *MBB.getParent();
> @@ -603,13 +603,8 @@ Thumb1RegisterInfo::eliminateFrameIndex(
> DebugLoc dl = MI.getDebugLoc();
> MachineInstrBuilder MIB(*MBB.getParent(), &MI);
>
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
> - }
> -
> unsigned FrameReg = ARM::SP;
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
> int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
> MF.getFrameInfo()->getStackSize() + SPAdj;
>
> @@ -646,15 +641,15 @@ Thumb1RegisterInfo::eliminateFrameIndex(
>
> // Special handling of dbg_value instructions.
> if (MI.isDebugValue()) {
> - MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
> - MI.getOperand(i+1).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
> return;
> }
>
> // Modify MI as necessary to handle as much of 'Offset' as possible
> assert(AFI->isThumbFunction() &&
> "This eliminateFrameIndex only supports Thumb1!");
> - if (rewriteFrameIndex(MI, i, FrameReg, Offset, TII))
> + if (rewriteFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
> return;
>
> // If we get here, the immediate doesn't fit into the instruction. We folded
> @@ -687,11 +682,12 @@ Thumb1RegisterInfo::eliminateFrameIndex(
> }
>
> MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
> - MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true);
> + MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true);
> if (UseRR)
> // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
> // register. The offset is already handled in the vreg value.
> - MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
> + MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
> + false);
> } else if (MI.mayStore()) {
> VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
> bool UseRR = false;
> @@ -708,11 +704,12 @@ Thumb1RegisterInfo::eliminateFrameIndex(
> emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
> *this);
> MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
> - MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
> + MI.getOperand(FIOperandNum).ChangeToRegister(VReg, false, false, true);
> if (UseRR)
> // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame
> // register. The offset is already handled in the vreg value.
> - MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false);
> + MI.getOperand(FIOperandNum+1).ChangeToRegister(FrameReg, false, false,
> + false);
> } else {
> llvm_unreachable("Unexpected opcode!");
> }
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -62,7 +62,8 @@ public:
> const TargetRegisterClass *RC,
> unsigned Reg) const;
> void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
> };
> }
>
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -133,21 +133,14 @@ eliminateCallFramePseudoInstr(MachineFun
> }
>
> void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS) const {
> -
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS) const {
> //
> // Hexagon_TODO: Do we need to enforce this for Hexagon?
> assert(SPAdj == 0 && "Unexpected");
>
> -
> - unsigned i = 0;
> MachineInstr &MI = *II;
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
> - }
> -
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
>
> // Addressable stack objects are accessed using neg. offsets from %fp.
> MachineFunction &MF = *MI.getParent()->getParent();
> @@ -167,8 +160,9 @@ void HexagonRegisterInfo::eliminateFrame
> TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
> !TII.isSpillPredRegOp(&MI)) {
> // Replace frame index with a stack pointer reference.
> - MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false, true);
> - MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
> + MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
> + false, true);
> + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
> } else {
> // Replace frame index with a frame pointer reference.
> if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
> @@ -205,8 +199,8 @@ void HexagonRegisterInfo::eliminateFrame
> dstReg).addReg(FrameReg).addImm(Offset);
> }
>
> - MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
> - MI.getOperand(i+1).ChangeToImmediate(0);
> + MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
> } else if ((MI.getOpcode() == Hexagon::STriw_indexed) ||
> (MI.getOpcode() == Hexagon::STriw) ||
> (MI.getOpcode() == Hexagon::STrid) ||
> @@ -233,29 +227,31 @@ void HexagonRegisterInfo::eliminateFrame
> TII.get(Hexagon::ADD_ri),
> resReg).addReg(FrameReg).addImm(Offset);
> }
> - MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
> - MI.getOperand(i+1).ChangeToImmediate(0);
> + MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
> } else if (TII.isMemOp(&MI)) {
> unsigned resReg = HEXAGON_RESERVED_REG_1;
> if (!MFI.hasVarSizedObjects() &&
> TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset))) {
> - MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false,
> - true);
> - MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
> + MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(),
> + false, false, true);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(FrameSize+Offset);
> } else if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
> BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
> TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
> BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
> TII.get(Hexagon::ADD_rr),
> resReg).addReg(FrameReg).addReg(resReg);
> - MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
> - MI.getOperand(i+1).ChangeToImmediate(0);
> + MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,
> + true);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
> } else {
> BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
> TII.get(Hexagon::ADD_ri),
> resReg).addReg(FrameReg).addImm(Offset);
> - MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
> - MI.getOperand(i+1).ChangeToImmediate(0);
> + MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,
> + true);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
> }
> } else {
> unsigned dstReg = MI.getOperand(0).getReg();
> @@ -265,14 +261,14 @@ void HexagonRegisterInfo::eliminateFrame
> TII.get(Hexagon::ADD_rr),
> dstReg).addReg(FrameReg).addReg(dstReg);
> // Can we delete MI??? r2 = add (r2, #0).
> - MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
> - MI.getOperand(i+1).ChangeToImmediate(0);
> + MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
> }
> } else {
> // If the offset is small enough to fit in the immediate field, directly
> // encode it.
> - MI.getOperand(i).ChangeToRegister(FrameReg, false);
> - MI.getOperand(i+1).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -61,7 +61,8 @@ struct HexagonRegisterInfo : public Hexa
> MachineBasicBlock::iterator I) const;
>
> void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
>
> /// determineFrameLayout - Determine the size of the frame and maximum call
> /// frame size.
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -126,24 +126,16 @@ eliminateCallFramePseudoInstr(MachineFun
> // direct reference.
> void MBlazeRegisterInfo::
> eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
> - RegScavenger *RS) const {
> + unsigned FIOperandNum, RegScavenger *RS) const {
> MachineInstr &MI = *II;
> MachineFunction &MF = *MI.getParent()->getParent();
> MachineFrameInfo *MFI = MF.getFrameInfo();
> -
> - unsigned i = 0;
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() &&
> - "Instr doesn't have FrameIndex operand!");
> - }
> -
> - unsigned oi = i == 2 ? 1 : 2;
> + unsigned OFIOperandNum = FIOperandNum == 2 ? 1 : 2;
>
> DEBUG(dbgs() << "\nFunction : " << MF.getName() << "\n";
> dbgs() << "<--------->\n" << MI);
>
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
> int stackSize = MFI->getStackSize();
> int spOffset = MFI->getObjectOffset(FrameIndex);
>
> @@ -159,12 +151,12 @@ eliminateFrameIndex(MachineBasicBlock::i
> // as explained on LowerFormalArguments, detect negative offsets
> // and adjust SPOffsets considering the final stack size.
> int Offset = (spOffset < 0) ? (stackSize - spOffset) : spOffset;
> - Offset += MI.getOperand(oi).getImm();
> + Offset += MI.getOperand(OFIOperandNum).getImm();
>
> DEBUG(dbgs() << "Offset : " << Offset << "\n" << "<--------->\n");
>
> - MI.getOperand(oi).ChangeToImmediate(Offset);
> - MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
> + MI.getOperand(OFIOperandNum).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum).ChangeToRegister(getFrameRegister(MF), false);
> }
>
> void MBlazeRegisterInfo::
>
> Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -56,7 +56,8 @@ struct MBlazeRegisterInfo : public MBlaz
>
> /// Stack Frame Processing Methods
> void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
>
> void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
>
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -163,7 +163,8 @@ eliminateCallFramePseudoInstr(MachineFun
>
> void
> MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS) const {
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS) const {
> assert(SPAdj == 0 && "Unexpected");
>
> unsigned i = 0;
> @@ -172,12 +173,7 @@ MSP430RegisterInfo::eliminateFrameIndex(
> MachineFunction &MF = *MBB.getParent();
> const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
> DebugLoc dl = MI.getDebugLoc();
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
> - }
> -
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
>
> unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
> int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
> @@ -191,7 +187,7 @@ MSP430RegisterInfo::eliminateFrameIndex(
> Offset += 2; // Skip the saved FPW
>
> // Fold imm into offset
> - Offset += MI.getOperand(i+1).getImm();
> + Offset += MI.getOperand(FIOperandNum + 1).getImm();
>
> if (MI.getOpcode() == MSP430::ADD16ri) {
> // This is actually "load effective address" of the stack slot
> @@ -199,7 +195,7 @@ MSP430RegisterInfo::eliminateFrameIndex(
> // expand it into mov + add
>
> MI.setDesc(TII.get(MSP430::MOV16rr));
> - MI.getOperand(i).ChangeToRegister(BasePtr, false);
> + MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
>
> if (Offset == 0)
> return;
> @@ -216,8 +212,8 @@ MSP430RegisterInfo::eliminateFrameIndex(
> return;
> }
>
> - MI.getOperand(i).ChangeToRegister(BasePtr, false);
> - MI.getOperand(i+1).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
> + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
> }
>
> unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
>
> Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -47,7 +47,8 @@ public:
> MachineBasicBlock::iterator I) const;
>
> void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
>
> // Debug information queries.
> unsigned getFrameRegister(const MachineFunction &MF) const;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -177,21 +177,14 @@ MipsRegisterInfo::trackLivenessAfterRegA
> // direct reference.
> void MipsRegisterInfo::
> eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
> - RegScavenger *RS) const {
> + unsigned FIOperandNum, RegScavenger *RS) const {
> MachineInstr &MI = *II;
> MachineFunction &MF = *MI.getParent()->getParent();
>
> - unsigned i = 0;
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() &&
> - "Instr doesn't have FrameIndex operand!");
> - }
> -
> DEBUG(errs() << "\nFunction : " << MF.getName() << "\n";
> errs() << "<--------->\n" << MI);
>
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
> uint64_t stackSize = MF.getFrameInfo()->getStackSize();
> int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
>
> @@ -199,7 +192,7 @@ eliminateFrameIndex(MachineBasicBlock::i
> << "spOffset : " << spOffset << "\n"
> << "stackSize : " << stackSize << "\n");
>
> - eliminateFI(MI, i, FrameIndex, stackSize, spOffset);
> + eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset);
> }
>
> unsigned MipsRegisterInfo::
>
> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -55,7 +55,8 @@ public:
>
> /// Stack Frame Processing Methods
> void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
>
> void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
>
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -277,30 +277,22 @@ BitVector NVPTXRegisterInfo::getReserved
>
> void NVPTXRegisterInfo::
> eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj,
> + int SPAdj, unsigned FIOperandNum,
> RegScavenger *RS) const {
> assert(SPAdj == 0 && "Unexpected");
>
> - unsigned i = 0;
> MachineInstr &MI = *II;
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() &&
> - "Instr doesn't have FrameIndex operand!");
> - }
> -
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
>
> MachineFunction &MF = *MI.getParent()->getParent();
> int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
> - MI.getOperand(i+1).getImm();
> + MI.getOperand(FIOperandNum+1).getImm();
>
> // Using I0 as the frame pointer
> - MI.getOperand(i).ChangeToRegister(NVPTX::VRFrame, false);
> - MI.getOperand(i+1).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
> + MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset);
> }
>
> -
> int NVPTXRegisterInfo::
> getDwarfRegNum(unsigned RegNum, bool isEH) const {
> return 0;
>
> Modified: llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/NVPTX/NVPTXRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -55,7 +55,7 @@ public:
> virtual BitVector getReservedRegs(const MachineFunction &MF) const;
>
> virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
> - int SPAdj,
> + int SPAdj, unsigned FIOperandNum,
> RegScavenger *RS=NULL) const;
>
> void eliminateCallFramePseudoInstr(MachineFunction &MF,
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -510,7 +510,8 @@ PPCRegisterInfo::hasReservedSpillSlot(co
>
> void
> PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS) const {
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS) const {
> assert(SPAdj == 0 && "Unexpected");
>
> // Get the instruction.
> @@ -524,20 +525,13 @@ PPCRegisterInfo::eliminateFrameIndex(Mac
> const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
> DebugLoc dl = MI.getDebugLoc();
>
> - // Find out which operand is the frame index.
> - unsigned FIOperandNo = 0;
> - while (!MI.getOperand(FIOperandNo).isFI()) {
> - ++FIOperandNo;
> - assert(FIOperandNo != MI.getNumOperands() &&
> - "Instr doesn't have FrameIndex operand!");
> - }
> // Take into account whether it's an add or mem instruction
> - unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
> + unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
> if (MI.isInlineAsm())
> - OffsetOperandNo = FIOperandNo-1;
> + OffsetOperandNo = FIOperandNum-1;
>
> // Get the frame index.
> - int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
>
> // Get the frame pointer save index. Users of this index are primarily
> // DYNALLOC instructions.
> @@ -567,7 +561,7 @@ PPCRegisterInfo::eliminateFrameIndex(Mac
> // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
>
> bool is64Bit = Subtarget.isPPC64();
> - MI.getOperand(FIOperandNo).ChangeToRegister(TFI->hasFP(MF) ?
> + MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
> (is64Bit ? PPC::X31 : PPC::R31) :
> (is64Bit ? PPC::X1 : PPC::R1),
> false);
> @@ -649,7 +643,7 @@ PPCRegisterInfo::eliminateFrameIndex(Mac
> OperandBase = OffsetOperandNo;
> }
>
> - unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
> + unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
> MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
> MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
> }
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -69,7 +69,8 @@ public:
> bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
> int &FrameIdx) const;
> void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
>
> // Debug information queries.
> unsigned getFrameRegister(const MachineFunction &MF) const;
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -71,30 +71,25 @@ eliminateCallFramePseudoInstr(MachineFun
>
> void
> SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS) const {
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS) const {
> assert(SPAdj == 0 && "Unexpected");
>
> - unsigned i = 0;
> MachineInstr &MI = *II;
> DebugLoc dl = MI.getDebugLoc();
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
> - }
> -
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
>
> // Addressable stack objects are accessed using neg. offsets from %fp
> MachineFunction &MF = *MI.getParent()->getParent();
> int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
> - MI.getOperand(i+1).getImm();
> + MI.getOperand(FIOperandNum + 1).getImm();
>
> // Replace frame index with a frame pointer reference.
> if (Offset >= -4096 && Offset <= 4095) {
> // If the offset is small enough to fit in the immediate field, directly
> // encode it.
> - MI.getOperand(i).ChangeToRegister(SP::I6, false);
> - MI.getOperand(i+1).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum).ChangeToRegister(SP::I6, false);
> + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
> } else {
> // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
> // scavenge a register here instead of reserving G1 all of the time.
> @@ -104,8 +99,8 @@ SparcRegisterInfo::eliminateFrameIndex(M
> BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
> .addReg(SP::I6);
> // Insert: G1+%lo(offset) into the user.
> - MI.getOperand(i).ChangeToRegister(SP::G1, false);
> - MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
> + MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
> + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -41,7 +41,8 @@ struct SparcRegisterInfo : public SparcG
> MachineBasicBlock::iterator I) const;
>
> void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
>
> void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
>
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -544,20 +544,14 @@ eliminateCallFramePseudoInstr(MachineFun
>
> void
> X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS) const {
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS) const {
> assert(SPAdj == 0 && "Unexpected");
>
> - unsigned i = 0;
> MachineInstr &MI = *II;
> MachineFunction &MF = *MI.getParent()->getParent();
> const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
> -
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
> - }
> -
> - int FrameIndex = MI.getOperand(i).getIndex();
> + int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
> unsigned BasePtr;
>
> unsigned Opc = MI.getOpcode();
> @@ -573,7 +567,7 @@ X86RegisterInfo::eliminateFrameIndex(Mac
>
> // This must be part of a four operand memory reference. Replace the
> // FrameIndex with base register with EBP. Add an offset to the offset.
> - MI.getOperand(i).ChangeToRegister(BasePtr, false);
> + MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
>
> // Now add the frame object offset to the offset from EBP.
> int FIOffset;
> @@ -584,17 +578,18 @@ X86RegisterInfo::eliminateFrameIndex(Mac
> } else
> FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
>
> - if (MI.getOperand(i+3).isImm()) {
> + if (MI.getOperand(FIOperandNum+3).isImm()) {
> // Offset is a 32-bit integer.
> - int Imm = (int)(MI.getOperand(i + 3).getImm());
> + int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
> int Offset = FIOffset + Imm;
> assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
> "Requesting 64-bit offset in 32-bit immediate!");
> - MI.getOperand(i + 3).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
> } else {
> // Offset is symbolic. This is extremely rare.
> - uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
> - MI.getOperand(i+3).setOffset(Offset);
> + uint64_t Offset = FIOffset +
> + (uint64_t)MI.getOperand(FIOperandNum+3).getOffset();
> + MI.getOperand(FIOperandNum + 3).setOffset(Offset);
> }
> }
>
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -122,7 +122,8 @@ public:
> MachineBasicBlock::iterator MI) const;
>
> void eliminateFrameIndex(MachineBasicBlock::iterator MI,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
>
> // Debug information queries.
> unsigned getFrameRegister(const MachineFunction &MF) const;
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Thu Jan 31 14:02:54 2013
> @@ -155,18 +155,12 @@ eliminateCallFramePseudoInstr(MachineFun
>
> void
> XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS) const {
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS) const {
> assert(SPAdj == 0 && "Unexpected");
> MachineInstr &MI = *II;
> DebugLoc dl = MI.getDebugLoc();
> - unsigned i = 0;
> -
> - while (!MI.getOperand(i).isFI()) {
> - ++i;
> - assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
> - }
> -
> - MachineOperand &FrameOp = MI.getOperand(i);
> + MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
> int FrameIndex = FrameOp.getIndex();
>
> MachineFunction &MF = *MI.getParent()->getParent();
> @@ -190,14 +184,14 @@ XCoreRegisterInfo::eliminateFrameIndex(M
>
> // Special handling of DBG_VALUE instructions.
> if (MI.isDebugValue()) {
> - MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
> - MI.getOperand(i+1).ChangeToImmediate(Offset);
> + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
> + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
> return;
> }
>
> // fold constant into offset.
> - Offset += MI.getOperand(i + 1).getImm();
> - MI.getOperand(i + 1).ChangeToImmediate(0);
> + Offset += MI.getOperand(FIOperandNum + 1).getImm();
> + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
>
> assert(Offset%4 == 0 && "Misaligned stack offset");
>
>
> Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=174083&r1=174082&r2=174083&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Thu Jan 31 14:02:54 2013
> @@ -59,7 +59,8 @@ public:
> MachineBasicBlock::iterator I) const;
>
> void eliminateFrameIndex(MachineBasicBlock::iterator II,
> - int SPAdj, RegScavenger *RS = NULL) const;
> + int SPAdj, unsigned FIOperandNum,
> + RegScavenger *RS = NULL) const;
>
> // Debug information queries.
> unsigned getFrameRegister(const MachineFunction &MF) const;
>
>
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