[llvm-commits] [llvm] r173625 - Legalizer: Reword comment again, per Duncan's suggestion.

[Benjamin Kramer]

Author: d0k
Date: Sun Jan 27 15:02:52 2013
New Revision: 173625

URL: http://llvm.org/viewvc/llvm-project?rev=173625&view=rev
Log:
Legalizer: Reword comment again, per Duncan's suggestion.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=173625&r1=173624&r2=173625&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sun Jan 27 15:02:52 2013
@@ -2098,9 +2098,8 @@ void DAGTypeLegalizer::ExpandIntRes_Shif
     EVT VT = LHSL.getValueType();
 
     // If the shift amount operand is coming from a vector legalization it may
-    // have an illegal type.  Fix that first by casting the operand.  Otherwise
-    // the new SHL_PARTS operation would need further legalization, and the
-    // legalizer assumes that illegal SHL_PARTS never occur.
+    // have an illegal type.  Fix that first by casting the operand, otherwise
+    // the new SHL_PARTS operation would need further legalization.
     SDValue ShiftOp = N->getOperand(1);
     MVT ShiftTy = TLI.getShiftAmountTy(VT);
     assert(ShiftTy.getSizeInBits() >= Log2_32_Ceil(VT.getSizeInBits()) &&