[llvm-commits] [RFC v2] Towards an assembler parser for PowerPC

Ulrich Weigand Ulrich.Weigand at de.ibm.com
Fri Jan 25 09:13:43 PST 2013


Hello,

here's another update of the PowerPC assembler parser patch set I've been
working on.   Overall, the parser now seems to be good enough to parse any
assembler file generated by clang itself.  (Obviously, there's still a
large number of instructions that are not handled.  But I'd suggest support
for those can be completed step by step after the initial patch set has
landed.)

Specifically, I've successfully run all tests in projects/test-suite with a
version of the clang driver configured to compile everything to assembler
source, and then assemble that source to object files by using clang
-cc1as.

For an overall description of the patch set, please refer to:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130114/162560.html
Note that many of the questions/issues discussed there still apply to the
current patch set, so I still do not consider it ready for upstream in its
current form.

Notable changes in this week's version of the patch set:

- diff-llvm-asm-branches:
The major change is a rewrite of the ISEL patterns to no longer take a
"pred" operand (pair of CCRC and PRED_... value), but instead directly take
a CCBITRC operand.  This models the actual instruction much more directly,
simplifies the logic to output it in either binary or textual form, and now
also makes it straightforward to handle in the asm parser.   The "pred"
operand is still used for the conditional branches, but as this is now the
sole user, some of the complexity in "pred" handling can be removed as
well.  As a result, while the BCC pattern itself still needs to remain
isCodeGenOnly, we can now handle the major conditional branch mnemonics in
the parser via simple InstAlias definitions resulting in instances of BCC.
[ As an option, it might be interesting to completely remove BCC and
replace it by a pair of BT/BF instructions that also take a CCBITRC
operand.  This might lead to further simplification ...  ]

- diff-llvm-asm-faddrtx:
This is a new patch, added to handle parsing the sequence generated to
implement long double -> int conversions.  As part of this sequence, we
need to perform an FADD in round-to-zero mode.  This is problematical since
the FPSCR is not at all modeled at the SelectionDAG level, and thus there
is a risk of getting floating point instructions generated out of sequence
with the instructions to modify FPSCR.  The current code handles this by
somewhat "special" patterns that in part have dummy operands, and/or
duplicate existing instructions, making them awkward for the parser.   My
patch suggests to change this by leaving the "FADD in round-to-zero mode"
as an atomic operation on the SelectionDAG level, and only split it up into
real instructions at the MI level (via custom inserter).  Since at *this*
level the FPSCR *is* modeled (via the "RM" hard register), much of the
"special" stuff can just go away, and the resulting patterns can be used by
the asm parser.

- diff-llvm-asm-fixups:
This is another patch, which became necessary to fix issues in generating
relocations.  The main problem is code like this
inMCTargetDesc/PPCMCCodeEmitter.cpp:
 if (isSVR4ABI() && is64BitMode())
   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_toc16));
 else
   Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
                                    (MCFixupKind)PPC::fixup_ppc_lo16));
which made wrong choices in the context of the asm parser, apparently since
the ABI/64-bit mode wasn't set up correctly.   However, more fundamentally,
at this point we shouldn't make such distinctions anyway; in an assembler
file, it always ought to be possible to e.g. generate TOC relocations even
when the main ABI is one that doesn't use TOC.  Fortunately, this is
actually completely unnecessary; that code was added to decide whether to
generate TOC relocations, but that information is in fact already encoded
in the VariantKind of the underlying symbol.  My patch therefore merges
those fixup types into one, and then decides which relocation to use based
on the VariantKind.

- diff-llvm-asm-hacks:
Removed some hacks that are now unnecessary due to the rework of the
FADDrtz sequence.   Added one new hack: when generating assembler source
for PC-relative branches, emit ".+8" instead of "$+8" since the generic
expression handling in the asm parser does not understand the usage of "$"
to refer to the current PC.  See also:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130121/163161.html

- diff-llvm-asm-parser:
This patch has undergone significant changes.  In addition to miscellaneous
bugfixes and cleanups, the following features were added:   support for
CCBITRC, CCRC, and crbitm operand types, support for the ".tc" directive,
and an actual implementation of ParseRegister (needed for cfi directives
and inline asm).

- diff-llvm-asm-aliases:
Added aliases for SLWI/SRWI and conditional branches.

Any comments, also on topics raised in last week's mail, remain welcome!


Bye,
Ulrich

(See attached file: diff-llvm-asm-address)(See attached file:
diff-llvm-asm-aliases)(See attached file: diff-llvm-asm-branches)(See
attached file: diff-llvm-asm-calls)(See attached file:
diff-llvm-asm-faddrtz)(See attached file: diff-llvm-asm-fixups)(See
attached file: diff-llvm-asm-hacks)(See attached file:
diff-llvm-asm-parser)(See attached file: diff-llvm-asm-preinc)(See attached
file: diff-llvm-asm-variants)(See attached file: diff-llvm-tblgen-regclass)
(See attached file: diff-llvm-tblgen-tie)(See attached file: series)
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