[llvm-commits] Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM
Weiming Zhao
weimingz at codeaurora.org
Thu Jan 24 17:46:04 PST 2013
Hi Jakob,
First, Im really sorry for late repose. I was really busy on other parts of
LLVM in the past few weeks.
CopyFromReg cant take a Untyped VT because
ScheduleDAGRRList.cpp::GetCostForDef() expects MachineOpCode for Untyped
node, while CopyFromReg is not a MachineOpCode:
static void GetCostForDef(
) {
MVT VT = RegDefPos.GetValue();
// Special handling for untyped values. These values can only come from
// the expansion of custom DAG-to-DAG patterns.
if (VT == MVT::Untyped) {
const SDNode *Node = RegDefPos.GetNode();
unsigned Opcode = Node->getMachineOpcode(); à CopyFromReg is not a
MachineOpcode()
This is why Im avoiding using CopyFromReg for Untyped.
Thanks,
Weiming
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk]
Sent: Thursday, January 03, 2013 12:58 PM
To: weimingz at codeaurora.org
Cc: llvm-commits at cs.uiuc.edu; 'James Grosbach'; Evan Cheng
Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm
with 64-bit data on ARM
On Jan 3, 2013, at 12:03 PM, Weiming Zhao <weimingz at codeaurora.org> wrote:
Yes, I tried to use CopyToReg/CopyFromReg to enforce the order. The issue is
Untyped data type.
The REG_SEQUENCE and EXTRACT_SUBREG has to use Untyped data type. However,
CopyToReg/CopyFromReg doesnt support such data type.
Why not?
And I explicitly add a glue edge between the Extract_subreg and inline asm:
SDValue E0 = SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
dl, MVT::i32, MVT::Glue, PairedReg,
CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32),
Chain.getValue(1) è Guarantees that this node is
emitted after the linlineasm
), 0);
In other words, this node has the same effect as CopyFromReg.
Your DAG may work, but your changes still allow bad DAGs to be emitted.
Plus, as I said, it's not necessary.
/jakob
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