[llvm-commits] [PATCH] Add TargetMemoryModel

[Hal Finkel]

David,

I am in favor of including this information; Among other things, I am working on a software prefetching pass that would greatly benefit from this. Is there a reason not to include this as part of the TTI infrastructure?

In addition, the prefetcher info should be cache-level specific. Many systems have different prefetchers for different cache levels. It is also important to know how may requests the prefetcher will generate in response to a stream hit or miss in its target cache level. Some prefetchers will continue to issue requests to fill the stream up to the stream depth as soon as the stream is established. Other prefetchers will only issue N new requests in response to hits or misses of the stream (bounded by the depth).

Thanks again,
Hal

----- Original Message -----
> From: greened at obbligato.org
> To: "David Greene" <dag at cray.com>
> Cc: llvm-commits at cs.uiuc.edu
> Sent: Thursday, January 24, 2013 9:56:50 AM
> Subject: Re: [llvm-commits] [PATCH] Add TargetMemoryModel
> 
> David Greene <dag at cray.com> writes:
> 
> > Add a new class to represent a processor memory model.  Memory
> > models
> > can include cache hierarchies, stream buffer information and
> > configuration data for target-independent software prefetchers.
> > ---
> >  llvm/include/llvm/Target/TargetMemoryModel.h |  257
> >  ++++++++++++++++++++++++++
> >  llvm/lib/Target/TargetMemoryModel.cpp        |   45 +++++
> >  2 files changed, 302 insertions(+), 0 deletions(-)
> >  create mode 100644 llvm/include/llvm/Target/TargetMemoryModel.h
> >  create mode 100644 llvm/lib/Target/TargetMemoryModel.cpp
> >
> >
> > _______________________________________________
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> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> Ping?
> 
>                        -David
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