[llvm-commits] [llvm] r173288 - in /llvm/trunk: lib/Target/XCore/Disassembler/XCoreDisassembler.cpp lib/Target/XCore/XCoreInstrFormats.td lib/Target/XCore/XCoreInstrInfo.td test/MC/Disassembler/XCore/xcore.txt
Richard Osborne
richard at xmos.com
Wed Jan 23 12:08:11 PST 2013
Author: friedgold
Date: Wed Jan 23 14:08:11 2013
New Revision: 173288
URL: http://llvm.org/viewvc/llvm-project?rev=173288&view=rev
Log:
Add instruction encodings / disassembly support for l6r instructions.
Modified:
llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td
llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
llvm/trunk/test/MC/Disassembler/XCore/xcore.txt
Modified: llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp?rev=173288&r1=173287&r2=173288&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp Wed Jan 23 14:08:11 2013
@@ -170,6 +170,11 @@
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
#include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@@ -572,6 +577,26 @@
return S;
}
+static DecodeStatus
+DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
+ unsigned Op1, Op2, Op3, Op4, Op5, Op6;
+ DecodeStatus S =
+ Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
+ if (S != MCDisassembler::Success)
+ return S;
+ S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
+ if (S != MCDisassembler::Success)
+ return S;
+ DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
+ DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
+ return S;
+}
+
MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size,
Modified: llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td?rev=173288&r1=173287&r2=173288&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrFormats.td Wed Jan 23 14:08:11 2013
@@ -226,6 +226,10 @@
: InstXCore<4, outs, ins, asmstr, pattern> {
}
-class _L6R<dag outs, dag ins, string asmstr, list<dag> pattern>
+class _FL6R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
+ let Inst{31-27} = opc;
+ let Inst{15-11} = 0b11111;
+
+ let DecoderMethod = "DecodeL6RInstruction";
}
Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=173288&r1=173287&r2=173288&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Wed Jan 23 14:08:11 2013
@@ -502,11 +502,10 @@
// Six operand long
-def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
- (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
- GRRegs:$src4),
- "lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
- []>;
+def LMUL_l6r : _FL6R<
+ 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
+ (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
+ "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
// Register - U6
Modified: llvm/trunk/test/MC/Disassembler/XCore/xcore.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/XCore/xcore.txt?rev=173288&r1=173287&r2=173288&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/XCore/xcore.txt (original)
+++ llvm/trunk/test/MC/Disassembler/XCore/xcore.txt Wed Jan 23 14:08:11 2013
@@ -456,3 +456,8 @@
# CHECK: bl 38631
0x25 0xf0 0xe7 0xd2
+
+# l6r instructions
+
+# CHECK: lmul r11, r0, r2, r5, r8, r10
+0xf9 0xfa 0x02 0x06
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