[llvm-commits] [llvm] r172793 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Craig Topper
craig.topper at gmail.com
Thu Jan 17 22:51:00 PST 2013
Author: ctopper
Date: Fri Jan 18 00:50:59 2013
New Revision: 172793
URL: http://llvm.org/viewvc/llvm-project?rev=172793&view=rev
Log:
Spelling fix: extened->extended. Trailing whitespace in same function.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=172793&r1=172792&r2=172793&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jan 18 00:50:59 2013
@@ -16967,29 +16967,30 @@
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget *Subtarget) {
EVT VT = N->getValueType(0);
-
+
if (!VT.isVector())
return SDValue();
SDValue In = N->getOperand(0);
EVT InVT = In.getValueType();
DebugLoc dl = N->getDebugLoc();
- unsigned ExtenedEltSize = VT.getVectorElementType().getSizeInBits();
+ unsigned ExtendedEltSize = VT.getVectorElementType().getSizeInBits();
// Split SIGN_EXTEND operation to use vmovsx instruction when possible
if (InVT == MVT::v8i8) {
- if (ExtenedEltSize > 16 && !Subtarget->hasInt256())
+ if (ExtendedEltSize > 16 && !Subtarget->hasInt256())
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, In);
- if (ExtenedEltSize > 32)
+ if (ExtendedEltSize > 32)
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i32, In);
return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In);
}
if ((InVT == MVT::v4i8 || InVT == MVT::v4i16) &&
- ExtenedEltSize > 32 && !Subtarget->hasInt256()) {
+ ExtendedEltSize > 32 && !Subtarget->hasInt256()) {
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, In);
return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In);
}
+
if (!DCI.isBeforeLegalizeOps())
return SDValue();
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