[llvm-commits] [PATCH] AArch64 backend: LLVM changes

[Tim Northover]

Hi Evan,

> /// EXTR instruciton extracts a contiguous chunk of bits from two existing
> /// registers viewed as a high/low pair. This function looks for the pattern:
> /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
> /// EXTR. Can't quite be done in TableGen because the two immediates aren't
> /// independent.
>
> Can't you match the instruction to rotr?

If VAL1 and VAL2 are the same then it's a rotr. That pattern doesn't
need C++ help so it's matched in the TableGen.

Tim.