[llvm-commits] [llvm] r171702 - in /llvm/trunk/lib/Target/Hexagon: HexagonInstrInfo.td HexagonInstrInfoV4.td
Craig Topper
craig.topper at gmail.com
Sun Jan 6 22:14:20 PST 2013
Author: ctopper
Date: Mon Jan 7 00:14:20 2013
New Revision: 171702
URL: http://llvm.org/viewvc/llvm-project?rev=171702&view=rev
Log:
Remove more unnecessary # operators with nothing to paste proceeding them.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=171702&r1=171701&r2=171702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Mon Jan 7 00:14:20 2013
@@ -98,7 +98,7 @@
multiclass ALU32_Pbase<string mnemonic, bit isNot,
bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
@@ -107,7 +107,7 @@
}
multiclass ALU32_Pred<string mnemonic, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>;
// Predicate new
defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>;
@@ -144,7 +144,7 @@
// ALU32/ALU (ADD with register-immediate form)
//===----------------------------------------------------------------------===//
multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
@@ -153,7 +153,7 @@
}
multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
// Predicate new
defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
@@ -222,7 +222,7 @@
multiclass TFR_Pred<bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
@@ -252,7 +252,7 @@
}
multiclass TFR64_Pred<bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
def _c#NAME : ALU32_rr<(outs DoubleRegs:$dst),
(ins PredRegs:$src1, DoubleRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
@@ -283,7 +283,7 @@
multiclass TFRI_Pred<bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Ext:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
@@ -845,16 +845,16 @@
// Load -- MEMri operand
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
bit isNot, bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, MEMri:$addr),
- #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
+ !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($addr)",
[]>;
}
multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
@@ -911,17 +911,17 @@
// Load - Base with Immediate offset addressing mode
multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
bit isNot, bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
- #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
+ !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2+#$src3)",
[]>;
}
multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
// Predicate new
defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
@@ -1005,10 +1005,10 @@
multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
bit isNot, bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
- #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
+ !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2++#$offset)",
[],
"$src2 = $dst2">;
@@ -1016,7 +1016,7 @@
multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
Operand ImmOp, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
// Predicate new
let Predicates = [HasV4T], validSubTargets = HasV4SubT in
@@ -1440,7 +1440,7 @@
//===----------------------------------------------------------------------===//
multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : STInst2<(outs),
(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
@@ -1449,7 +1449,7 @@
}
multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
@@ -1467,7 +1467,7 @@
isPredicable = 1 in
def NAME : STInst2<(outs),
(ins MEMri:$addr, RC:$src),
- #mnemonic#"($addr) = $src",
+ mnemonic#"($addr) = $src",
[]>;
let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
@@ -1506,7 +1506,7 @@
//===----------------------------------------------------------------------===//
multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
bit isNot, bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
@@ -1516,7 +1516,7 @@
multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true"), isPredicated = 1 in {
+ let PredSense = !if(PredNot, "false", "true"), isPredicated = 1 in {
defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
// Predicate new
@@ -1535,7 +1535,7 @@
isPredicable = 1 in
def NAME : STInst2<(outs),
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
- #mnemonic#"($src1+#$src2) = $src3",
+ mnemonic#"($src1+#$src2) = $src3",
[]>;
let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits in {
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=171702&r1=171701&r2=171702&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Mon Jan 7 00:14:20 2013
@@ -418,7 +418,7 @@
// addressing mode
multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
@@ -427,7 +427,7 @@
}
multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
@@ -1518,7 +1518,7 @@
// mode
multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
RC:$src5),
@@ -1529,7 +1529,7 @@
}
multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
@@ -1542,7 +1542,7 @@
let isPredicable = 1 in
def NAME#_V4 : STInst2<(outs),
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
- #mnemonic#"($src1+$src2<<#$src3) = $src4",
+ mnemonic#"($src1+$src2<<#$src3) = $src4",
[]>,
Requires<[HasV4T]>;
@@ -1557,7 +1557,7 @@
// addressing mode.
multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
RC:$src5),
@@ -1568,7 +1568,7 @@
}
multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
// Predicate new
defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
@@ -1581,7 +1581,7 @@
let isPredicable = 1 in
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
- #mnemonic#"($src1+$src2<<#$src3) = $src4.new",
+ mnemonic#"($src1+$src2<<#$src3) = $src4.new",
[]>,
Requires<[HasV4T]>;
@@ -1682,17 +1682,17 @@
// addressing mode and immediate stored value.
multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
- #!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
+ !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = #$src4",
[]>,
Requires<[HasV4T]>;
}
multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
// Predicate new
defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
@@ -1705,7 +1705,7 @@
let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
def NAME#_V4 : STInst2<(outs),
(ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
- #mnemonic#"($src1+#$src2) = #$src3",
+ mnemonic#"($src1+#$src2) = #$src3",
[]>,
Requires<[HasV4T]>;
@@ -2356,7 +2356,7 @@
//
multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
Operand predImmOp, bit isNot, bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
@@ -2367,7 +2367,7 @@
multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
// Predicate new
defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
@@ -2384,7 +2384,7 @@
isPredicable = 1 in
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
- #mnemonic#"($src1+#$src2) = $src3.new",
+ mnemonic#"($src1+#$src2) = $src3.new",
[]>,
Requires<[HasV4T]>;
@@ -2409,7 +2409,7 @@
// and MEMri operand.
multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
- let PNewValue = #!if(isPredNew, "new", "") in
+ let PNewValue = !if(isPredNew, "new", "") in
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
@@ -2419,7 +2419,7 @@
}
multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
- let PredSense = #!if(PredNot, "false", "true") in {
+ let PredSense = !if(PredNot, "false", "true") in {
defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
// Predicate new
@@ -2436,7 +2436,7 @@
isPredicable = 1 in
def NAME#_nv_V4 : NVInst_V4<(outs),
(ins MEMri:$addr, RC:$src),
- #mnemonic#"($addr) = $src.new",
+ mnemonic#"($addr) = $src.new",
[]>,
Requires<[HasV4T]>;
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