[llvm-commits] [llvm] r171508 - /llvm/trunk/docs/TableGenFundamentals.rst

[Eli Bendersky]

Author: eliben
Date: Fri Jan  4 13:09:15 2013
New Revision: 171508

URL: http://llvm.org/viewvc/llvm-project?rev=171508&view=rev
Log:
fix a couple of typos

Modified:
    llvm/trunk/docs/TableGenFundamentals.rst

Modified: llvm/trunk/docs/TableGenFundamentals.rst
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TableGenFundamentals.rst?rev=171508&r1=171507&r2=171508&view=diff
==============================================================================
--- llvm/trunk/docs/TableGenFundamentals.rst (original)
+++ llvm/trunk/docs/TableGenFundamentals.rst Fri Jan  4 13:09:15 2013
@@ -121,11 +121,11 @@
   ...
 
 This definition corresponds to the 32-bit register-register ``add`` instruction
-of the the x86 architecture.  ``def ADD32rr`` defines a record named
+of the x86 architecture.  ``def ADD32rr`` defines a record named
 ``ADD32rr``, and the comment at the end of the line indicates the superclasses
 of the definition.  The body of the record contains all of the data that
 TableGen assembled for the record, indicating that the instruction is part of
-the "X86" namespace, the pattern indicating how the the instruction should be
+the "X86" namespace, the pattern indicating how the instruction should be
 emitted into the assembly file, that it is a two-address instruction, has a
 particular encoding, etc.  The contents and semantics of the information in the
 record are specific to the needs of the X86 backend, and are only shown as an