[llvm-commits] [llvm] r170947 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Akira Hatanaka
ahatanaka at mips.com
Fri Dec 21 14:57:27 PST 2012
Author: ahatanak
Date: Fri Dec 21 16:57:26 2012
New Revision: 170947
URL: http://llvm.org/viewvc/llvm-project?rev=170947&view=rev
Log:
[mips] Remove unnecessary isPseudo parameter.
Modified:
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=170947&r1=170946&r2=170947&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Dec 21 16:57:26 2012
@@ -406,27 +406,22 @@
// Memory Load/Store
let canFoldAsLoad = 1 in
class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
- Operand MemOpnd, bit Pseudo>:
+ Operand MemOpnd>:
FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
!strconcat(instr_asm, "\t$rt, $addr"),
- [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
- let isPseudo = Pseudo;
-}
+ [(set RC:$rt, (OpNode addr:$addr))], IILoad>;
class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
- Operand MemOpnd, bit Pseudo>:
+ Operand MemOpnd>:
FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
!strconcat(instr_asm, "\t$rt, $addr"),
- [(OpNode RC:$rt, addr:$addr)], IIStore> {
- let isPseudo = Pseudo;
-}
+ [(OpNode RC:$rt, addr:$addr)], IIStore>;
// 32-bit load.
-multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
- bit Pseudo = 0> {
- def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
+multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode> {
+ def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem>,
Requires<[NotN64, HasStdEnc]>;
- def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
+ def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
@@ -434,11 +429,10 @@
}
// 64-bit load.
-multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
- bit Pseudo = 0> {
- def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
+multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode> {
+ def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem>,
Requires<[NotN64, HasStdEnc]>;
- def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
+ def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
@@ -446,11 +440,10 @@
}
// 32-bit store.
-multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
- bit Pseudo = 0> {
- def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
+multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode> {
+ def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem>,
Requires<[NotN64, HasStdEnc]>;
- def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
+ def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
@@ -458,11 +451,10 @@
}
// 64-bit store.
-multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
- bit Pseudo = 0> {
- def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
+multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode> {
+ def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem>,
Requires<[NotN64, HasStdEnc]>;
- def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
+ def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
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