[llvm-commits] [llvm] r170942 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsInstrFormats.td MipsInstrInfo.td

[Akira Hatanaka]

Author: ahatanak
Date: Fri Dec 21 16:43:58 2012
New Revision: 170942

URL: http://llvm.org/viewvc/llvm-project?rev=170942&view=rev
Log:
[mips] Refactor count leading zero or one instructions.


Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=170942&r1=170941&r2=170942&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Fri Dec 21 16:43:58 2012
@@ -196,8 +196,8 @@
 def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18>;
 
 /// Count Leading
-def DCLZ : CountLeading0<0x24, "dclz", CPU64Regs>;
-def DCLO : CountLeading1<0x25, "dclo", CPU64Regs>;
+def DCLZ : CountLeading0<"dclz", CPU64Regs>, CLO_FM<0x24>;
+def DCLO : CountLeading1<"dclo", CPU64Regs>, CLO_FM<0x25>;
 
 /// Double Word Swap Bytes/HalfWords
 def DSBH : SubwordSwap<0x24, 0x2, "dsbh", CPU64Regs>;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=170942&r1=170941&r2=170942&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Fri Dec 21 16:43:58 2012
@@ -340,6 +340,22 @@
   let Inst{5-0}   = 0x20;
 }
 
+class CLO_FM<bits<6> funct> {
+  bits<5> rd;
+  bits<5> rs;
+  bits<5> rt;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0x1c;
+  let Inst{25-21} = rs;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = rd;
+  let Inst{10-6}  = 0;
+  let Inst{5-0}   = funct;
+  let rt = rd;
+}
+
 //===----------------------------------------------------------------------===//
 //
 //  FLOATING POINT INSTRUCTION FORMATS

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=170942&r1=170941&r2=170942&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Dec 21 16:43:58 2012
@@ -684,23 +684,16 @@
 }
 
 // Count Leading Ones/Zeros in Word
-class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
-  FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
-     !strconcat(instr_asm, "\t$rd, $rs"),
-     [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
-     Requires<[HasBitCount, HasStdEnc]> {
-  let shamt = 0;
-  let rt = rd;
-}
+class CountLeading0<string opstr, RegisterClass RC>:
+  InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
+         [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>,
+  Requires<[HasBitCount, HasStdEnc]>;
+
+class CountLeading1<string opstr, RegisterClass RC>:
+  InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
+         [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>,
+  Requires<[HasBitCount, HasStdEnc]>;
 
-class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
-  FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
-     !strconcat(instr_asm, "\t$rd, $rs"),
-     [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
-     Requires<[HasBitCount, HasStdEnc]> {
-  let shamt = 0;
-  let rt = rd;
-}
 
 // Sign Extend in Register.
 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
@@ -966,8 +959,8 @@
 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18>;
 
 /// Count Leading
-def CLZ : CountLeading0<0x20, "clz", CPURegs>;
-def CLO : CountLeading1<0x21, "clo", CPURegs>;
+def CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>;
+def CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>;
 
 /// Word Swap Bytes Within Halfwords
 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;