[llvm-commits] [www-releases] r170845 [24/55] - in /www-releases/trunk/3.2/docs: ./ CommandGuide/ HistoricalNotes/ _static/ _templates/ _themes/ _themes/llvm-theme/ _themes/llvm-theme/static/ doxygen/ doxygen/html/ llvm-theme/ llvm-theme/static/ tutorial/
Tanya Lattner
tonic at nondot.org
Thu Dec 20 22:58:17 PST 2012
Added: www-releases/trunk/3.2/docs/doxygen/html/PPCISelLowering_8cpp_source.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.2/docs/doxygen/html/PPCISelLowering_8cpp_source.html?rev=170845&view=auto
==============================================================================
--- www-releases/trunk/3.2/docs/doxygen/html/PPCISelLowering_8cpp_source.html (added)
+++ www-releases/trunk/3.2/docs/doxygen/html/PPCISelLowering_8cpp_source.html Fri Dec 21 00:57:24 2012
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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+<meta name="description" content="C++ source code API documentation for LLVM."/>
+<title>LLVM: PPCISelLowering.cpp Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head><body>
+<p class="title">LLVM API Documentation</p>
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+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>File Members</span></a></li>
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+ <div id="nav-path" class="navpath">
+ <ul>
+ <li class="navelem"><a class="el" href="dir_b41d254693bea6e92988e5bb1ad97e02.html">llvm-3.2.src</a> </li>
+ <li class="navelem"><a class="el" href="dir_74e9364f374e99e3aeab4fae4e196292.html">lib</a> </li>
+ <li class="navelem"><a class="el" href="dir_8a55ec9894173378e0d08f27f306eeee.html">Target</a> </li>
+ <li class="navelem"><a class="el" href="dir_294e0a5f95410d4be44cdd50e2f548b0.html">PowerPC</a> </li>
+ </ul>
+ </div>
+</div>
+<div class="header">
+ <div class="headertitle">
+<div class="title">PPCISelLowering.cpp</div> </div>
+</div>
+<div class="contents">
+<a href="PPCISelLowering_8cpp.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file implements the PPCISelLowering class.</span>
+<a name="l00011"></a>00011 <span class="comment">//</span>
+<a name="l00012"></a>00012 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00013"></a>00013
+<a name="l00014"></a>00014 <span class="preprocessor">#include "<a class="code" href="PPCISelLowering_8h.html">PPCISelLowering.h</a>"</span>
+<a name="l00015"></a>00015 <span class="preprocessor">#include "<a class="code" href="PPCMachineFunctionInfo_8h.html">PPCMachineFunctionInfo.h</a>"</span>
+<a name="l00016"></a>00016 <span class="preprocessor">#include "<a class="code" href="PPCPerfectShuffle_8h.html">PPCPerfectShuffle.h</a>"</span>
+<a name="l00017"></a>00017 <span class="preprocessor">#include "<a class="code" href="PPCTargetMachine_8h.html">PPCTargetMachine.h</a>"</span>
+<a name="l00018"></a>00018 <span class="preprocessor">#include "<a class="code" href="PPCPredicates_8h.html">MCTargetDesc/PPCPredicates.h</a>"</span>
+<a name="l00019"></a>00019 <span class="preprocessor">#include "<a class="code" href="CallingConv_8h.html">llvm/CallingConv.h</a>"</span>
+<a name="l00020"></a>00020 <span class="preprocessor">#include "<a class="code" href="Constants_8h.html">llvm/Constants.h</a>"</span>
+<a name="l00021"></a>00021 <span class="preprocessor">#include "<a class="code" href="DerivedTypes_8h.html">llvm/DerivedTypes.h</a>"</span>
+<a name="l00022"></a>00022 <span class="preprocessor">#include "<a class="code" href="Function_8h.html">llvm/Function.h</a>"</span>
+<a name="l00023"></a>00023 <span class="preprocessor">#include "<a class="code" href="Intrinsics_8h.html">llvm/Intrinsics.h</a>"</span>
+<a name="l00024"></a>00024 <span class="preprocessor">#include "<a class="code" href="STLExtras_8h.html">llvm/ADT/STLExtras.h</a>"</span>
+<a name="l00025"></a>00025 <span class="preprocessor">#include "<a class="code" href="CallingConvLower_8h.html">llvm/CodeGen/CallingConvLower.h</a>"</span>
+<a name="l00026"></a>00026 <span class="preprocessor">#include "<a class="code" href="MachineFrameInfo_8h.html">llvm/CodeGen/MachineFrameInfo.h</a>"</span>
+<a name="l00027"></a>00027 <span class="preprocessor">#include "<a class="code" href="MachineFunction_8h.html">llvm/CodeGen/MachineFunction.h</a>"</span>
+<a name="l00028"></a>00028 <span class="preprocessor">#include "<a class="code" href="MachineInstrBuilder_8h.html">llvm/CodeGen/MachineInstrBuilder.h</a>"</span>
+<a name="l00029"></a>00029 <span class="preprocessor">#include "<a class="code" href="MachineRegisterInfo_8h.html">llvm/CodeGen/MachineRegisterInfo.h</a>"</span>
+<a name="l00030"></a>00030 <span class="preprocessor">#include "<a class="code" href="SelectionDAG_8h.html">llvm/CodeGen/SelectionDAG.h</a>"</span>
+<a name="l00031"></a>00031 <span class="preprocessor">#include "<a class="code" href="TargetLoweringObjectFileImpl_8h.html">llvm/CodeGen/TargetLoweringObjectFileImpl.h</a>"</span>
+<a name="l00032"></a>00032 <span class="preprocessor">#include "<a class="code" href="CommandLine_8h.html">llvm/Support/CommandLine.h</a>"</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#include "<a class="code" href="ErrorHandling_8h.html">llvm/Support/ErrorHandling.h</a>"</span>
+<a name="l00034"></a>00034 <span class="preprocessor">#include "<a class="code" href="MathExtras_8h.html">llvm/Support/MathExtras.h</a>"</span>
+<a name="l00035"></a>00035 <span class="preprocessor">#include "<a class="code" href="raw__ostream_8h.html">llvm/Support/raw_ostream.h</a>"</span>
+<a name="l00036"></a>00036 <span class="preprocessor">#include "<a class="code" href="TargetOptions_8h.html">llvm/Target/TargetOptions.h</a>"</span>
+<a name="l00037"></a>00037 <span class="keyword">using namespace </span>llvm;
+<a name="l00038"></a>00038
+<a name="l00039"></a>00039 <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#a4681e9291a864ce414f99b9993fa1c4f">CC_PPC_SVR4_Custom_Dummy</a>(<span class="keywordtype">unsigned</span> &ValNo, <a class="code" href="classllvm_1_1MVT.html">MVT</a> &ValVT, <a class="code" href="classllvm_1_1MVT.html">MVT</a> &LocVT,
+<a name="l00040"></a>00040 <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45">CCValAssign::LocInfo</a> &LocInfo,
+<a name="l00041"></a>00041 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> &ArgFlags,
+<a name="l00042"></a>00042 <a class="code" href="classllvm_1_1CCState.html">CCState</a> &State);
+<a name="l00043"></a>00043 <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#a39f14542b4ad3861660fea58481d7409">CC_PPC_SVR4_Custom_AlignArgRegs</a>(<span class="keywordtype">unsigned</span> &ValNo, <a class="code" href="classllvm_1_1MVT.html">MVT</a> &ValVT,
+<a name="l00044"></a>00044 <a class="code" href="classllvm_1_1MVT.html">MVT</a> &LocVT,
+<a name="l00045"></a>00045 <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45">CCValAssign::LocInfo</a> &LocInfo,
+<a name="l00046"></a>00046 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> &ArgFlags,
+<a name="l00047"></a>00047 <a class="code" href="classllvm_1_1CCState.html">CCState</a> &State);
+<a name="l00048"></a>00048 <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#af90d91f7fcb6fe7789fd8d9a8641f7e4">CC_PPC_SVR4_Custom_AlignFPArgRegs</a>(<span class="keywordtype">unsigned</span> &ValNo, <a class="code" href="classllvm_1_1MVT.html">MVT</a> &ValVT,
+<a name="l00049"></a>00049 <a class="code" href="classllvm_1_1MVT.html">MVT</a> &LocVT,
+<a name="l00050"></a>00050 <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45">CCValAssign::LocInfo</a> &LocInfo,
+<a name="l00051"></a>00051 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> &ArgFlags,
+<a name="l00052"></a>00052 <a class="code" href="classllvm_1_1CCState.html">CCState</a> &State);
+<a name="l00053"></a>00053
+<a name="l00054"></a>00054 <span class="keyword">static</span> <a class="code" href="classllvm_1_1cl_1_1opt.html">cl::opt<bool></a> <a class="code" href="PPCISelLowering_8cpp.html#a39032b11b8339a15cd3c828db23000fb">DisablePPCPreinc</a>(<span class="stringliteral">"disable-ppc-preinc"</span>,
+<a name="l00055"></a>00055 <a class="code" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>(<span class="stringliteral">"disable preincrement load/store generation on PPC"</span>), <a class="code" href="namespacellvm_1_1cl.html#a68075925a54790e71ca790e1d4f21a40a263ac008d8d31f13ce460395fc4cf7e6">cl::Hidden</a>);
+<a name="l00056"></a>00056
+<a name="l00057"></a>00057 <span class="keyword">static</span> <a class="code" href="classllvm_1_1cl_1_1opt.html">cl::opt<bool></a> <a class="code" href="PPCISelLowering_8cpp.html#ae8df7699f069ce76cf9c5d988b4319d3">DisableILPPref</a>(<span class="stringliteral">"disable-ppc-ilp-pref"</span>,
+<a name="l00058"></a>00058 <a class="code" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>(<span class="stringliteral">"disable setting the node scheduling preference to ILP on PPC"</span>), <a class="code" href="namespacellvm_1_1cl.html#a68075925a54790e71ca790e1d4f21a40a263ac008d8d31f13ce460395fc4cf7e6">cl::Hidden</a>);
+<a name="l00059"></a>00059
+<a name="l00060"></a><a class="code" href="PPCISelLowering_8cpp.html#a631c3222757cd088edf4ba738fdf908c">00060</a> <span class="keyword">static</span> <a class="code" href="classllvm_1_1TargetLoweringObjectFile.html">TargetLoweringObjectFile</a> *<a class="code" href="PPCISelLowering_8cpp.html#a631c3222757cd088edf4ba738fdf908c">CreateTLOF</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCTargetMachine.html">PPCTargetMachine</a> &TM) {
+<a name="l00061"></a>00061 <span class="keywordflow">if</span> (TM.<a class="code" href="classllvm_1_1PPCTargetMachine.html#a19468aad6e69c24f158cadf2e3ac95d3">getSubtargetImpl</a>()-><a class="code" href="classllvm_1_1PPCSubtarget.html#abf861b7eababe28400eb7d5b3519f18f" title="isDarwin - True if this is any darwin platform.">isDarwin</a>())
+<a name="l00062"></a>00062 <span class="keywordflow">return</span> <span class="keyword">new</span> <a class="code" href="classllvm_1_1TargetLoweringObjectFileMachO.html">TargetLoweringObjectFileMachO</a>();
+<a name="l00063"></a>00063
+<a name="l00064"></a>00064 <span class="keywordflow">return</span> <span class="keyword">new</span> <a class="code" href="classllvm_1_1TargetLoweringObjectFileELF.html">TargetLoweringObjectFileELF</a>();
+<a name="l00065"></a>00065 }
+<a name="l00066"></a>00066
+<a name="l00067"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#a840de59c43fdd3160c0811cea581814e">00067</a> <a class="code" href="classllvm_1_1PPCTargetLowering.html#a840de59c43fdd3160c0811cea581814e">PPCTargetLowering::PPCTargetLowering</a>(<a class="code" href="classllvm_1_1PPCTargetMachine.html">PPCTargetMachine</a> &TM)
+<a name="l00068"></a>00068 : <a class="code" href="classllvm_1_1TargetLowering.html">TargetLowering</a>(TM, <a class="code" href="PPCISelLowering_8cpp.html#a631c3222757cd088edf4ba738fdf908c">CreateTLOF</a>(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
+<a name="l00069"></a>00069 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a> *Subtarget = &TM.<a class="code" href="classllvm_1_1TargetMachine.html#a5af2fed99951774b6a14d30ec6e73792">getSubtarget</a><<a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a>>();
+<a name="l00070"></a>00070
+<a name="l00071"></a>00071 <a class="code" href="classllvm_1_1TargetLowering.html#a7a24b0f1cf6150726504a8c92b54f659">setPow2DivIsCheap</a>();
+<a name="l00072"></a>00072
+<a name="l00073"></a>00073 <span class="comment">// Use _setjmp/_longjmp instead of setjmp/longjmp.</span>
+<a name="l00074"></a>00074 <a class="code" href="classllvm_1_1TargetLowering.html#af4a9000fcfb5de9e706332d13c87acea">setUseUnderscoreSetJmp</a>(<span class="keyword">true</span>);
+<a name="l00075"></a>00075 <a class="code" href="classllvm_1_1TargetLowering.html#a8d74dbc1e17c8f627cba83437694c61a">setUseUnderscoreLongJmp</a>(<span class="keyword">true</span>);
+<a name="l00076"></a>00076
+<a name="l00077"></a>00077 <span class="comment">// On PPC32/64, arguments smaller than 4/8 bytes are extended, so all</span>
+<a name="l00078"></a>00078 <span class="comment">// arguments are at least 4/8 bytes aligned.</span>
+<a name="l00079"></a>00079 <span class="keywordtype">bool</span> isPPC64 = Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>();
+<a name="l00080"></a>00080 <a class="code" href="classllvm_1_1TargetLowering.html#a11e319c9e2e1cf1c61d30b1e68372add">setMinStackArgumentAlignment</a>(isPPC64 ? 8:4);
+<a name="l00081"></a>00081
+<a name="l00082"></a>00082 <span class="comment">// Set up the register classes.</span>
+<a name="l00083"></a>00083 <a class="code" href="classllvm_1_1TargetLowering.html#a3c9f9db4814d0797586e65bebb09559d">addRegisterClass</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, &PPC::GPRCRegClass);
+<a name="l00084"></a>00084 <a class="code" href="classllvm_1_1TargetLowering.html#a3c9f9db4814d0797586e65bebb09559d">addRegisterClass</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, &PPC::F4RCRegClass);
+<a name="l00085"></a>00085 <a class="code" href="classllvm_1_1TargetLowering.html#a3c9f9db4814d0797586e65bebb09559d">addRegisterClass</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, &PPC::F8RCRegClass);
+<a name="l00086"></a>00086
+<a name="l00087"></a>00087 <span class="comment">// PowerPC has an i16 but no i8 (or i1) SEXTLOAD</span>
+<a name="l00088"></a>00088 <a class="code" href="classllvm_1_1TargetLowering.html#ae4ac865451dca0c871bed2f413a05aa2">setLoadExtAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00089"></a>00089 <a class="code" href="classllvm_1_1TargetLowering.html#ae4ac865451dca0c871bed2f413a05aa2">setLoadExtAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00090"></a>00090
+<a name="l00091"></a>00091 <a class="code" href="classllvm_1_1TargetLowering.html#ad6f72f4fa4e7fde53ecde15fa5563433">setTruncStoreAction</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00092"></a>00092
+<a name="l00093"></a>00093 <span class="comment">// PowerPC has pre-inc load and store's.</span>
+<a name="l00094"></a>00094 <a class="code" href="classllvm_1_1TargetLowering.html#aff16f11c3d3b828741a23d0882728053">setIndexedLoadAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00095"></a>00095 <a class="code" href="classllvm_1_1TargetLowering.html#aff16f11c3d3b828741a23d0882728053">setIndexedLoadAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00096"></a>00096 <a class="code" href="classllvm_1_1TargetLowering.html#aff16f11c3d3b828741a23d0882728053">setIndexedLoadAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00097"></a>00097 <a class="code" href="classllvm_1_1TargetLowering.html#aff16f11c3d3b828741a23d0882728053">setIndexedLoadAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00098"></a>00098 <a class="code" href="classllvm_1_1TargetLowering.html#aff16f11c3d3b828741a23d0882728053">setIndexedLoadAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00099"></a>00099 <a class="code" href="classllvm_1_1TargetLowering.html#adca6d54a9d5611b9e50c004b7cdd2232">setIndexedStoreAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00100"></a>00100 <a class="code" href="classllvm_1_1TargetLowering.html#adca6d54a9d5611b9e50c004b7cdd2232">setIndexedStoreAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00101"></a>00101 <a class="code" href="classllvm_1_1TargetLowering.html#adca6d54a9d5611b9e50c004b7cdd2232">setIndexedStoreAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00102"></a>00102 <a class="code" href="classllvm_1_1TargetLowering.html#adca6d54a9d5611b9e50c004b7cdd2232">setIndexedStoreAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00103"></a>00103 <a class="code" href="classllvm_1_1TargetLowering.html#adca6d54a9d5611b9e50c004b7cdd2232">setIndexedStoreAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00104"></a>00104
+<a name="l00105"></a>00105 <span class="comment">// This is used in the ppcf128->int sequence. Note it has different semantics</span>
+<a name="l00106"></a>00106 <span class="comment">// from FP_ROUND: that rounds to nearest, this rounds to zero.</span>
+<a name="l00107"></a>00107 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8745901e68ed76ceaf48791715cefcb4">ISD::FP_ROUND_INREG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00108"></a>00108
+<a name="l00109"></a>00109 <span class="comment">// We do not currently implement these libm ops for PowerPC.</span>
+<a name="l00110"></a>00110 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4336c27826676e1ef61383cafa999219">ISD::FFLOOR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00111"></a>00111 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad56e9199ae3993a09af36ff41d327a11">ISD::FCEIL</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00112"></a>00112 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1e92ea554489509b0ad970901bcc715b">ISD::FTRUNC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00113"></a>00113 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a68014623710f7a44c808cd412236d6a1">ISD::FRINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00114"></a>00114 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a2dc876d6cc16ac04376483552292f9f4">ISD::FNEARBYINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00115"></a>00115
+<a name="l00116"></a>00116 <span class="comment">// PowerPC has no SREM/UREM instructions</span>
+<a name="l00117"></a>00117 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a124ba0f5b2887879212c74a68bc230a3">ISD::SREM</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00118"></a>00118 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad1657dbc1957901a6d9cd224efbc0f28">ISD::UREM</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00119"></a>00119 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a124ba0f5b2887879212c74a68bc230a3">ISD::SREM</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00120"></a>00120 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad1657dbc1957901a6d9cd224efbc0f28">ISD::UREM</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00121"></a>00121
+<a name="l00122"></a>00122 <span class="comment">// Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.</span>
+<a name="l00123"></a>00123 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a79c959df09509d7ff66d9b04bc40d18d">ISD::UMUL_LOHI</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00124"></a>00124 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1354c6f8508d6cd697dc89a5d9a52dfd">ISD::SMUL_LOHI</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00125"></a>00125 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a79c959df09509d7ff66d9b04bc40d18d">ISD::UMUL_LOHI</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00126"></a>00126 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1354c6f8508d6cd697dc89a5d9a52dfd">ISD::SMUL_LOHI</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00127"></a>00127 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3a257ffa49107e2db978e8a6e2688ada">ISD::UDIVREM</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00128"></a>00128 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3a874f66e1efe5be79552bbe7ee3121a">ISD::SDIVREM</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00129"></a>00129 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3a257ffa49107e2db978e8a6e2688ada">ISD::UDIVREM</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00130"></a>00130 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3a874f66e1efe5be79552bbe7ee3121a">ISD::SDIVREM</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00131"></a>00131
+<a name="l00132"></a>00132 <span class="comment">// We don't support sin/cos/sqrt/fmod/pow</span>
+<a name="l00133"></a>00133 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad46ae9fdfe20cd04f7fda7ccbb937543">ISD::FSIN</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00134"></a>00134 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9133d7cfb6a66404ff7757b699bc3941">ISD::FCOS</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00135"></a>00135 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110abdd7bbb76dac7962dda6e116e33699da">ISD::FREM</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00136"></a>00136 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1a6952b1572a4ce241cc3cf45a9ab071">ISD::FPOW</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00137"></a>00137 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a293ca68b3b2ce80eef991de822822254">ISD::FMA</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00138"></a>00138 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad46ae9fdfe20cd04f7fda7ccbb937543">ISD::FSIN</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00139"></a>00139 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9133d7cfb6a66404ff7757b699bc3941">ISD::FCOS</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00140"></a>00140 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110abdd7bbb76dac7962dda6e116e33699da">ISD::FREM</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00141"></a>00141 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1a6952b1572a4ce241cc3cf45a9ab071">ISD::FPOW</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00142"></a>00142 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a293ca68b3b2ce80eef991de822822254">ISD::FMA</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00143"></a>00143
+<a name="l00144"></a>00144 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a06a1a0916d630a342fc3c355b0de8eab">ISD::FLT_ROUNDS_</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00145"></a>00145
+<a name="l00146"></a>00146 <span class="comment">// If we're enabling GP optimizations, use hardware square root</span>
+<a name="l00147"></a>00147 <span class="keywordflow">if</span> (!Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#a1fcd7b93a56527b2e92a8fadd753ad2a">hasFSQRT</a>()) {
+<a name="l00148"></a>00148 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae1118ddac1ce0af8e9f7cc16c9e94fc0">ISD::FSQRT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00149"></a>00149 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae1118ddac1ce0af8e9f7cc16c9e94fc0">ISD::FSQRT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00150"></a>00150 }
+<a name="l00151"></a>00151
+<a name="l00152"></a>00152 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aeffc3319657e213a530ce583603f7221">ISD::FCOPYSIGN</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00153"></a>00153 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aeffc3319657e213a530ce583603f7221">ISD::FCOPYSIGN</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00154"></a>00154
+<a name="l00155"></a>00155 <span class="comment">// PowerPC does not have BSWAP, CTPOP or CTTZ</span>
+<a name="l00156"></a>00156 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a19328c462764af5f4699fb1698dad994" title="Byte Swap and Counting operators.">ISD::BSWAP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00157"></a>00157 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a991d07d163bd4d9984cf1ef36e92c214">ISD::CTPOP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00158"></a>00158 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6da41a113af0909470baea7486b3386b">ISD::CTTZ</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00159"></a>00159 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a601e66a26efd05520f7cb26aef3af340" title="Bit counting operators with an undefined result for zero inputs.">ISD::CTTZ_ZERO_UNDEF</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00160"></a>00160 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0340c8d57d1dcebc43a00412989583d3">ISD::CTLZ_ZERO_UNDEF</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00161"></a>00161 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a19328c462764af5f4699fb1698dad994" title="Byte Swap and Counting operators.">ISD::BSWAP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00162"></a>00162 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a991d07d163bd4d9984cf1ef36e92c214">ISD::CTPOP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00163"></a>00163 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6da41a113af0909470baea7486b3386b">ISD::CTTZ</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00164"></a>00164 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a601e66a26efd05520f7cb26aef3af340" title="Bit counting operators with an undefined result for zero inputs.">ISD::CTTZ_ZERO_UNDEF</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00165"></a>00165 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0340c8d57d1dcebc43a00412989583d3">ISD::CTLZ_ZERO_UNDEF</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00166"></a>00166
+<a name="l00167"></a>00167 <span class="comment">// PowerPC does not have ROTR</span>
+<a name="l00168"></a>00168 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a19cd524269b035941434cce28b585715">ISD::ROTR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00169"></a>00169 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a19cd524269b035941434cce28b585715">ISD::ROTR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00170"></a>00170
+<a name="l00171"></a>00171 <span class="comment">// PowerPC does not have Select</span>
+<a name="l00172"></a>00172 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00173"></a>00173 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00174"></a>00174 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00175"></a>00175 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00176"></a>00176
+<a name="l00177"></a>00177 <span class="comment">// PowerPC wants to turn select_cc of FP into fsel when possible.</span>
+<a name="l00178"></a>00178 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a99ad6b342b7457df56b91d24e66016b3">ISD::SELECT_CC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00179"></a>00179 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a99ad6b342b7457df56b91d24e66016b3">ISD::SELECT_CC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00180"></a>00180
+<a name="l00181"></a>00181 <span class="comment">// PowerPC wants to optimize integer setcc a bit</span>
+<a name="l00182"></a>00182 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0158ee47dfa868be5d28e2cbef70d5d0">ISD::SETCC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00183"></a>00183
+<a name="l00184"></a>00184 <span class="comment">// PowerPC does not have BRCOND which requires SetCC</span>
+<a name="l00185"></a>00185 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae8167e4f6fa1bfb30f074ba620b81782">ISD::BRCOND</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00186"></a>00186
+<a name="l00187"></a>00187 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a716d19ebad1927a2e8dd5fe3f951f882">ISD::BR_JT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00188"></a>00188
+<a name="l00189"></a>00189 <span class="comment">// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.</span>
+<a name="l00190"></a>00190 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac3f8f8d8437c64b2e2e9f978e2707210">ISD::FP_TO_SINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00191"></a>00191
+<a name="l00192"></a>00192 <span class="comment">// PowerPC does not have [U|S]INT_TO_FP</span>
+<a name="l00193"></a>00193 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a315004656a75a3c3a9d7294f105a8da2">ISD::SINT_TO_FP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00194"></a>00194 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a169032eecd015d4eeb869c457202a6c8">ISD::UINT_TO_FP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00195"></a>00195
+<a name="l00196"></a>00196 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00197"></a>00197 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00198"></a>00198 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00199"></a>00199 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00200"></a>00200
+<a name="l00201"></a>00201 <span class="comment">// We cannot sextinreg(i1). Expand to shifts.</span>
+<a name="l00202"></a>00202 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aaa59dd5ec37f21905436b354c0292d9e">ISD::SIGN_EXTEND_INREG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00203"></a>00203
+<a name="l00204"></a>00204 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6259032ff84d3fdad80a57aad4da9b85">ISD::EXCEPTIONADDR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00205"></a>00205 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a565eb54f2492c02ad71732d7fc7934b9">ISD::EHSELECTION</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00206"></a>00206 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6259032ff84d3fdad80a57aad4da9b85">ISD::EXCEPTIONADDR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00207"></a>00207 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a565eb54f2492c02ad71732d7fc7934b9">ISD::EHSELECTION</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00208"></a>00208
+<a name="l00209"></a>00209
+<a name="l00210"></a>00210 <span class="comment">// We want to legalize GlobalAddress and ConstantPool nodes into the</span>
+<a name="l00211"></a>00211 <span class="comment">// appropriate instructions to materialize the address.</span>
+<a name="l00212"></a>00212 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a30316f8f9985260c49d7c26bc70a6cad">ISD::GlobalAddress</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00213"></a>00213 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a49f1172c7014cc4fa3570792e6834e2c">ISD::GlobalTLSAddress</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00214"></a>00214 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae98378a8672947382d343d75a5df3003">ISD::BlockAddress</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00215"></a>00215 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aa8cad208c3cb96b33b5d8544590325b1">ISD::ConstantPool</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00216"></a>00216 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0c70100db6ddc0b37b56feb242145cf4">ISD::JumpTable</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00217"></a>00217 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a30316f8f9985260c49d7c26bc70a6cad">ISD::GlobalAddress</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00218"></a>00218 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a49f1172c7014cc4fa3570792e6834e2c">ISD::GlobalTLSAddress</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00219"></a>00219 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae98378a8672947382d343d75a5df3003">ISD::BlockAddress</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00220"></a>00220 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aa8cad208c3cb96b33b5d8544590325b1">ISD::ConstantPool</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00221"></a>00221 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0c70100db6ddc0b37b56feb242145cf4">ISD::JumpTable</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00222"></a>00222
+<a name="l00223"></a>00223 <span class="comment">// TRAP is legal.</span>
+<a name="l00224"></a>00224 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac5fb8808f3dcb9f0a83f1fc2e7747485" title="TRAP - Trapping instruction.">ISD::TRAP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00225"></a>00225
+<a name="l00226"></a>00226 <span class="comment">// TRAMPOLINE is custom lowered.</span>
+<a name="l00227"></a>00227 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4534a6db2862a28324932a8ea1cb54d6">ISD::INIT_TRAMPOLINE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00228"></a>00228 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110af7bfad446dfd85837fe7ff904ebb1aff">ISD::ADJUST_TRAMPOLINE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00229"></a>00229
+<a name="l00230"></a>00230 <span class="comment">// VASTART needs to be custom lowered to use the VarArgsFrameIndex</span>
+<a name="l00231"></a>00231 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110adfe32beaa596a1512b17e66b46e773ed">ISD::VASTART</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00232"></a>00232
+<a name="l00233"></a>00233 <span class="keywordflow">if</span> (Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>()) {
+<a name="l00234"></a>00234 <span class="keywordflow">if</span> (isPPC64) {
+<a name="l00235"></a>00235 <span class="comment">// VAARG always uses double-word chunks, so promote anything smaller.</span>
+<a name="l00236"></a>00236 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00237"></a>00237 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l00238"></a>00238 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00239"></a>00239 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l00240"></a>00240 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00241"></a>00241 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l00242"></a>00242 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00243"></a>00243 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l00244"></a>00244 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00245"></a>00245 } <span class="keywordflow">else</span> {
+<a name="l00246"></a>00246 <span class="comment">// VAARG is custom lowered with the 32-bit SVR4 ABI.</span>
+<a name="l00247"></a>00247 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00248"></a>00248 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00249"></a>00249 }
+<a name="l00250"></a>00250 } <span class="keywordflow">else</span>
+<a name="l00251"></a>00251 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00252"></a>00252
+<a name="l00253"></a>00253 <span class="comment">// Use the default implementation.</span>
+<a name="l00254"></a>00254 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a804c1960ac64628cdd1f74d7de885284">ISD::VACOPY</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00255"></a>00255 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1aadbb14ab26b74d841ac003363e3a5d">ISD::VAEND</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00256"></a>00256 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a031ce694e40832d40a163d7254a8df14">ISD::STACKSAVE</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00257"></a>00257 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a023a9de787026fe61b024476bf9c32cb">ISD::STACKRESTORE</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00258"></a>00258 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aa71ac22470bf853868fe6b39a25bac72">ISD::DYNAMIC_STACKALLOC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00259"></a>00259 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aa71ac22470bf853868fe6b39a25bac72">ISD::DYNAMIC_STACKALLOC</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> , <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00260"></a>00260
+<a name="l00261"></a>00261 <span class="comment">// We want to custom lower some of our intrinsics.</span>
+<a name="l00262"></a>00262 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac771b9cda3b889242d457cc4d9b2159c">ISD::INTRINSIC_WO_CHAIN</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00263"></a>00263
+<a name="l00264"></a>00264 <span class="comment">// Comparisons that require checking two conditions.</span>
+<a name="l00265"></a>00265 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00266"></a>00266 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00267"></a>00267 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00268"></a>00268 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00269"></a>00269 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0deb50cd2f3f8e4a94eef4cdf769b848">ISD::SETUEQ</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00270"></a>00270 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0deb50cd2f3f8e4a94eef4cdf769b848">ISD::SETUEQ</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00271"></a>00271 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac7bb30d4918c1ee9dd208083154e109f">ISD::SETOGE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00272"></a>00272 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac7bb30d4918c1ee9dd208083154e109f">ISD::SETOGE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00273"></a>00273 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a1febf3bac2f3d7d98ec19f1ff5c385ea">ISD::SETOLE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00274"></a>00274 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a1febf3bac2f3d7d98ec19f1ff5c385ea">ISD::SETOLE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00275"></a>00275 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a57c68bf7ef20bd558854a24d5b0c1e72">ISD::SETONE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00276"></a>00276 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a57c68bf7ef20bd558854a24d5b0c1e72">ISD::SETONE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00277"></a>00277
+<a name="l00278"></a>00278 <span class="keywordflow">if</span> (Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#a011454ea07a73444b499f0b8bb35fa37">has64BitSupport</a>()) {
+<a name="l00279"></a>00279 <span class="comment">// They also have instructions for converting between i64 and fp.</span>
+<a name="l00280"></a>00280 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac3f8f8d8437c64b2e2e9f978e2707210">ISD::FP_TO_SINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00281"></a>00281 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a71640703ec096a8b07111e85cfff6987">ISD::FP_TO_UINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00282"></a>00282 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a315004656a75a3c3a9d7294f105a8da2">ISD::SINT_TO_FP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00283"></a>00283 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a169032eecd015d4eeb869c457202a6c8">ISD::UINT_TO_FP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00284"></a>00284 <span class="comment">// This is just the low 32 bits of a (signed) fp->i64 conversion.</span>
+<a name="l00285"></a>00285 <span class="comment">// We cannot do this with Promote because i64 is not a legal type.</span>
+<a name="l00286"></a>00286 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a71640703ec096a8b07111e85cfff6987">ISD::FP_TO_UINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00287"></a>00287
+<a name="l00288"></a>00288 <span class="comment">// FIXME: disable this lowered code. This generates 64-bit register values,</span>
+<a name="l00289"></a>00289 <span class="comment">// and we don't model the fact that the top part is clobbered by calls. We</span>
+<a name="l00290"></a>00290 <span class="comment">// need to flag these together so that the value isn't live across a call.</span>
+<a name="l00291"></a>00291 <span class="comment">//setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);</span>
+<a name="l00292"></a>00292 } <span class="keywordflow">else</span> {
+<a name="l00293"></a>00293 <span class="comment">// PowerPC does not have FP_TO_UINT on 32-bit implementations.</span>
+<a name="l00294"></a>00294 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a71640703ec096a8b07111e85cfff6987">ISD::FP_TO_UINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00295"></a>00295 }
+<a name="l00296"></a>00296
+<a name="l00297"></a>00297 <span class="keywordflow">if</span> (Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#ac9b52e4b6f9d3dab8595d4eb36fe2b7a">use64BitRegs</a>()) {
+<a name="l00298"></a>00298 <span class="comment">// 64-bit PowerPC implementations can support i64 types directly</span>
+<a name="l00299"></a>00299 <a class="code" href="classllvm_1_1TargetLowering.html#a3c9f9db4814d0797586e65bebb09559d">addRegisterClass</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, &PPC::G8RCRegClass);
+<a name="l00300"></a>00300 <span class="comment">// BUILD_PAIR can't be handled natively, and should be expanded to shl/or</span>
+<a name="l00301"></a>00301 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a41bd84b853e2c03fb1af1f4ca9ebdcaf">ISD::BUILD_PAIR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00302"></a>00302 <span class="comment">// 64-bit PowerPC wants to expand i128 shifts itself.</span>
+<a name="l00303"></a>00303 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aeb80f9832dad739ee9c6deaa3110d98f">ISD::SHL_PARTS</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00304"></a>00304 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78139be59781ad05e1698eb95c58e0b1">ISD::SRA_PARTS</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00305"></a>00305 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9ed8e1dc0db59ab2a071da53ee794759">ISD::SRL_PARTS</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00306"></a>00306 } <span class="keywordflow">else</span> {
+<a name="l00307"></a>00307 <span class="comment">// 32-bit PowerPC wants to expand i64 shifts itself.</span>
+<a name="l00308"></a>00308 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aeb80f9832dad739ee9c6deaa3110d98f">ISD::SHL_PARTS</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00309"></a>00309 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78139be59781ad05e1698eb95c58e0b1">ISD::SRA_PARTS</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00310"></a>00310 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9ed8e1dc0db59ab2a071da53ee794759">ISD::SRL_PARTS</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00311"></a>00311 }
+<a name="l00312"></a>00312
+<a name="l00313"></a>00313 <span class="keywordflow">if</span> (Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#a48acc37c623a6d5e12a3a262077ffe35">hasAltivec</a>()) {
+<a name="l00314"></a>00314 <span class="comment">// First set operation action for all vector types to expand. Then we</span>
+<a name="l00315"></a>00315 <span class="comment">// will selectively turn on ones that can be effectively codegen'd.</span>
+<a name="l00316"></a>00316 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = (<span class="keywordtype">unsigned</span>)<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae95173386f40dde17d7ae56a7bdd416e">MVT::FIRST_VECTOR_VALUETYPE</a>;
+<a name="l00317"></a>00317 i <= (<a class="code" href="classunsigned.html">unsigned</a>)<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac70c1ab4641d55854fdc2d7b7d40350f">MVT::LAST_VECTOR_VALUETYPE</a>; ++i) {
+<a name="l00318"></a>00318 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a> VT = (<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a>)i;
+<a name="l00319"></a>00319
+<a name="l00320"></a>00320 <span class="comment">// add/sub are legal for all supported vector VT's.</span>
+<a name="l00321"></a>00321 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> , VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00322"></a>00322 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> , VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00323"></a>00323
+<a name="l00324"></a>00324 <span class="comment">// We promote all shuffles to v16i8.</span>
+<a name="l00325"></a>00325 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8d8773b28111d8898663d4a0f6223d68">ISD::VECTOR_SHUFFLE</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00326"></a>00326 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8d8773b28111d8898663d4a0f6223d68">ISD::VECTOR_SHUFFLE</a>, VT, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>);
+<a name="l00327"></a>00327
+<a name="l00328"></a>00328 <span class="comment">// We promote all non-typed operations to v4i32.</span>
+<a name="l00329"></a>00329 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a> , VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00330"></a>00330 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a> , VT, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>);
+<a name="l00331"></a>00331 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a> , VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00332"></a>00332 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a> , VT, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>);
+<a name="l00333"></a>00333 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a> , VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00334"></a>00334 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a> , VT, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>);
+<a name="l00335"></a>00335 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a> , VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00336"></a>00336 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a> , VT, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>);
+<a name="l00337"></a>00337 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00338"></a>00338 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, VT, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>);
+<a name="l00339"></a>00339 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a047178c3b2c6a5df40ae22a407b8aca9">ISD::STORE</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbaf8cfab91a9fc402ca794d6079674ccfc">Promote</a>);
+<a name="l00340"></a>00340 <a class="code" href="classllvm_1_1TargetLowering.html#af00f75e0890a335122c89fcba0d7807a">AddPromotedToType</a> (<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a047178c3b2c6a5df40ae22a407b8aca9">ISD::STORE</a>, VT, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>);
+<a name="l00341"></a>00341
+<a name="l00342"></a>00342 <span class="comment">// No other operations are legal.</span>
+<a name="l00343"></a>00343 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a> , VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00344"></a>00344 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1f61c2422057e10403b2f6003543c300">ISD::SDIV</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00345"></a>00345 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a124ba0f5b2887879212c74a68bc230a3">ISD::SREM</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00346"></a>00346 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a15637879021fa7d5226045c0668a99a8">ISD::UDIV</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00347"></a>00347 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad1657dbc1957901a6d9cd224efbc0f28">ISD::UREM</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00348"></a>00348 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110abc6c09c7af98236460f0b020eb3be94e">ISD::FDIV</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00349"></a>00349 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6d26c45c040d8f85d577a5f645261d1a">ISD::FNEG</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00350"></a>00350 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9329e79f62e9ab9b41cfbcafd314bcbd">ISD::EXTRACT_VECTOR_ELT</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00351"></a>00351 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad3bc7c2d379fbfdc2f8eaca038690ec9">ISD::INSERT_VECTOR_ELT</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00352"></a>00352 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00353"></a>00353 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a79c959df09509d7ff66d9b04bc40d18d">ISD::UMUL_LOHI</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00354"></a>00354 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1354c6f8508d6cd697dc89a5d9a52dfd">ISD::SMUL_LOHI</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00355"></a>00355 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3a257ffa49107e2db978e8a6e2688ada">ISD::UDIVREM</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00356"></a>00356 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3a874f66e1efe5be79552bbe7ee3121a">ISD::SDIVREM</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00357"></a>00357 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a576080a08ef1bbab0308eac9d5838f75">ISD::SCALAR_TO_VECTOR</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00358"></a>00358 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1a6952b1572a4ce241cc3cf45a9ab071">ISD::FPOW</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00359"></a>00359 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a991d07d163bd4d9984cf1ef36e92c214">ISD::CTPOP</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00360"></a>00360 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110add33c0ae9a63902e573fc1f92fc33f1c">ISD::CTLZ</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00361"></a>00361 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0340c8d57d1dcebc43a00412989583d3">ISD::CTLZ_ZERO_UNDEF</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00362"></a>00362 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6da41a113af0909470baea7486b3386b">ISD::CTTZ</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00363"></a>00363 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a601e66a26efd05520f7cb26aef3af340" title="Bit counting operators with an undefined result for zero inputs.">ISD::CTTZ_ZERO_UNDEF</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00364"></a>00364 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aaa59dd5ec37f21905436b354c0292d9e">ISD::SIGN_EXTEND_INREG</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00365"></a>00365
+<a name="l00366"></a>00366 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j = (<span class="keywordtype">unsigned</span>)<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae95173386f40dde17d7ae56a7bdd416e">MVT::FIRST_VECTOR_VALUETYPE</a>;
+<a name="l00367"></a>00367 j <= (<a class="code" href="classunsigned.html">unsigned</a>)<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac70c1ab4641d55854fdc2d7b7d40350f">MVT::LAST_VECTOR_VALUETYPE</a>; ++j) {
+<a name="l00368"></a>00368 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a> InnerVT = (<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a>)j;
+<a name="l00369"></a>00369 <a class="code" href="classllvm_1_1TargetLowering.html#ad6f72f4fa4e7fde53ecde15fa5563433">setTruncStoreAction</a>(VT, InnerVT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00370"></a>00370 }
+<a name="l00371"></a>00371 <a class="code" href="classllvm_1_1TargetLowering.html#ae4ac865451dca0c871bed2f413a05aa2">setLoadExtAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00372"></a>00372 <a class="code" href="classllvm_1_1TargetLowering.html#ae4ac865451dca0c871bed2f413a05aa2">setLoadExtAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a8d89c7da4444d9ec11667aa369abc5f7">ISD::ZEXTLOAD</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00373"></a>00373 <a class="code" href="classllvm_1_1TargetLowering.html#ae4ac865451dca0c871bed2f413a05aa2">setLoadExtAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7afab3fffd153f7d7770fed81272e4b78f">ISD::EXTLOAD</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00374"></a>00374 }
+<a name="l00375"></a>00375
+<a name="l00376"></a>00376 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = (<span class="keywordtype">unsigned</span>)<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca8a48671a1ceb25c1025a152609497e15">MVT::FIRST_FP_VECTOR_VALUETYPE</a>;
+<a name="l00377"></a>00377 i <= (<a class="code" href="classunsigned.html">unsigned</a>)<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca29b59231428eb32804afb17abd744941">MVT::LAST_FP_VECTOR_VALUETYPE</a>; ++i) {
+<a name="l00378"></a>00378 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a> VT = (<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a>)i;
+<a name="l00379"></a>00379 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae1118ddac1ce0af8e9f7cc16c9e94fc0">ISD::FSQRT</a>, VT, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00380"></a>00380 }
+<a name="l00381"></a>00381
+<a name="l00382"></a>00382 <span class="comment">// We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle</span>
+<a name="l00383"></a>00383 <span class="comment">// with merges, splats, etc.</span>
+<a name="l00384"></a>00384 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8d8773b28111d8898663d4a0f6223d68">ISD::VECTOR_SHUFFLE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00385"></a>00385
+<a name="l00386"></a>00386 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00387"></a>00387 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00388"></a>00388 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00389"></a>00389 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00390"></a>00390 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00391"></a>00391 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a047178c3b2c6a5df40ae22a407b8aca9">ISD::STORE</a> , <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00392"></a>00392 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac3f8f8d8437c64b2e2e9f978e2707210">ISD::FP_TO_SINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00393"></a>00393 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a71640703ec096a8b07111e85cfff6987">ISD::FP_TO_UINT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00394"></a>00394 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a315004656a75a3c3a9d7294f105a8da2">ISD::SINT_TO_FP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00395"></a>00395 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a169032eecd015d4eeb869c457202a6c8">ISD::UINT_TO_FP</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00396"></a>00396
+<a name="l00397"></a>00397 <a class="code" href="classllvm_1_1TargetLowering.html#a3c9f9db4814d0797586e65bebb09559d">addRegisterClass</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, &PPC::VRRCRegClass);
+<a name="l00398"></a>00398 <a class="code" href="classllvm_1_1TargetLowering.html#a3c9f9db4814d0797586e65bebb09559d">addRegisterClass</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, &PPC::VRRCRegClass);
+<a name="l00399"></a>00399 <a class="code" href="classllvm_1_1TargetLowering.html#a3c9f9db4814d0797586e65bebb09559d">addRegisterClass</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>, &PPC::VRRCRegClass);
+<a name="l00400"></a>00400 <a class="code" href="classllvm_1_1TargetLowering.html#a3c9f9db4814d0797586e65bebb09559d">addRegisterClass</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, &PPC::VRRCRegClass);
+<a name="l00401"></a>00401
+<a name="l00402"></a>00402 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00403"></a>00403 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a293ca68b3b2ce80eef991de822822254">ISD::FMA</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00404"></a>00404 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00405"></a>00405 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00406"></a>00406 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00407"></a>00407
+<a name="l00408"></a>00408 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a576080a08ef1bbab0308eac9d5838f75">ISD::SCALAR_TO_VECTOR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00409"></a>00409 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a576080a08ef1bbab0308eac9d5838f75">ISD::SCALAR_TO_VECTOR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00410"></a>00410
+<a name="l00411"></a>00411 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00412"></a>00412 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00413"></a>00413 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00414"></a>00414 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba146bb5f7368109741fc8d4a8a85ad31e">Custom</a>);
+<a name="l00415"></a>00415
+<a name="l00416"></a>00416 <span class="comment">// Altivec does not contain unordered floating-point compare instructions</span>
+<a name="l00417"></a>00417 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a48a334bbe606d5e82c9cd84eaa127b50">ISD::SETUO</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00418"></a>00418 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0deb50cd2f3f8e4a94eef4cdf769b848">ISD::SETUEQ</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00419"></a>00419 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00420"></a>00420 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a9dff1dcbac65852b71473818c11869b1">ISD::SETUGE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00421"></a>00421 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00422"></a>00422 <a class="code" href="classllvm_1_1TargetLowering.html#a3c270244add3732b047298dbbd2886ae">setCondCodeAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac538f0b432df970cbaaf6b81d777c6a7">ISD::SETULE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00423"></a>00423 }
+<a name="l00424"></a>00424
+<a name="l00425"></a>00425 <span class="keywordflow">if</span> (Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#a011454ea07a73444b499f0b8bb35fa37">has64BitSupport</a>()) {
+<a name="l00426"></a>00426 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a691a4c9004e9bd04d1c0bebc5df57443">ISD::PREFETCH</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00427"></a>00427 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac43f9bea13e29622bbf18c861b52144d">ISD::READCYCLECOUNTER</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acba01fa4a725e243a37d72f1aafcabcafbe">Legal</a>);
+<a name="l00428"></a>00428 }
+<a name="l00429"></a>00429
+<a name="l00430"></a>00430 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7c47226f266248f4b8c155b83601b109">ISD::ATOMIC_LOAD</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00431"></a>00431 <a class="code" href="classllvm_1_1TargetLowering.html#aea1fb263848e2e8d2a2870ec5c5c342e">setOperationAction</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1db943abc1bf78a911daeb7b03d81de8">ISD::ATOMIC_STORE</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1TargetLowering.html#a105fb022b0fac6bc3639537811698acbad1779d45cfb616a92d1657b26ee75913">Expand</a>);
+<a name="l00432"></a>00432
+<a name="l00433"></a>00433 <a class="code" href="classllvm_1_1TargetLowering.html#ace3a60b4ba19680f75cedd49b026784f">setBooleanContents</a>(<a class="code" href="classllvm_1_1TargetLowering.html#a9782107892cd3e2d874265724648101baacf191b9517a18a33d74b417e2c6b56d">ZeroOrOneBooleanContent</a>);
+<a name="l00434"></a>00434 <a class="code" href="classllvm_1_1TargetLowering.html#ac60532e6e0bb8efc5146b3cc6882d979">setBooleanVectorContents</a>(<a class="code" href="classllvm_1_1TargetLowering.html#a9782107892cd3e2d874265724648101baacf191b9517a18a33d74b417e2c6b56d">ZeroOrOneBooleanContent</a>); <span class="comment">// FIXME: Is this correct?</span>
+<a name="l00435"></a>00435
+<a name="l00436"></a>00436 <span class="keywordflow">if</span> (isPPC64) {
+<a name="l00437"></a>00437 <a class="code" href="classllvm_1_1TargetLowering.html#a5ecea850fb8fa3cb8706b050f4d468cc">setStackPointerRegisterToSaveRestore</a>(PPC::X1);
+<a name="l00438"></a>00438 <a class="code" href="classllvm_1_1TargetLowering.html#a277c482f045f53738acb4e4c97298dd0">setExceptionPointerRegister</a>(PPC::X3);
+<a name="l00439"></a>00439 <a class="code" href="classllvm_1_1TargetLowering.html#a785fc5da4c24af5cacf1a0a2a452ce03">setExceptionSelectorRegister</a>(PPC::X4);
+<a name="l00440"></a>00440 } <span class="keywordflow">else</span> {
+<a name="l00441"></a>00441 <a class="code" href="classllvm_1_1TargetLowering.html#a5ecea850fb8fa3cb8706b050f4d468cc">setStackPointerRegisterToSaveRestore</a>(PPC::R1);
+<a name="l00442"></a>00442 <a class="code" href="classllvm_1_1TargetLowering.html#a277c482f045f53738acb4e4c97298dd0">setExceptionPointerRegister</a>(PPC::R3);
+<a name="l00443"></a>00443 <a class="code" href="classllvm_1_1TargetLowering.html#a785fc5da4c24af5cacf1a0a2a452ce03">setExceptionSelectorRegister</a>(PPC::R4);
+<a name="l00444"></a>00444 }
+<a name="l00445"></a>00445
+<a name="l00446"></a>00446 <span class="comment">// We have target-specific dag combine patterns for the following nodes:</span>
+<a name="l00447"></a>00447 <a class="code" href="classllvm_1_1TargetLowering.html#ab98b8190d282aec5843b5cc3e4ad34b3">setTargetDAGCombine</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a315004656a75a3c3a9d7294f105a8da2">ISD::SINT_TO_FP</a>);
+<a name="l00448"></a>00448 <a class="code" href="classllvm_1_1TargetLowering.html#ab98b8190d282aec5843b5cc3e4ad34b3">setTargetDAGCombine</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a047178c3b2c6a5df40ae22a407b8aca9">ISD::STORE</a>);
+<a name="l00449"></a>00449 <a class="code" href="classllvm_1_1TargetLowering.html#ab98b8190d282aec5843b5cc3e4ad34b3">setTargetDAGCombine</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6d5e322b263f0d5ea4204efafc1d78bb">ISD::BR_CC</a>);
+<a name="l00450"></a>00450 <a class="code" href="classllvm_1_1TargetLowering.html#ab98b8190d282aec5843b5cc3e4ad34b3">setTargetDAGCombine</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a19328c462764af5f4699fb1698dad994" title="Byte Swap and Counting operators.">ISD::BSWAP</a>);
+<a name="l00451"></a>00451
+<a name="l00452"></a>00452 <span class="comment">// Darwin long double math library functions have $LDBL128 appended.</span>
+<a name="l00453"></a>00453 <span class="keywordflow">if</span> (Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#abf861b7eababe28400eb7d5b3519f18f" title="isDarwin - True if this is any darwin platform.">isDarwin</a>()) {
+<a name="l00454"></a>00454 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447acd1ac5bde6e8130cdf274cd80150a6fe">RTLIB::COS_PPCF128</a>, <span class="stringliteral">"cosl$LDBL128"</span>);
+<a name="l00455"></a>00455 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447a27c3c049787afb74d9c7ebeed3119060">RTLIB::POW_PPCF128</a>, <span class="stringliteral">"powl$LDBL128"</span>);
+<a name="l00456"></a>00456 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447a33b67cea917a9560371f62c847c81d36">RTLIB::REM_PPCF128</a>, <span class="stringliteral">"fmodl$LDBL128"</span>);
+<a name="l00457"></a>00457 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447a1a9189900ae5c91cdf8f0c712fdce22f">RTLIB::SIN_PPCF128</a>, <span class="stringliteral">"sinl$LDBL128"</span>);
+<a name="l00458"></a>00458 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447a523c09ebf4484c38d3bb066447d26b8e">RTLIB::SQRT_PPCF128</a>, <span class="stringliteral">"sqrtl$LDBL128"</span>);
+<a name="l00459"></a>00459 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447a87c0a85f979b7e95a254b0972c051635">RTLIB::LOG_PPCF128</a>, <span class="stringliteral">"logl$LDBL128"</span>);
+<a name="l00460"></a>00460 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447ad7837284a4b9dcc4c8139a6468b49d80">RTLIB::LOG2_PPCF128</a>, <span class="stringliteral">"log2l$LDBL128"</span>);
+<a name="l00461"></a>00461 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447a5f72128817687b0322d639af385b8929">RTLIB::LOG10_PPCF128</a>, <span class="stringliteral">"log10l$LDBL128"</span>);
+<a name="l00462"></a>00462 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447a2cddfd7ba21b019af1a85476bc2f41a0">RTLIB::EXP_PPCF128</a>, <span class="stringliteral">"expl$LDBL128"</span>);
+<a name="l00463"></a>00463 <a class="code" href="classllvm_1_1TargetLowering.html#aadf2ca810fae75b7bc18e7e8cdaf1cc4">setLibcallName</a>(<a class="code" href="namespacellvm_1_1RTLIB.html#a50a0bab21f1d14a86a1483ec283e4447abaf4745416240994a8338fb833f5c435">RTLIB::EXP2_PPCF128</a>, <span class="stringliteral">"exp2l$LDBL128"</span>);
+<a name="l00464"></a>00464 }
+<a name="l00465"></a>00465
+<a name="l00466"></a>00466 <a class="code" href="classllvm_1_1TargetLowering.html#acfeb3f5b6cc498b5a45af1eff33efd28">setMinFunctionAlignment</a>(2);
+<a name="l00467"></a>00467 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abf861b7eababe28400eb7d5b3519f18f" title="isDarwin - True if this is any darwin platform.">isDarwin</a>())
+<a name="l00468"></a>00468 <a class="code" href="classllvm_1_1TargetLowering.html#a5d6c9df704431953e813d10d1f876582">setPrefFunctionAlignment</a>(4);
+<a name="l00469"></a>00469
+<a name="l00470"></a>00470 <span class="keywordflow">if</span> (isPPC64 && Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#a681a429eed034e724db0e5059726dad8">isJITCodeModel</a>())
+<a name="l00471"></a>00471 <span class="comment">// Temporary workaround for the inability of PPC64 JIT to handle jump</span>
+<a name="l00472"></a>00472 <span class="comment">// tables.</span>
+<a name="l00473"></a>00473 <a class="code" href="classllvm_1_1TargetLowering.html#ac8ec9799ada52afab34c45aae3e39aa7">setSupportJumpTables</a>(<span class="keyword">false</span>);
+<a name="l00474"></a>00474
+<a name="l00475"></a>00475 <a class="code" href="classllvm_1_1TargetLowering.html#a21458f530f80e24af196ded18eec516a">setInsertFencesForAtomic</a>(<span class="keyword">true</span>);
+<a name="l00476"></a>00476
+<a name="l00477"></a>00477 <a class="code" href="classllvm_1_1TargetLowering.html#a61ad598bb69883c95ce6fc020f0d5589" title="setSchedulingPreference - Specify the target scheduling preference.">setSchedulingPreference</a>(<a class="code" href="namespacellvm_1_1Sched.html#ac1547cccaf660851fcd6863d1e60309ea6530ebdb4e713581540e6ceb88897acb">Sched::Hybrid</a>);
+<a name="l00478"></a>00478
+<a name="l00479"></a>00479 <a class="code" href="classllvm_1_1TargetLowering.html#a8795a96bcc37445c668fc71427fb863d">computeRegisterProperties</a>();
+<a name="l00480"></a>00480
+<a name="l00481"></a>00481 <span class="comment">// The Freescale cores does better with aggressive inlining of memcpy and</span>
+<a name="l00482"></a>00482 <span class="comment">// friends. Gcc uses same threshold of 128 bytes (= 32 word stores).</span>
+<a name="l00483"></a>00483 <span class="keywordflow">if</span> (Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#acc246ab25df99943c39246a7485f6f83">getDarwinDirective</a>() == <a class="code" href="namespacellvm_1_1PPC.html#aaddfbe0455c4a5aae558ced038355cbca00d4f7d7f8d110db90749f417fceff3a">PPC::DIR_E500mc</a> ||
+<a name="l00484"></a>00484 Subtarget-><a class="code" href="classllvm_1_1PPCSubtarget.html#acc246ab25df99943c39246a7485f6f83">getDarwinDirective</a>() == <a class="code" href="namespacellvm_1_1PPC.html#aaddfbe0455c4a5aae558ced038355cbcac4e6bb06de05f2620850b3fc53a0433e">PPC::DIR_E5500</a>) {
+<a name="l00485"></a>00485 <a class="code" href="classllvm_1_1TargetLowering.html#a139edfad1584eb225bbf9521f0dc057b" title="Specify maximum number of store instructions per memset call.">maxStoresPerMemset</a> = 32;
+<a name="l00486"></a>00486 <a class="code" href="classllvm_1_1TargetLowering.html#a385d5497177eda624ac028f253612d99">maxStoresPerMemsetOptSize</a> = 16;
+<a name="l00487"></a>00487 <a class="code" href="classllvm_1_1TargetLowering.html#a5e34898f8bd846b470c9ffc21a2173cb" title="Specify maximum bytes of store instructions per memcpy call.">maxStoresPerMemcpy</a> = 32;
+<a name="l00488"></a>00488 <a class="code" href="classllvm_1_1TargetLowering.html#aac44fc2cb786b89170acc7cf9c7d44aa">maxStoresPerMemcpyOptSize</a> = 8;
+<a name="l00489"></a>00489 <a class="code" href="classllvm_1_1TargetLowering.html#abaef9267367cedf4f51382be135d0cba" title="Specify maximum bytes of store instructions per memmove call.">maxStoresPerMemmove</a> = 32;
+<a name="l00490"></a>00490 <a class="code" href="classllvm_1_1TargetLowering.html#a649bf41339d18489262636653c69ab86">maxStoresPerMemmoveOptSize</a> = 8;
+<a name="l00491"></a>00491
+<a name="l00492"></a>00492 <a class="code" href="classllvm_1_1TargetLowering.html#a5d6c9df704431953e813d10d1f876582">setPrefFunctionAlignment</a>(4);
+<a name="l00493"></a>00493 <a class="code" href="classllvm_1_1TargetLowering.html#addc004c3ccbbb53ff87a77277ec8f6a8">benefitFromCodePlacementOpt</a> = <span class="keyword">true</span>;
+<a name="l00494"></a>00494 }
+<a name="l00495"></a>00495 }
+<a name="l00496"></a>00496 <span class="comment"></span>
+<a name="l00497"></a>00497 <span class="comment">/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate</span>
+<a name="l00498"></a>00498 <span class="comment">/// function arguments in the caller parameter area.</span>
+<a name="l00499"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#aeda072b47ee5dccf983504e29ec5fe2e">00499</a> <span class="comment"></span><span class="keywordtype">unsigned</span> <a class="code" href="classllvm_1_1PPCTargetLowering.html#aeda072b47ee5dccf983504e29ec5fe2e">PPCTargetLowering::getByValTypeAlignment</a>(<a class="code" href="classllvm_1_1Type.html">Type</a> *Ty)<span class="keyword"> const </span>{
+<a name="l00500"></a>00500 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetMachine.html">TargetMachine</a> &TM = <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>();
+<a name="l00501"></a>00501 <span class="comment">// Darwin passes everything on 4 byte boundary.</span>
+<a name="l00502"></a>00502 <span class="keywordflow">if</span> (TM.<a class="code" href="classllvm_1_1TargetMachine.html#a5af2fed99951774b6a14d30ec6e73792">getSubtarget</a><<a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a>>().<a class="code" href="classllvm_1_1PPCSubtarget.html#abf861b7eababe28400eb7d5b3519f18f" title="isDarwin - True if this is any darwin platform.">isDarwin</a>())
+<a name="l00503"></a>00503 <span class="keywordflow">return</span> 4;
+<a name="l00504"></a>00504
+<a name="l00505"></a>00505 <span class="comment">// 16byte and wider vectors are passed on 16byte boundary.</span>
+<a name="l00506"></a>00506 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1VectorType.html">VectorType</a> *VTy = dyn_cast<VectorType>(Ty))
+<a name="l00507"></a>00507 <span class="keywordflow">if</span> (VTy->getBitWidth() >= 128)
+<a name="l00508"></a>00508 <span class="keywordflow">return</span> 16;
+<a name="l00509"></a>00509
+<a name="l00510"></a>00510 <span class="comment">// The rest is 8 on PPC64 and 4 on PPC32 boundary.</span>
+<a name="l00511"></a>00511 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>())
+<a name="l00512"></a>00512 <span class="keywordflow">return</span> 8;
+<a name="l00513"></a>00513
+<a name="l00514"></a>00514 <span class="keywordflow">return</span> 4;
+<a name="l00515"></a>00515 }
+<a name="l00516"></a>00516
+<a name="l00517"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#a2474ba98067cac511db469757356afc0">00517</a> <span class="keyword">const</span> <span class="keywordtype">char</span> *<a class="code" href="classllvm_1_1PPCTargetLowering.html#a2474ba98067cac511db469757356afc0">PPCTargetLowering::getTargetNodeName</a>(<span class="keywordtype">unsigned</span> Opcode)<span class="keyword"> const </span>{
+<a name="l00518"></a>00518 <span class="keywordflow">switch</span> (Opcode) {
+<a name="l00519"></a>00519 <span class="keywordflow">default</span>: <span class="keywordflow">return</span> 0;
+<a name="l00520"></a>00520 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aed93fe593cbca270b48f14bc00c5d73a">PPCISD::FSEL</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::FSEL"</span>;
+<a name="l00521"></a>00521 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a7d46bc38a9f3de58adde307de9c5e892">PPCISD::FCFID</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::FCFID"</span>;
+<a name="l00522"></a>00522 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2a79156c141fbb0faadd358c767b906b">PPCISD::FCTIDZ</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::FCTIDZ"</span>;
+<a name="l00523"></a>00523 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2a6e33357fd46c15294432ab65adecec">PPCISD::FCTIWZ</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::FCTIWZ"</span>;
+<a name="l00524"></a>00524 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aa71de12afd261e0b3f2e040ce1c10315">PPCISD::STFIWX</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::STFIWX"</span>;
+<a name="l00525"></a>00525 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a4641b97d96da9f08b2609132342ca65b">PPCISD::VMADDFP</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::VMADDFP"</span>;
+<a name="l00526"></a>00526 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2a34a5ed2588ccc989de4882384c296b">PPCISD::VNMSUBFP</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::VNMSUBFP"</span>;
+<a name="l00527"></a>00527 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abd37e9e242507f9bcda602075a67c9dd">PPCISD::VPERM</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::VPERM"</span>;
+<a name="l00528"></a>00528 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66afaa3b6d013f5589d52186fb31c1507de">PPCISD::Hi</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::Hi"</span>;
+<a name="l00529"></a>00529 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abcb9c462158b362a5edc6a1d754c9edb">PPCISD::Lo</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::Lo"</span>;
+<a name="l00530"></a>00530 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a5ac8e8dafc2dd10379a59ceff7b237d6">PPCISD::TOC_ENTRY</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::TOC_ENTRY"</span>;
+<a name="l00531"></a>00531 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66ab791c435016d75f72e1e95c54f3d42d9">PPCISD::TOC_RESTORE</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::TOC_RESTORE"</span>;
+<a name="l00532"></a>00532 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a35d9b393639fbc9a4e639ce81c704d17" title="Like a regular LOAD but additionally taking/producing a flag.">PPCISD::LOAD</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::LOAD"</span>;
+<a name="l00533"></a>00533 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a4a73d0b02b92ec58d7f38d00ad50f289">PPCISD::LOAD_TOC</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::LOAD_TOC"</span>;
+<a name="l00534"></a>00534 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a098fa0d2b0ca58b9d504edb6a164ee54">PPCISD::DYNALLOC</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::DYNALLOC"</span>;
+<a name="l00535"></a>00535 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">PPCISD::GlobalBaseReg</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::GlobalBaseReg"</span>;
+<a name="l00536"></a>00536 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1b0abca17bd696928f9399acfd3d1522">PPCISD::SRL</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::SRL"</span>;
+<a name="l00537"></a>00537 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aad0d80bf5cf5a07b271e4357ed436f62">PPCISD::SRA</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::SRA"</span>;
+<a name="l00538"></a>00538 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a56a6aa00c6f25ef2c1f51277099a78a4">PPCISD::SHL</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::SHL"</span>;
+<a name="l00539"></a>00539 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a73d5538a5e8e3868aa25756ec31a416f">PPCISD::EXTSW_32</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::EXTSW_32"</span>;
+<a name="l00540"></a>00540 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1ad5156dad8dfe65002aeb13e0da5c5e" title="STD_32 - This is the STD instruction for use with "32-bit" registers.">PPCISD::STD_32</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::STD_32"</span>;
+<a name="l00541"></a>00541 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66acf9dfc83dc60a6e978bde88a5f43c10c">PPCISD::CALL_SVR4</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::CALL_SVR4"</span>;
+<a name="l00542"></a>00542 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2835b483522c86e3f126ca118152d55d">PPCISD::CALL_NOP_SVR4</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::CALL_NOP_SVR4"</span>;
+<a name="l00543"></a>00543 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abedf5397c58d51756c7a87898df6065c">PPCISD::CALL_Darwin</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::CALL_Darwin"</span>;
+<a name="l00544"></a>00544 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a7d967753b98358faf4088a7bd8cec60b" title="NOP - Special NOP which follows 64-bit SVR4 calls.">PPCISD::NOP</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::NOP"</span>;
+<a name="l00545"></a>00545 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aa48a0d892596a0da3cf4a82c6ff5a91f">PPCISD::MTCTR</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::MTCTR"</span>;
+<a name="l00546"></a>00546 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aaf00be05177a18c604cdafebde41d4ce">PPCISD::BCTRL_Darwin</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::BCTRL_Darwin"</span>;
+<a name="l00547"></a>00547 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66ac9e5a043bcec002240b677d88e122f10">PPCISD::BCTRL_SVR4</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::BCTRL_SVR4"</span>;
+<a name="l00548"></a>00548 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aca057f3b5880594ff9a4ef1750a61924" title="Return with a flag operand, matched by 'blr'.">PPCISD::RET_FLAG</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::RET_FLAG"</span>;
+<a name="l00549"></a>00549 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1850fed22e97200319f85dd13fc7d798">PPCISD::MFCR</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::MFCR"</span>;
+<a name="l00550"></a>00550 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a43a3ad5a512466965973ac46c8239c60">PPCISD::VCMP</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::VCMP"</span>;
+<a name="l00551"></a>00551 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2739f8327120cab9e21846dee3a5366b">PPCISD::VCMPo</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::VCMPo"</span>;
+<a name="l00552"></a>00552 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a8032251e5c6dfb52579250ef6373d599">PPCISD::LBRX</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::LBRX"</span>;
+<a name="l00553"></a>00553 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66af2142b68a3cab0d2f680eecbb31c76e0">PPCISD::STBRX</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::STBRX"</span>;
+<a name="l00554"></a>00554 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a21a28a4fd508bbb42150bd0a22bfa6a6">PPCISD::LARX</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::LARX"</span>;
+<a name="l00555"></a>00555 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66ac7dcbb4c22c1613325814e5d3550cc59">PPCISD::STCX</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::STCX"</span>;
+<a name="l00556"></a>00556 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a0992940624286ed6bc85cd7163501613">PPCISD::COND_BRANCH</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::COND_BRANCH"</span>;
+<a name="l00557"></a>00557 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aab6a046c536c71121190fefd548d6b25">PPCISD::MFFS</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::MFFS"</span>;
+<a name="l00558"></a>00558 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a993035abda4f7c501e3ca88e8297e37d" title="OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.">PPCISD::MTFSB0</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::MTFSB0"</span>;
+<a name="l00559"></a>00559 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2c4c29545f861421669b2c8db4464d0a" title="OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.">PPCISD::MTFSB1</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::MTFSB1"</span>;
+<a name="l00560"></a>00560 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66ad2b0da006c4560646ac3eb561a8b73b2">PPCISD::FADDRTZ</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::FADDRTZ"</span>;
+<a name="l00561"></a>00561 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a29fbc2a15e633db7ade7b0ee2f137a1c" title="MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.">PPCISD::MTFSF</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::MTFSF"</span>;
+<a name="l00562"></a>00562 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aa4dc9f480c199614ca9475c7969ead06">PPCISD::TC_RETURN</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::TC_RETURN"</span>;
+<a name="l00563"></a>00563 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a7fa84f3807a868c9e48e0928e3ac7f81" title="ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls">PPCISD::CR6SET</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::CR6SET"</span>;
+<a name="l00564"></a>00564 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a0a616f27a6f2de704ab3ed849b50b181">PPCISD::CR6UNSET</a>: <span class="keywordflow">return</span> <span class="stringliteral">"PPCISD::CR6UNSET"</span>;
+<a name="l00565"></a>00565 }
+<a name="l00566"></a>00566 }
+<a name="l00567"></a>00567
+<a name="l00568"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#adb7aaff8d1cd55d1608e1aa9f995bf3a">00568</a> <a class="code" href="structllvm_1_1EVT.html">EVT</a> <a class="code" href="classllvm_1_1PPCTargetLowering.html#adb7aaff8d1cd55d1608e1aa9f995bf3a" title="getSetCCResultType - Return the ISD::SETCC ValueType">PPCTargetLowering::getSetCCResultType</a>(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT)<span class="keyword"> const </span>{
+<a name="l00569"></a>00569 <span class="keywordflow">if</span> (!VT.<a class="code" href="structllvm_1_1EVT.html#a73f7c824cad61a47c21bf6d652ae2fd7" title="isVector - Return true if this is a vector value type.">isVector</a>())
+<a name="l00570"></a>00570 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>;
+<a name="l00571"></a>00571 <span class="keywordflow">return</span> VT.<a class="code" href="structllvm_1_1EVT.html#a2eed75ff7477295264c8320af1630bbb">changeVectorElementTypeToInteger</a>();
+<a name="l00572"></a>00572 }
+<a name="l00573"></a>00573
+<a name="l00574"></a>00574 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00575"></a>00575 <span class="comment">// Node matching predicates, for use by the tblgen matching code.</span>
+<a name="l00576"></a>00576 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00577"></a>00577 <span class="comment"></span>
+<a name="l00578"></a>00578 <span class="comment">/// isFloatingPointZero - Return true if this is 0.0 or -0.0.</span>
+<a name="l00579"></a><a class="code" href="PPCISelLowering_8cpp.html#af4674b301fdc98e0a729a8d4690e45f2">00579</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#af4674b301fdc98e0a729a8d4690e45f2" title="isFloatingPointZero - Return true if this is 0.0 or -0.0.">isFloatingPointZero</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op) {
+<a name="l00580"></a>00580 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantFPSDNode.html">ConstantFPSDNode</a> *CFP = dyn_cast<ConstantFPSDNode>(Op))
+<a name="l00581"></a>00581 <span class="keywordflow">return</span> CFP->getValueAPF().isZero();
+<a name="l00582"></a>00582 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="namespacellvm_1_1ISD.html#a910795e8d77c1545da0683c0e1cb81ee">ISD::isEXTLoad</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()) || <a class="code" href="namespacellvm_1_1ISD.html#a15623094a1ed0cd7163dc786e44c87c9">ISD::isNON_EXTLoad</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>())) {
+<a name="l00583"></a>00583 <span class="comment">// Maybe this has already been legalized into the constant pool?</span>
+<a name="l00584"></a>00584 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantPoolSDNode.html">ConstantPoolSDNode</a> *CP = dyn_cast<ConstantPoolSDNode>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1)))
+<a name="l00585"></a>00585 <span class="keywordflow">if</span> (<span class="keyword">const</span> <a class="code" href="classllvm_1_1ConstantFP.html">ConstantFP</a> *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
+<a name="l00586"></a>00586 <span class="keywordflow">return</span> CFP->getValueAPF().isZero();
+<a name="l00587"></a>00587 }
+<a name="l00588"></a>00588 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00589"></a>00589 }
+<a name="l00590"></a>00590 <span class="comment"></span>
+<a name="l00591"></a>00591 <span class="comment">/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return</span>
+<a name="l00592"></a>00592 <span class="comment">/// true if Op is undef or if it matches the specified value.</span>
+<a name="l00593"></a><a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">00593</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(<span class="keywordtype">int</span> Op, <span class="keywordtype">int</span> Val) {
+<a name="l00594"></a>00594 <span class="keywordflow">return</span> Op < 0 || Op == Val;
+<a name="l00595"></a>00595 }
+<a name="l00596"></a>00596 <span class="comment"></span>
+<a name="l00597"></a>00597 <span class="comment">/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a</span>
+<a name="l00598"></a>00598 <span class="comment">/// VPKUHUM instruction.</span>
+<a name="l00599"></a><a class="code" href="namespacellvm_1_1PPC.html#a4546a80a0dc0cca8a263b80cc86122b0">00599</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="namespacellvm_1_1PPC.html#a4546a80a0dc0cca8a263b80cc86122b0">PPC::isVPKUHUMShuffleMask</a>(<a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *N, <span class="keywordtype">bool</span> isUnary) {
+<a name="l00600"></a>00600 <span class="keywordflow">if</span> (!isUnary) {
+<a name="l00601"></a>00601 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 16; ++i)
+<a name="l00602"></a>00602 <span class="keywordflow">if</span> (!<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i), i*2+1))
+<a name="l00603"></a>00603 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00604"></a>00604 } <span class="keywordflow">else</span> {
+<a name="l00605"></a>00605 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 8; ++i)
+<a name="l00606"></a>00606 <span class="keywordflow">if</span> (!<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i), i*2+1) ||
+<a name="l00607"></a>00607 !<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i+8), i*2+1))
+<a name="l00608"></a>00608 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00609"></a>00609 }
+<a name="l00610"></a>00610 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00611"></a>00611 }
+<a name="l00612"></a>00612 <span class="comment"></span>
+<a name="l00613"></a>00613 <span class="comment">/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a</span>
+<a name="l00614"></a>00614 <span class="comment">/// VPKUWUM instruction.</span>
+<a name="l00615"></a><a class="code" href="namespacellvm_1_1PPC.html#ac08dd0e631069166e1c864b2bfbc05fe">00615</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="namespacellvm_1_1PPC.html#ac08dd0e631069166e1c864b2bfbc05fe">PPC::isVPKUWUMShuffleMask</a>(<a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *N, <span class="keywordtype">bool</span> isUnary) {
+<a name="l00616"></a>00616 <span class="keywordflow">if</span> (!isUnary) {
+<a name="l00617"></a>00617 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 16; i += 2)
+<a name="l00618"></a>00618 <span class="keywordflow">if</span> (!<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i ), i*2+2) ||
+<a name="l00619"></a>00619 !<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i+1), i*2+3))
+<a name="l00620"></a>00620 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00621"></a>00621 } <span class="keywordflow">else</span> {
+<a name="l00622"></a>00622 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 8; i += 2)
+<a name="l00623"></a>00623 <span class="keywordflow">if</span> (!<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i ), i*2+2) ||
+<a name="l00624"></a>00624 !<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i+1), i*2+3) ||
+<a name="l00625"></a>00625 !<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i+8), i*2+2) ||
+<a name="l00626"></a>00626 !<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i+9), i*2+3))
+<a name="l00627"></a>00627 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00628"></a>00628 }
+<a name="l00629"></a>00629 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00630"></a>00630 }
+<a name="l00631"></a>00631 <span class="comment"></span>
+<a name="l00632"></a>00632 <span class="comment">/// isVMerge - Common function, used to match vmrg* shuffles.</span>
+<a name="l00633"></a>00633 <span class="comment">///</span>
+<a name="l00634"></a><a class="code" href="PPCISelLowering_8cpp.html#a941eb33c376cb0192d0d7e52e21c0c11">00634</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#a941eb33c376cb0192d0d7e52e21c0c11">isVMerge</a>(<a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *N, <span class="keywordtype">unsigned</span> UnitSize,
+<a name="l00635"></a>00635 <span class="keywordtype">unsigned</span> LHSStart, <span class="keywordtype">unsigned</span> RHSStart) {
+<a name="l00636"></a>00636 assert(N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a> &&
+<a name="l00637"></a>00637 <span class="stringliteral">"PPC only supports shuffles by bytes!"</span>);
+<a name="l00638"></a>00638 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
+<a name="l00639"></a>00639 <span class="stringliteral">"Unsupported merge size!"</span>);
+<a name="l00640"></a>00640
+<a name="l00641"></a>00641 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 8/UnitSize; ++i) <span class="comment">// Step over units</span>
+<a name="l00642"></a>00642 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j = 0; j != UnitSize; ++j) { <span class="comment">// Step over bytes within unit</span>
+<a name="l00643"></a>00643 <span class="keywordflow">if</span> (!<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i*UnitSize*2+j),
+<a name="l00644"></a>00644 LHSStart+j+i*UnitSize) ||
+<a name="l00645"></a>00645 !<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i*UnitSize*2+UnitSize+j),
+<a name="l00646"></a>00646 RHSStart+j+i*UnitSize))
+<a name="l00647"></a>00647 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00648"></a>00648 }
+<a name="l00649"></a>00649 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00650"></a>00650 }
+<a name="l00651"></a>00651 <span class="comment"></span>
+<a name="l00652"></a>00652 <span class="comment">/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for</span>
+<a name="l00653"></a>00653 <span class="comment">/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).</span>
+<a name="l00654"></a><a class="code" href="namespacellvm_1_1PPC.html#ac5d667b47894c7546da2e58080fe2144">00654</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="namespacellvm_1_1PPC.html#ac5d667b47894c7546da2e58080fe2144">PPC::isVMRGLShuffleMask</a>(<a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *N, <span class="keywordtype">unsigned</span> UnitSize,
+<a name="l00655"></a>00655 <span class="keywordtype">bool</span> isUnary) {
+<a name="l00656"></a>00656 <span class="keywordflow">if</span> (!isUnary)
+<a name="l00657"></a>00657 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a941eb33c376cb0192d0d7e52e21c0c11">isVMerge</a>(N, UnitSize, 8, 24);
+<a name="l00658"></a>00658 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a941eb33c376cb0192d0d7e52e21c0c11">isVMerge</a>(N, UnitSize, 8, 8);
+<a name="l00659"></a>00659 }
+<a name="l00660"></a>00660 <span class="comment"></span>
+<a name="l00661"></a>00661 <span class="comment">/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for</span>
+<a name="l00662"></a>00662 <span class="comment">/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).</span>
+<a name="l00663"></a><a class="code" href="namespacellvm_1_1PPC.html#a8ddfb467153e079ac0e9c4951b948887">00663</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="namespacellvm_1_1PPC.html#a8ddfb467153e079ac0e9c4951b948887">PPC::isVMRGHShuffleMask</a>(<a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *N, <span class="keywordtype">unsigned</span> UnitSize,
+<a name="l00664"></a>00664 <span class="keywordtype">bool</span> isUnary) {
+<a name="l00665"></a>00665 <span class="keywordflow">if</span> (!isUnary)
+<a name="l00666"></a>00666 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a941eb33c376cb0192d0d7e52e21c0c11">isVMerge</a>(N, UnitSize, 0, 16);
+<a name="l00667"></a>00667 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a941eb33c376cb0192d0d7e52e21c0c11">isVMerge</a>(N, UnitSize, 0, 0);
+<a name="l00668"></a>00668 }
+<a name="l00669"></a>00669
+<a name="l00670"></a>00670 <span class="comment"></span>
+<a name="l00671"></a>00671 <span class="comment">/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift</span>
+<a name="l00672"></a>00672 <span class="comment">/// amount, otherwise return -1.</span>
+<a name="l00673"></a><a class="code" href="namespacellvm_1_1PPC.html#a9fdffa1326c897a221fdba3dc82f0ec4">00673</a> <span class="comment"></span><span class="keywordtype">int</span> <a class="code" href="namespacellvm_1_1PPC.html#a9fdffa1326c897a221fdba3dc82f0ec4">PPC::isVSLDOIShuffleMask</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> isUnary) {
+<a name="l00674"></a>00674 assert(N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a> &&
+<a name="l00675"></a>00675 <span class="stringliteral">"PPC only supports shuffles by bytes!"</span>);
+<a name="l00676"></a>00676
+<a name="l00677"></a>00677 <a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *SVOp = cast<ShuffleVectorSDNode>(N);
+<a name="l00678"></a>00678
+<a name="l00679"></a>00679 <span class="comment">// Find the first non-undef value in the shuffle mask.</span>
+<a name="l00680"></a>00680 <span class="keywordtype">unsigned</span> i;
+<a name="l00681"></a>00681 <span class="keywordflow">for</span> (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
+<a name="l00682"></a>00682 <span class="comment">/*search*/</span>;
+<a name="l00683"></a>00683
+<a name="l00684"></a>00684 <span class="keywordflow">if</span> (i == 16) <span class="keywordflow">return</span> -1; <span class="comment">// all undef.</span>
+<a name="l00685"></a>00685
+<a name="l00686"></a>00686 <span class="comment">// Otherwise, check to see if the rest of the elements are consecutively</span>
+<a name="l00687"></a>00687 <span class="comment">// numbered from this value.</span>
+<a name="l00688"></a>00688 <span class="keywordtype">unsigned</span> ShiftAmt = SVOp-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i);
+<a name="l00689"></a>00689 <span class="keywordflow">if</span> (ShiftAmt < i) <span class="keywordflow">return</span> -1;
+<a name="l00690"></a>00690 ShiftAmt -= i;
+<a name="l00691"></a>00691
+<a name="l00692"></a>00692 <span class="keywordflow">if</span> (!isUnary) {
+<a name="l00693"></a>00693 <span class="comment">// Check the rest of the elements to see if they are consecutive.</span>
+<a name="l00694"></a>00694 <span class="keywordflow">for</span> (++i; i != 16; ++i)
+<a name="l00695"></a>00695 <span class="keywordflow">if</span> (!<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(SVOp->getMaskElt(i), ShiftAmt+i))
+<a name="l00696"></a>00696 <span class="keywordflow">return</span> -1;
+<a name="l00697"></a>00697 } <span class="keywordflow">else</span> {
+<a name="l00698"></a>00698 <span class="comment">// Check the rest of the elements to see if they are consecutive.</span>
+<a name="l00699"></a>00699 <span class="keywordflow">for</span> (++i; i != 16; ++i)
+<a name="l00700"></a>00700 <span class="keywordflow">if</span> (!<a class="code" href="PPCISelLowering_8cpp.html#a0aa657a6a85ab82917c254bc085416bd">isConstantOrUndef</a>(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
+<a name="l00701"></a>00701 <span class="keywordflow">return</span> -1;
+<a name="l00702"></a>00702 }
+<a name="l00703"></a>00703 <span class="keywordflow">return</span> ShiftAmt;
+<a name="l00704"></a>00704 }
+<a name="l00705"></a>00705 <span class="comment"></span>
+<a name="l00706"></a>00706 <span class="comment">/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand</span>
+<a name="l00707"></a>00707 <span class="comment">/// specifies a splat of a single element that is suitable for input to</span>
+<a name="l00708"></a>00708 <span class="comment">/// VSPLTB/VSPLTH/VSPLTW.</span>
+<a name="l00709"></a><a class="code" href="namespacellvm_1_1PPC.html#adf912033ee385662cb4e40bd06206b67">00709</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="namespacellvm_1_1PPC.html#adf912033ee385662cb4e40bd06206b67">PPC::isSplatShuffleMask</a>(<a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *N, <span class="keywordtype">unsigned</span> EltSize) {
+<a name="l00710"></a>00710 assert(N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a> &&
+<a name="l00711"></a>00711 (EltSize == 1 || EltSize == 2 || EltSize == 4));
+<a name="l00712"></a>00712
+<a name="l00713"></a>00713 <span class="comment">// This is a splat operation if each element of the permute is the same, and</span>
+<a name="l00714"></a>00714 <span class="comment">// if the value doesn't reference the second vector.</span>
+<a name="l00715"></a>00715 <span class="keywordtype">unsigned</span> ElementBase = N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(0);
+<a name="l00716"></a>00716
+<a name="l00717"></a>00717 <span class="comment">// FIXME: Handle UNDEF elements too!</span>
+<a name="l00718"></a>00718 <span class="keywordflow">if</span> (ElementBase >= 16)
+<a name="l00719"></a>00719 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00720"></a>00720
+<a name="l00721"></a>00721 <span class="comment">// Check that the indices are consecutive, in the case of a multi-byte element</span>
+<a name="l00722"></a>00722 <span class="comment">// splatted with a v16i8 mask.</span>
+<a name="l00723"></a>00723 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 1; i != EltSize; ++i)
+<a name="l00724"></a>00724 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i) < 0 || N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i) != (int)(i+ElementBase))
+<a name="l00725"></a>00725 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00726"></a>00726
+<a name="l00727"></a>00727 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = EltSize, e = 16; i != e; i += EltSize) {
+<a name="l00728"></a>00728 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i) < 0) <span class="keywordflow">continue</span>;
+<a name="l00729"></a>00729 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j = 0; j != EltSize; ++j)
+<a name="l00730"></a>00730 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(i+j) != N-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(j))
+<a name="l00731"></a>00731 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00732"></a>00732 }
+<a name="l00733"></a>00733 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00734"></a>00734 }
+<a name="l00735"></a>00735 <span class="comment"></span>
+<a name="l00736"></a>00736 <span class="comment">/// isAllNegativeZeroVector - Returns true if all elements of build_vector</span>
+<a name="l00737"></a>00737 <span class="comment">/// are -0.0.</span>
+<a name="l00738"></a><a class="code" href="namespacellvm_1_1PPC.html#a96b493b8aa609c1c5c83e21dde6bf3d0">00738</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="namespacellvm_1_1PPC.html#a96b493b8aa609c1c5c83e21dde6bf3d0">PPC::isAllNegativeZeroVector</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l00739"></a>00739 <a class="code" href="classllvm_1_1BuildVectorSDNode.html">BuildVectorSDNode</a> *BV = cast<BuildVectorSDNode>(N);
+<a name="l00740"></a>00740
+<a name="l00741"></a>00741 <a class="code" href="classllvm_1_1APInt.html" title="Class for arbitrary precision integers.">APInt</a> APVal, APUndef;
+<a name="l00742"></a>00742 <span class="keywordtype">unsigned</span> BitSize;
+<a name="l00743"></a>00743 <span class="keywordtype">bool</span> HasAnyUndefs;
+<a name="l00744"></a>00744
+<a name="l00745"></a>00745 <span class="keywordflow">if</span> (BV-><a class="code" href="classllvm_1_1BuildVectorSDNode.html#a0d1aedc8b57ec58e82db037ccb38c2a2">isConstantSplat</a>(APVal, APUndef, BitSize, HasAnyUndefs, 32, <span class="keyword">true</span>))
+<a name="l00746"></a>00746 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantFPSDNode.html">ConstantFPSDNode</a> *CFP = dyn_cast<ConstantFPSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0)))
+<a name="l00747"></a>00747 <span class="keywordflow">return</span> CFP->getValueAPF().isNegZero();
+<a name="l00748"></a>00748
+<a name="l00749"></a>00749 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00750"></a>00750 }
+<a name="l00751"></a>00751 <span class="comment"></span>
+<a name="l00752"></a>00752 <span class="comment">/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the</span>
+<a name="l00753"></a>00753 <span class="comment">/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.</span>
+<a name="l00754"></a><a class="code" href="namespacellvm_1_1PPC.html#a9e6acfbcf4b5bde3ce4f55352a82aa49">00754</a> <span class="comment"></span><span class="keywordtype">unsigned</span> <a class="code" href="namespacellvm_1_1PPC.html#a9e6acfbcf4b5bde3ce4f55352a82aa49">PPC::getVSPLTImmediate</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">unsigned</span> EltSize) {
+<a name="l00755"></a>00755 <a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *SVOp = cast<ShuffleVectorSDNode>(N);
+<a name="l00756"></a>00756 assert(<a class="code" href="namespacellvm_1_1PPC.html#adf912033ee385662cb4e40bd06206b67">isSplatShuffleMask</a>(SVOp, EltSize));
+<a name="l00757"></a>00757 <span class="keywordflow">return</span> SVOp-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#aae5468704c119f87dceb6728814b5502">getMaskElt</a>(0) / EltSize;
+<a name="l00758"></a>00758 }
+<a name="l00759"></a>00759 <span class="comment"></span>
+<a name="l00760"></a>00760 <span class="comment">/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed</span>
+<a name="l00761"></a>00761 <span class="comment">/// by using a vspltis[bhw] instruction of the specified element size, return</span>
+<a name="l00762"></a>00762 <span class="comment">/// the constant being splatted. The ByteSize field indicates the number of</span>
+<a name="l00763"></a>00763 <span class="comment">/// bytes of each element [124] -> [bhw].</span>
+<a name="l00764"></a><a class="code" href="namespacellvm_1_1PPC.html#a1a14301103c8d97e52ed0ca117ea6b65">00764</a> <span class="comment"></span><a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1PPC.html#a1a14301103c8d97e52ed0ca117ea6b65">PPC::get_VSPLTI_elt</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">unsigned</span> ByteSize, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG) {
+<a name="l00765"></a>00765 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OpVal(0, 0);
+<a name="l00766"></a>00766
+<a name="l00767"></a>00767 <span class="comment">// If ByteSize of the splat is bigger than the element size of the</span>
+<a name="l00768"></a>00768 <span class="comment">// build_vector, then we have a case where we are checking for a splat where</span>
+<a name="l00769"></a>00769 <span class="comment">// multiple elements of the buildvector are folded together into a single</span>
+<a name="l00770"></a>00770 <span class="comment">// logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).</span>
+<a name="l00771"></a>00771 <span class="keywordtype">unsigned</span> EltSize = 16/N-><a class="code" href="classllvm_1_1SDNode.html#abc5c2f1d47a517373030133c6a102106">getNumOperands</a>();
+<a name="l00772"></a>00772 <span class="keywordflow">if</span> (EltSize < ByteSize) {
+<a name="l00773"></a>00773 <span class="keywordtype">unsigned</span> Multiple = ByteSize/EltSize; <span class="comment">// Number of BV entries per spltval.</span>
+<a name="l00774"></a>00774 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> UniquedVals[4];
+<a name="l00775"></a>00775 assert(Multiple > 1 && Multiple <= 4 && <span class="stringliteral">"How can this happen?"</span>);
+<a name="l00776"></a>00776
+<a name="l00777"></a>00777 <span class="comment">// See if all of the elements in the buildvector agree across.</span>
+<a name="l00778"></a>00778 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = N-><a class="code" href="classllvm_1_1SDNode.html#abc5c2f1d47a517373030133c6a102106">getNumOperands</a>(); i != e; ++i) {
+<a name="l00779"></a>00779 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(i).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7c6d8f265e9e16e5debdb9a536b55d3d" title="UNDEF - An undefined node.">ISD::UNDEF</a>) <span class="keywordflow">continue</span>;
+<a name="l00780"></a>00780 <span class="comment">// If the element isn't a constant, bail fully out.</span>
+<a name="l00781"></a>00781 <span class="keywordflow">if</span> (!isa<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(i))) <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l00782"></a>00782
+<a name="l00783"></a>00783
+<a name="l00784"></a>00784 <span class="keywordflow">if</span> (UniquedVals[i&(Multiple-1)].getNode() == 0)
+<a name="l00785"></a>00785 UniquedVals[i&(Multiple-1)] = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(i);
+<a name="l00786"></a>00786 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (UniquedVals[i&(Multiple-1)] != N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(i))
+<a name="l00787"></a>00787 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(); <span class="comment">// no match.</span>
+<a name="l00788"></a>00788 }
+<a name="l00789"></a>00789
+<a name="l00790"></a>00790 <span class="comment">// Okay, if we reached this point, UniquedVals[0..Multiple-1] contains</span>
+<a name="l00791"></a>00791 <span class="comment">// either constant or undef values that are identical for each chunk. See</span>
+<a name="l00792"></a>00792 <span class="comment">// if these chunks can form into a larger vspltis*.</span>
+<a name="l00793"></a>00793
+<a name="l00794"></a>00794 <span class="comment">// Check to see if all of the leading entries are either 0 or -1. If</span>
+<a name="l00795"></a>00795 <span class="comment">// neither, then this won't fit into the immediate field.</span>
+<a name="l00796"></a>00796 <span class="keywordtype">bool</span> LeadingZero = <span class="keyword">true</span>;
+<a name="l00797"></a>00797 <span class="keywordtype">bool</span> LeadingOnes = <span class="keyword">true</span>;
+<a name="l00798"></a>00798 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != Multiple-1; ++i) {
+<a name="l00799"></a>00799 <span class="keywordflow">if</span> (UniquedVals[i].getNode() == 0) <span class="keywordflow">continue</span>; <span class="comment">// Must have been undefs.</span>
+<a name="l00800"></a>00800
+<a name="l00801"></a>00801 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
+<a name="l00802"></a>00802 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
+<a name="l00803"></a>00803 }
+<a name="l00804"></a>00804 <span class="comment">// Finally, check the least significant entry.</span>
+<a name="l00805"></a>00805 <span class="keywordflow">if</span> (LeadingZero) {
+<a name="l00806"></a>00806 <span class="keywordflow">if</span> (UniquedVals[Multiple-1].getNode() == 0)
+<a name="l00807"></a>00807 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>); <span class="comment">// 0,0,0,undef</span>
+<a name="l00808"></a>00808 <span class="keywordtype">int</span> Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
+<a name="l00809"></a>00809 <span class="keywordflow">if</span> (Val < 16)
+<a name="l00810"></a>00810 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(Val, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>); <span class="comment">// 0,0,0,4 -> vspltisw(4)</span>
+<a name="l00811"></a>00811 }
+<a name="l00812"></a>00812 <span class="keywordflow">if</span> (LeadingOnes) {
+<a name="l00813"></a>00813 <span class="keywordflow">if</span> (UniquedVals[Multiple-1].getNode() == 0)
+<a name="l00814"></a>00814 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(~0U, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>); <span class="comment">// -1,-1,-1,undef</span>
+<a name="l00815"></a>00815 <span class="keywordtype">int</span> Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
+<a name="l00816"></a>00816 <span class="keywordflow">if</span> (Val >= -16) <span class="comment">// -1,-1,-1,-2 -> vspltisw(-2)</span>
+<a name="l00817"></a>00817 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(Val, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00818"></a>00818 }
+<a name="l00819"></a>00819
+<a name="l00820"></a>00820 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l00821"></a>00821 }
+<a name="l00822"></a>00822
+<a name="l00823"></a>00823 <span class="comment">// Check to see if this buildvec has a single non-undef value in its elements.</span>
+<a name="l00824"></a>00824 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = N-><a class="code" href="classllvm_1_1SDNode.html#abc5c2f1d47a517373030133c6a102106">getNumOperands</a>(); i != e; ++i) {
+<a name="l00825"></a>00825 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(i).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7c6d8f265e9e16e5debdb9a536b55d3d" title="UNDEF - An undefined node.">ISD::UNDEF</a>) <span class="keywordflow">continue</span>;
+<a name="l00826"></a>00826 <span class="keywordflow">if</span> (OpVal.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>() == 0)
+<a name="l00827"></a>00827 OpVal = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(i);
+<a name="l00828"></a>00828 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (OpVal != N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(i))
+<a name="l00829"></a>00829 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l00830"></a>00830 }
+<a name="l00831"></a>00831
+<a name="l00832"></a>00832 <span class="keywordflow">if</span> (OpVal.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>() == 0) <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(); <span class="comment">// All UNDEF: use implicit def.</span>
+<a name="l00833"></a>00833
+<a name="l00834"></a>00834 <span class="keywordtype">unsigned</span> ValSizeInBytes = EltSize;
+<a name="l00835"></a>00835 uint64_t <a class="code" href="classllvm_1_1Value.html" title="LLVM Value Representation.">Value</a> = 0;
+<a name="l00836"></a>00836 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *CN = dyn_cast<ConstantSDNode>(OpVal)) {
+<a name="l00837"></a>00837 Value = CN->getZExtValue();
+<a name="l00838"></a>00838 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantFPSDNode.html">ConstantFPSDNode</a> *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
+<a name="l00839"></a>00839 assert(CN->getValueType(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a> && <span class="stringliteral">"Only one legal FP vector type!"</span>);
+<a name="l00840"></a>00840 Value = <a class="code" href="namespacellvm.html#a5537d2c18e3c7cf4e9b70986bb7c90db">FloatToBits</a>(CN->getValueAPF().convertToFloat());
+<a name="l00841"></a>00841 }
+<a name="l00842"></a>00842
+<a name="l00843"></a>00843 <span class="comment">// If the splat value is larger than the element value, then we can never do</span>
+<a name="l00844"></a>00844 <span class="comment">// this splat. The only case that we could fit the replicated bits into our</span>
+<a name="l00845"></a>00845 <span class="comment">// immediate field for would be zero, and we prefer to use vxor for it.</span>
+<a name="l00846"></a>00846 <span class="keywordflow">if</span> (ValSizeInBytes < ByteSize) <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l00847"></a>00847
+<a name="l00848"></a>00848 <span class="comment">// If the element value is larger than the splat value, cut it in half and</span>
+<a name="l00849"></a>00849 <span class="comment">// check to see if the two halves are equal. Continue doing this until we</span>
+<a name="l00850"></a>00850 <span class="comment">// get to ByteSize. This allows us to handle 0x01010101 as 0x01.</span>
+<a name="l00851"></a>00851 <span class="keywordflow">while</span> (ValSizeInBytes > ByteSize) {
+<a name="l00852"></a>00852 ValSizeInBytes >>= 1;
+<a name="l00853"></a>00853
+<a name="l00854"></a>00854 <span class="comment">// If the top half equals the bottom half, we're still ok.</span>
+<a name="l00855"></a>00855 <span class="keywordflow">if</span> (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
+<a name="l00856"></a>00856 (Value & ((1 << (8*ValSizeInBytes))-1)))
+<a name="l00857"></a>00857 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l00858"></a>00858 }
+<a name="l00859"></a>00859
+<a name="l00860"></a>00860 <span class="comment">// Properly sign extend the value.</span>
+<a name="l00861"></a>00861 <span class="keywordtype">int</span> MaskVal = <a class="code" href="namespacellvm.html#a79155cfcf20c6572900a4c43f127bf00">SignExtend32</a>(Value, ByteSize * 8);
+<a name="l00862"></a>00862
+<a name="l00863"></a>00863 <span class="comment">// If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.</span>
+<a name="l00864"></a>00864 <span class="keywordflow">if</span> (MaskVal == 0) <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l00865"></a>00865
+<a name="l00866"></a>00866 <span class="comment">// Finally, if this value fits in a 5 bit sext field, return it</span>
+<a name="l00867"></a>00867 <span class="keywordflow">if</span> (SignExtend32<5>(MaskVal) == MaskVal)
+<a name="l00868"></a>00868 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(MaskVal, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00869"></a>00869 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l00870"></a>00870 }
+<a name="l00871"></a>00871
+<a name="l00872"></a>00872 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00873"></a>00873 <span class="comment">// Addressing Mode Selection</span>
+<a name="l00874"></a>00874 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00875"></a>00875 <span class="comment"></span>
+<a name="l00876"></a>00876 <span class="comment">/// isIntS16Immediate - This method tests to see if the node is either a 32-bit</span>
+<a name="l00877"></a>00877 <span class="comment">/// or 64-bit immediate, and if the value can be accurately represented as a</span>
+<a name="l00878"></a>00878 <span class="comment">/// sign extension from a 16-bit value. If so, this returns true and the</span>
+<a name="l00879"></a>00879 <span class="comment">/// immediate.</span>
+<a name="l00880"></a><a class="code" href="PPCISelLowering_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">00880</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">short</span> &Imm) {
+<a name="l00881"></a>00881 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a>)
+<a name="l00882"></a>00882 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00883"></a>00883
+<a name="l00884"></a>00884 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00885"></a>00885 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>)
+<a name="l00886"></a>00886 <span class="keywordflow">return</span> Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00887"></a>00887 <span class="keywordflow">else</span>
+<a name="l00888"></a>00888 <span class="keywordflow">return</span> Imm == (<a class="code" href="classint64__t.html">int64_t</a>)cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00889"></a>00889 }
+<a name="l00890"></a><a class="code" href="PPCISelLowering_8cpp.html#a5a2abfa58ea2a3349750c7f4b4a11694">00890</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <span class="keywordtype">short</span> &Imm) {
+<a name="l00891"></a>00891 <span class="keywordflow">return</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm);
+<a name="l00892"></a>00892 }
+<a name="l00893"></a>00893
+<a name="l00894"></a>00894 <span class="comment"></span>
+<a name="l00895"></a>00895 <span class="comment">/// SelectAddressRegReg - Given the specified addressed, check to see if it</span>
+<a name="l00896"></a>00896 <span class="comment">/// can be represented as an indexed [r+r] operation. Returns false if it</span>
+<a name="l00897"></a>00897 <span class="comment">/// can be more efficiently represented with [r+imm].</span>
+<a name="l00898"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#a82ce354ab2e296919fb5052cb69191ff">00898</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1PPCTargetLowering.html#a82ce354ab2e296919fb5052cb69191ff">PPCTargetLowering::SelectAddressRegReg</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00899"></a>00899 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Index,
+<a name="l00900"></a>00900 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l00901"></a>00901 <span class="keywordtype">short</span> imm = 0;
+<a name="l00902"></a>00902 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9acfcf145f2788bf340ff3f3098bc54909">ISD::ADD</a>) {
+<a name="l00903"></a>00903 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), imm))
+<a name="l00904"></a>00904 <span class="keywordflow">return</span> <span class="keyword">false</span>; <span class="comment">// r+i</span>
+<a name="l00905"></a>00905 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ab68a439987d870da623ed899fa47344c" title="Low address component (lower 16)">PPCISD::Lo</a>)
+<a name="l00906"></a>00906 <span class="keywordflow">return</span> <span class="keyword">false</span>; <span class="comment">// r+i</span>
+<a name="l00907"></a>00907
+<a name="l00908"></a>00908 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00909"></a>00909 Index = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00910"></a>00910 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00911"></a>00911 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a96727447c0ad447987df1c6415aef074">ISD::OR</a>) {
+<a name="l00912"></a>00912 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), imm))
+<a name="l00913"></a>00913 <span class="keywordflow">return</span> <span class="keyword">false</span>; <span class="comment">// r+i can fold it if we can.</span>
+<a name="l00914"></a>00914
+<a name="l00915"></a>00915 <span class="comment">// If this is an or of disjoint bitfields, we can codegen this as an add</span>
+<a name="l00916"></a>00916 <span class="comment">// (for better address arithmetic) if the LHS and RHS of the OR are provably</span>
+<a name="l00917"></a>00917 <span class="comment">// disjoint.</span>
+<a name="l00918"></a>00918 <a class="code" href="classllvm_1_1APInt.html" title="Class for arbitrary precision integers.">APInt</a> LHSKnownZero, LHSKnownOne;
+<a name="l00919"></a>00919 <a class="code" href="classllvm_1_1APInt.html" title="Class for arbitrary precision integers.">APInt</a> RHSKnownZero, RHSKnownOne;
+<a name="l00920"></a>00920 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad06ca140783fd9f03eed498e8485fc3d">ComputeMaskedBits</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0),
+<a name="l00921"></a>00921 LHSKnownZero, LHSKnownOne);
+<a name="l00922"></a>00922
+<a name="l00923"></a>00923 <span class="keywordflow">if</span> (LHSKnownZero.<a class="code" href="classllvm_1_1APInt.html#ac8be1ee0c47d9e47e567fa353f987ed5" title="Boolean conversion function.">getBoolValue</a>()) {
+<a name="l00924"></a>00924 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad06ca140783fd9f03eed498e8485fc3d">ComputeMaskedBits</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1),
+<a name="l00925"></a>00925 RHSKnownZero, RHSKnownOne);
+<a name="l00926"></a>00926 <span class="comment">// If all of the bits are known zero on the LHS or RHS, the add won't</span>
+<a name="l00927"></a>00927 <span class="comment">// carry.</span>
+<a name="l00928"></a>00928 <span class="keywordflow">if</span> (~(LHSKnownZero | RHSKnownZero) == 0) {
+<a name="l00929"></a>00929 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00930"></a>00930 Index = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00931"></a>00931 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00932"></a>00932 }
+<a name="l00933"></a>00933 }
+<a name="l00934"></a>00934 }
+<a name="l00935"></a>00935
+<a name="l00936"></a>00936 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00937"></a>00937 }
+<a name="l00938"></a>00938 <span class="comment"></span>
+<a name="l00939"></a>00939 <span class="comment">/// Returns true if the address N can be represented by a base register plus</span>
+<a name="l00940"></a>00940 <span class="comment">/// a signed 16-bit displacement [r+imm], and if it is not better</span>
+<a name="l00941"></a>00941 <span class="comment">/// represented as reg+reg.</span>
+<a name="l00942"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#a0f7b9578535340e18edcb75bfae9d385">00942</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1PPCTargetLowering.html#a0f7b9578535340e18edcb75bfae9d385">PPCTargetLowering::SelectAddressRegImm</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Disp,
+<a name="l00943"></a>00943 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00944"></a>00944 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l00945"></a>00945 <span class="comment">// FIXME dl should come from parent load or store, not from address</span>
+<a name="l00946"></a>00946 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l00947"></a>00947 <span class="comment">// If this can be more profitably realized as r+r, fail.</span>
+<a name="l00948"></a>00948 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1PPCTargetLowering.html#a82ce354ab2e296919fb5052cb69191ff">SelectAddressRegReg</a>(N, Disp, Base, DAG))
+<a name="l00949"></a>00949 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00950"></a>00950
+<a name="l00951"></a>00951 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9acfcf145f2788bf340ff3f3098bc54909">ISD::ADD</a>) {
+<a name="l00952"></a>00952 <span class="keywordtype">short</span> imm = 0;
+<a name="l00953"></a>00953 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), imm)) {
+<a name="l00954"></a>00954 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>((<span class="keywordtype">int</span>)imm & 0xFFFF, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00955"></a>00955 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1FrameIndexSDNode.html">FrameIndexSDNode</a> *FI = dyn_cast<FrameIndexSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0))) {
+<a name="l00956"></a>00956 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6ececde40ed933c2dfb5af16cb002529">getTargetFrameIndex</a>(FI->getIndex(), N.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l00957"></a>00957 } <span class="keywordflow">else</span> {
+<a name="l00958"></a>00958 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00959"></a>00959 }
+<a name="l00960"></a>00960 <span class="keywordflow">return</span> <span class="keyword">true</span>; <span class="comment">// [r+i]</span>
+<a name="l00961"></a>00961 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ab68a439987d870da623ed899fa47344c" title="Low address component (lower 16)">PPCISD::Lo</a>) {
+<a name="l00962"></a>00962 <span class="comment">// Match LOAD (ADD (X, Lo(G))).</span>
+<a name="l00963"></a>00963 assert(!cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))->getZExtValue()
+<a name="l00964"></a>00964 && <span class="stringliteral">"Cannot handle constant offsets yet!"</span>);
+<a name="l00965"></a>00965 Disp = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0); <span class="comment">// The global address.</span>
+<a name="l00966"></a>00966 assert(Disp.getOpcode() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a> ||
+<a name="l00967"></a>00967 Disp.getOpcode() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110afc9ad7857b7faf49dcde3dcf434e22a6">ISD::TargetGlobalTLSAddress</a> ||
+<a name="l00968"></a>00968 Disp.getOpcode() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a038a7f124b4118456a27a739c03650bf">ISD::TargetConstantPool</a> ||
+<a name="l00969"></a>00969 Disp.getOpcode() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a603c0651ff8c3a929c5e1d8b9a8f14cb">ISD::TargetJumpTable</a>);
+<a name="l00970"></a>00970 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00971"></a>00971 <span class="keywordflow">return</span> <span class="keyword">true</span>; <span class="comment">// [&g+r]</span>
+<a name="l00972"></a>00972 }
+<a name="l00973"></a>00973 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a96727447c0ad447987df1c6415aef074">ISD::OR</a>) {
+<a name="l00974"></a>00974 <span class="keywordtype">short</span> imm = 0;
+<a name="l00975"></a>00975 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), imm)) {
+<a name="l00976"></a>00976 <span class="comment">// If this is an or of disjoint bitfields, we can codegen this as an add</span>
+<a name="l00977"></a>00977 <span class="comment">// (for better address arithmetic) if the LHS and RHS of the OR are</span>
+<a name="l00978"></a>00978 <span class="comment">// provably disjoint.</span>
+<a name="l00979"></a>00979 <a class="code" href="classllvm_1_1APInt.html" title="Class for arbitrary precision integers.">APInt</a> LHSKnownZero, LHSKnownOne;
+<a name="l00980"></a>00980 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad06ca140783fd9f03eed498e8485fc3d">ComputeMaskedBits</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), LHSKnownZero, LHSKnownOne);
+<a name="l00981"></a>00981
+<a name="l00982"></a>00982 <span class="keywordflow">if</span> ((LHSKnownZero.<a class="code" href="classllvm_1_1APInt.html#a7dc983ebf0eb2d255fa90a67063c72e2" title="Get zero extended value.">getZExtValue</a>()|~(uint64_t)imm) == ~0ULL) {
+<a name="l00983"></a>00983 <span class="comment">// If all of the bits are known zero on the LHS or RHS, the add won't</span>
+<a name="l00984"></a>00984 <span class="comment">// carry.</span>
+<a name="l00985"></a>00985 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00986"></a>00986 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>((<span class="keywordtype">int</span>)imm & 0xFFFF, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00987"></a>00987 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00988"></a>00988 }
+<a name="l00989"></a>00989 }
+<a name="l00990"></a>00990 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *CN = dyn_cast<ConstantSDNode>(N)) {
+<a name="l00991"></a>00991 <span class="comment">// Loading from a constant address.</span>
+<a name="l00992"></a>00992
+<a name="l00993"></a>00993 <span class="comment">// If this address fits entirely in a 16-bit sext immediate field, codegen</span>
+<a name="l00994"></a>00994 <span class="comment">// this as "d, 0"</span>
+<a name="l00995"></a>00995 <span class="keywordtype">short</span> Imm;
+<a name="l00996"></a>00996 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(CN, Imm)) {
+<a name="l00997"></a>00997 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(Imm, CN->getValueType(0));
+<a name="l00998"></a>00998 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>() ? PPC::X0 : PPC::R0,
+<a name="l00999"></a>00999 CN->getValueType(0));
+<a name="l01000"></a>01000 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01001"></a>01001 }
+<a name="l01002"></a>01002
+<a name="l01003"></a>01003 <span class="comment">// Handle 32-bit sext immediates with LIS + addr mode.</span>
+<a name="l01004"></a>01004 <span class="keywordflow">if</span> (CN->getValueType(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> ||
+<a name="l01005"></a>01005 (<a class="code" href="classint64__t.html">int64_t</a>)CN->getZExtValue() == (int)CN->getZExtValue()) {
+<a name="l01006"></a>01006 <span class="keywordtype">int</span> Addr = (int)CN->getZExtValue();
+<a name="l01007"></a>01007
+<a name="l01008"></a>01008 <span class="comment">// Otherwise, break this down into an LIS + disp.</span>
+<a name="l01009"></a>01009 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>((<span class="keywordtype">short</span>)Addr, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01010"></a>01010
+<a name="l01011"></a>01011 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>((Addr - (<span class="keywordtype">signed</span> <span class="keywordtype">short</span>)Addr) >> 16, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01012"></a>01012 <span class="keywordtype">unsigned</span> Opc = CN-><a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> ? PPC::LIS : PPC::LIS8;
+<a name="l01013"></a>01013 Base = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad70be180b80a5767ac863b95b932dd31">getMachineNode</a>(Opc, dl, CN->getValueType(0), Base), 0);
+<a name="l01014"></a>01014 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01015"></a>01015 }
+<a name="l01016"></a>01016 }
+<a name="l01017"></a>01017
+<a name="l01018"></a>01018 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(0, <a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>());
+<a name="l01019"></a>01019 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1FrameIndexSDNode.html">FrameIndexSDNode</a> *FI = dyn_cast<FrameIndexSDNode>(N))
+<a name="l01020"></a>01020 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6ececde40ed933c2dfb5af16cb002529">getTargetFrameIndex</a>(FI->getIndex(), N.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l01021"></a>01021 <span class="keywordflow">else</span>
+<a name="l01022"></a>01022 Base = N;
+<a name="l01023"></a>01023 <span class="keywordflow">return</span> <span class="keyword">true</span>; <span class="comment">// [r+0]</span>
+<a name="l01024"></a>01024 }
+<a name="l01025"></a>01025 <span class="comment"></span>
+<a name="l01026"></a>01026 <span class="comment">/// SelectAddressRegRegOnly - Given the specified addressed, force it to be</span>
+<a name="l01027"></a>01027 <span class="comment">/// represented as an indexed [r+r] operation.</span>
+<a name="l01028"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#aee1e7fbaa86db98a24b2971b90ec06bb">01028</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1PPCTargetLowering.html#aee1e7fbaa86db98a24b2971b90ec06bb">PPCTargetLowering::SelectAddressRegRegOnly</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01029"></a>01029 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Index,
+<a name="l01030"></a>01030 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01031"></a>01031 <span class="comment">// Check to see if we can easily represent this as an [r+r] address. This</span>
+<a name="l01032"></a>01032 <span class="comment">// will fail if it thinks that the address is more profitably represented as</span>
+<a name="l01033"></a>01033 <span class="comment">// reg+imm, e.g. where imm = 0.</span>
+<a name="l01034"></a>01034 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1PPCTargetLowering.html#a82ce354ab2e296919fb5052cb69191ff">SelectAddressRegReg</a>(N, Base, Index, DAG))
+<a name="l01035"></a>01035 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01036"></a>01036
+<a name="l01037"></a>01037 <span class="comment">// If the operand is an addition, always emit this as [r+r], since this is</span>
+<a name="l01038"></a>01038 <span class="comment">// better (for code size, and execution, as the memop does the add for free)</span>
+<a name="l01039"></a>01039 <span class="comment">// than emitting an explicit add.</span>
+<a name="l01040"></a>01040 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9acfcf145f2788bf340ff3f3098bc54909">ISD::ADD</a>) {
+<a name="l01041"></a>01041 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01042"></a>01042 Index = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l01043"></a>01043 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01044"></a>01044 }
+<a name="l01045"></a>01045
+<a name="l01046"></a>01046 <span class="comment">// Otherwise, do it the hard way, using R0 as the base register.</span>
+<a name="l01047"></a>01047 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>() ? PPC::X0 : PPC::R0,
+<a name="l01048"></a>01048 N.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l01049"></a>01049 Index = N;
+<a name="l01050"></a>01050 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01051"></a>01051 }
+<a name="l01052"></a>01052 <span class="comment"></span>
+<a name="l01053"></a>01053 <span class="comment">/// SelectAddressRegImmShift - Returns true if the address N can be</span>
+<a name="l01054"></a>01054 <span class="comment">/// represented by a base register plus a signed 14-bit displacement</span>
+<a name="l01055"></a>01055 <span class="comment">/// [r+imm*4]. Suitable for use by STD and friends.</span>
+<a name="l01056"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#a6b1a7cf9ef88ea41c501e2c9f30c61e7">01056</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1PPCTargetLowering.html#a6b1a7cf9ef88ea41c501e2c9f30c61e7">PPCTargetLowering::SelectAddressRegImmShift</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Disp,
+<a name="l01057"></a>01057 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01058"></a>01058 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01059"></a>01059 <span class="comment">// FIXME dl should come from the parent load or store, not the address</span>
+<a name="l01060"></a>01060 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l01061"></a>01061 <span class="comment">// If this can be more profitably realized as r+r, fail.</span>
+<a name="l01062"></a>01062 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1PPCTargetLowering.html#a82ce354ab2e296919fb5052cb69191ff">SelectAddressRegReg</a>(N, Disp, Base, DAG))
+<a name="l01063"></a>01063 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01064"></a>01064
+<a name="l01065"></a>01065 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9acfcf145f2788bf340ff3f3098bc54909">ISD::ADD</a>) {
+<a name="l01066"></a>01066 <span class="keywordtype">short</span> imm = 0;
+<a name="l01067"></a>01067 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), imm) && (imm & 3) == 0) {
+<a name="l01068"></a>01068 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(((<span class="keywordtype">int</span>)imm & 0xFFFF) >> 2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01069"></a>01069 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1FrameIndexSDNode.html">FrameIndexSDNode</a> *FI = dyn_cast<FrameIndexSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0))) {
+<a name="l01070"></a>01070 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6ececde40ed933c2dfb5af16cb002529">getTargetFrameIndex</a>(FI->getIndex(), N.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l01071"></a>01071 } <span class="keywordflow">else</span> {
+<a name="l01072"></a>01072 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01073"></a>01073 }
+<a name="l01074"></a>01074 <span class="keywordflow">return</span> <span class="keyword">true</span>; <span class="comment">// [r+i]</span>
+<a name="l01075"></a>01075 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ab68a439987d870da623ed899fa47344c" title="Low address component (lower 16)">PPCISD::Lo</a>) {
+<a name="l01076"></a>01076 <span class="comment">// Match LOAD (ADD (X, Lo(G))).</span>
+<a name="l01077"></a>01077 assert(!cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))->getZExtValue()
+<a name="l01078"></a>01078 && <span class="stringliteral">"Cannot handle constant offsets yet!"</span>);
+<a name="l01079"></a>01079 Disp = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0); <span class="comment">// The global address.</span>
+<a name="l01080"></a>01080 assert(Disp.getOpcode() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a> ||
+<a name="l01081"></a>01081 Disp.getOpcode() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a038a7f124b4118456a27a739c03650bf">ISD::TargetConstantPool</a> ||
+<a name="l01082"></a>01082 Disp.getOpcode() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a603c0651ff8c3a929c5e1d8b9a8f14cb">ISD::TargetJumpTable</a>);
+<a name="l01083"></a>01083 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01084"></a>01084 <span class="keywordflow">return</span> <span class="keyword">true</span>; <span class="comment">// [&g+r]</span>
+<a name="l01085"></a>01085 }
+<a name="l01086"></a>01086 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a96727447c0ad447987df1c6415aef074">ISD::OR</a>) {
+<a name="l01087"></a>01087 <span class="keywordtype">short</span> imm = 0;
+<a name="l01088"></a>01088 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), imm) && (imm & 3) == 0) {
+<a name="l01089"></a>01089 <span class="comment">// If this is an or of disjoint bitfields, we can codegen this as an add</span>
+<a name="l01090"></a>01090 <span class="comment">// (for better address arithmetic) if the LHS and RHS of the OR are</span>
+<a name="l01091"></a>01091 <span class="comment">// provably disjoint.</span>
+<a name="l01092"></a>01092 <a class="code" href="classllvm_1_1APInt.html" title="Class for arbitrary precision integers.">APInt</a> LHSKnownZero, LHSKnownOne;
+<a name="l01093"></a>01093 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad06ca140783fd9f03eed498e8485fc3d">ComputeMaskedBits</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), LHSKnownZero, LHSKnownOne);
+<a name="l01094"></a>01094 <span class="keywordflow">if</span> ((LHSKnownZero.<a class="code" href="classllvm_1_1APInt.html#a7dc983ebf0eb2d255fa90a67063c72e2" title="Get zero extended value.">getZExtValue</a>()|~(uint64_t)imm) == ~0ULL) {
+<a name="l01095"></a>01095 <span class="comment">// If all of the bits are known zero on the LHS or RHS, the add won't</span>
+<a name="l01096"></a>01096 <span class="comment">// carry.</span>
+<a name="l01097"></a>01097 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01098"></a>01098 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(((<span class="keywordtype">int</span>)imm & 0xFFFF) >> 2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01099"></a>01099 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01100"></a>01100 }
+<a name="l01101"></a>01101 }
+<a name="l01102"></a>01102 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *CN = dyn_cast<ConstantSDNode>(N)) {
+<a name="l01103"></a>01103 <span class="comment">// Loading from a constant address. Verify low two bits are clear.</span>
+<a name="l01104"></a>01104 <span class="keywordflow">if</span> ((CN->getZExtValue() & 3) == 0) {
+<a name="l01105"></a>01105 <span class="comment">// If this address fits entirely in a 14-bit sext immediate field, codegen</span>
+<a name="l01106"></a>01106 <span class="comment">// this as "d, 0"</span>
+<a name="l01107"></a>01107 <span class="keywordtype">short</span> Imm;
+<a name="l01108"></a>01108 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(CN, Imm)) {
+<a name="l01109"></a>01109 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>((<span class="keywordtype">unsigned</span> <span class="keywordtype">short</span>)Imm >> 2, <a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>());
+<a name="l01110"></a>01110 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>() ? PPC::X0 : PPC::R0,
+<a name="l01111"></a>01111 CN->getValueType(0));
+<a name="l01112"></a>01112 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01113"></a>01113 }
+<a name="l01114"></a>01114
+<a name="l01115"></a>01115 <span class="comment">// Fold the low-part of 32-bit absolute addresses into addr mode.</span>
+<a name="l01116"></a>01116 <span class="keywordflow">if</span> (CN->getValueType(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> ||
+<a name="l01117"></a>01117 (<a class="code" href="classint64__t.html">int64_t</a>)CN->getZExtValue() == (int)CN->getZExtValue()) {
+<a name="l01118"></a>01118 <span class="keywordtype">int</span> Addr = (int)CN->getZExtValue();
+<a name="l01119"></a>01119
+<a name="l01120"></a>01120 <span class="comment">// Otherwise, break this down into an LIS + disp.</span>
+<a name="l01121"></a>01121 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>((<span class="keywordtype">short</span>)Addr >> 2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01122"></a>01122 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>((Addr-(<span class="keywordtype">signed</span> <span class="keywordtype">short</span>)Addr) >> 16, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01123"></a>01123 <span class="keywordtype">unsigned</span> Opc = CN-><a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> ? PPC::LIS : PPC::LIS8;
+<a name="l01124"></a>01124 Base = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad70be180b80a5767ac863b95b932dd31">getMachineNode</a>(Opc, dl, CN->getValueType(0), Base),0);
+<a name="l01125"></a>01125 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01126"></a>01126 }
+<a name="l01127"></a>01127 }
+<a name="l01128"></a>01128 }
+<a name="l01129"></a>01129
+<a name="l01130"></a>01130 Disp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>(0, <a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>());
+<a name="l01131"></a>01131 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1FrameIndexSDNode.html">FrameIndexSDNode</a> *FI = dyn_cast<FrameIndexSDNode>(N))
+<a name="l01132"></a>01132 Base = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6ececde40ed933c2dfb5af16cb002529">getTargetFrameIndex</a>(FI->getIndex(), N.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l01133"></a>01133 <span class="keywordflow">else</span>
+<a name="l01134"></a>01134 Base = N;
+<a name="l01135"></a>01135 <span class="keywordflow">return</span> <span class="keyword">true</span>; <span class="comment">// [r+0]</span>
+<a name="l01136"></a>01136 }
+<a name="l01137"></a>01137
+<a name="l01138"></a>01138 <span class="comment"></span>
+<a name="l01139"></a>01139 <span class="comment">/// getPreIndexedAddressParts - returns true by value, base pointer and</span>
+<a name="l01140"></a>01140 <span class="comment">/// offset pointer and addressing mode by reference if the node's address</span>
+<a name="l01141"></a>01141 <span class="comment">/// can be legally represented as pre-indexed load / store address.</span>
+<a name="l01142"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#ad29bfd78dd46028de88d10314613fcbd">01142</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1PPCTargetLowering.html#ad29bfd78dd46028de88d10314613fcbd">PPCTargetLowering::getPreIndexedAddressParts</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01143"></a>01143 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset,
+<a name="l01144"></a>01144 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> &AM,
+<a name="l01145"></a>01145 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01146"></a>01146 <span class="keywordflow">if</span> (<a class="code" href="PPCISelLowering_8cpp.html#a39032b11b8339a15cd3c828db23000fb">DisablePPCPreinc</a>) <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01147"></a>01147
+<a name="l01148"></a>01148 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ptr;
+<a name="l01149"></a>01149 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT;
+<a name="l01150"></a>01150 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1LoadSDNode.html">LoadSDNode</a> *LD = dyn_cast<LoadSDNode>(N)) {
+<a name="l01151"></a>01151 Ptr = LD->getBasePtr();
+<a name="l01152"></a>01152 VT = LD->getMemoryVT();
+<a name="l01153"></a>01153
+<a name="l01154"></a>01154 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1StoreSDNode.html">StoreSDNode</a> *<a class="code" href="namespacellvm_1_1ARM__MB.html#ad70272e2a9ec2a7e3a497458e1edbc85aed0b9bef861c96eee19e89db753db7b2">ST</a> = dyn_cast<StoreSDNode>(N)) {
+<a name="l01155"></a>01155 Ptr = <a class="code" href="namespacellvm_1_1ARM__MB.html#ad70272e2a9ec2a7e3a497458e1edbc85aed0b9bef861c96eee19e89db753db7b2">ST</a>->getBasePtr();
+<a name="l01156"></a>01156 VT = <a class="code" href="namespacellvm_1_1ARM__MB.html#ad70272e2a9ec2a7e3a497458e1edbc85aed0b9bef861c96eee19e89db753db7b2">ST</a>->getMemoryVT();
+<a name="l01157"></a>01157 } <span class="keywordflow">else</span>
+<a name="l01158"></a>01158 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01159"></a>01159
+<a name="l01160"></a>01160 <span class="comment">// PowerPC doesn't have preinc load/store instructions for vectors.</span>
+<a name="l01161"></a>01161 <span class="keywordflow">if</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a73f7c824cad61a47c21bf6d652ae2fd7" title="isVector - Return true if this is a vector value type.">isVector</a>())
+<a name="l01162"></a>01162 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01163"></a>01163
+<a name="l01164"></a>01164 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1PPCTargetLowering.html#a82ce354ab2e296919fb5052cb69191ff">SelectAddressRegReg</a>(Ptr, Offset, Base, DAG)) {
+<a name="l01165"></a>01165 AM = <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>;
+<a name="l01166"></a>01166 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01167"></a>01167 }
+<a name="l01168"></a>01168
+<a name="l01169"></a>01169 <span class="comment">// LDU/STU use reg+imm*4, others use reg+imm.</span>
+<a name="l01170"></a>01170 <span class="keywordflow">if</span> (VT != <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>) {
+<a name="l01171"></a>01171 <span class="comment">// reg + imm</span>
+<a name="l01172"></a>01172 <span class="keywordflow">if</span> (!<a class="code" href="classllvm_1_1PPCTargetLowering.html#a0f7b9578535340e18edcb75bfae9d385">SelectAddressRegImm</a>(Ptr, Offset, Base, DAG))
+<a name="l01173"></a>01173 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01174"></a>01174 } <span class="keywordflow">else</span> {
+<a name="l01175"></a>01175 <span class="comment">// reg + imm * 4.</span>
+<a name="l01176"></a>01176 <span class="keywordflow">if</span> (!<a class="code" href="classllvm_1_1PPCTargetLowering.html#a6b1a7cf9ef88ea41c501e2c9f30c61e7">SelectAddressRegImmShift</a>(Ptr, Offset, Base, DAG))
+<a name="l01177"></a>01177 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01178"></a>01178 }
+<a name="l01179"></a>01179
+<a name="l01180"></a>01180 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1LoadSDNode.html">LoadSDNode</a> *LD = dyn_cast<LoadSDNode>(N)) {
+<a name="l01181"></a>01181 <span class="comment">// PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of</span>
+<a name="l01182"></a>01182 <span class="comment">// sext i32 to i64 when addr mode is r+i.</span>
+<a name="l01183"></a>01183 <span class="keywordflow">if</span> (LD->getValueType(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> && LD->getMemoryVT() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> &&
+<a name="l01184"></a>01184 LD->getExtensionType() == <a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a> &&
+<a name="l01185"></a>01185 isa<ConstantSDNode>(Offset))
+<a name="l01186"></a>01186 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01187"></a>01187 }
+<a name="l01188"></a>01188
+<a name="l01189"></a>01189 AM = <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>;
+<a name="l01190"></a>01190 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01191"></a>01191 }
+<a name="l01192"></a>01192
+<a name="l01193"></a>01193 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l01194"></a>01194 <span class="comment">// LowerOperation implementation</span>
+<a name="l01195"></a>01195 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l01196"></a>01196 <span class="comment"></span>
+<a name="l01197"></a>01197 <span class="comment">/// GetLabelAccessInfo - Return true if we should reference labels using a</span>
+<a name="l01198"></a>01198 <span class="comment">/// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.</span>
+<a name="l01199"></a><a class="code" href="PPCISelLowering_8cpp.html#adeb13b67584232ee5ddade3d82a0b23a">01199</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#adeb13b67584232ee5ddade3d82a0b23a">GetLabelAccessInfo</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetMachine.html">TargetMachine</a> &TM, <span class="keywordtype">unsigned</span> &HiOpFlags,
+<a name="l01200"></a>01200 <span class="keywordtype">unsigned</span> &LoOpFlags, <span class="keyword">const</span> <a class="code" href="classllvm_1_1GlobalValue.html">GlobalValue</a> *GV = 0) {
+<a name="l01201"></a>01201 HiOpFlags = <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffa56fe0d0f0a5d799a256ad5ddc099af32">PPCII::MO_HA16</a>;
+<a name="l01202"></a>01202 LoOpFlags = <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffae87828d085fb01bff7d541bc38e7021f" title="MO_LO16, MO_HA16 - lo16(symbol) and ha16(symbol)">PPCII::MO_LO16</a>;
+<a name="l01203"></a>01203
+<a name="l01204"></a>01204 <span class="comment">// Don't use the pic base if not in PIC relocation model. Or if we are on a</span>
+<a name="l01205"></a>01205 <span class="comment">// non-darwin platform. We don't support PIC on other platforms yet.</span>
+<a name="l01206"></a>01206 <span class="keywordtype">bool</span> isPIC = TM.<a class="code" href="classllvm_1_1TargetMachine.html#a87f1815c4b56735aaadbbcdfdf32cf4f">getRelocationModel</a>() == <a class="code" href="namespacellvm_1_1Reloc.html#af59f6dc86e80aaf56f1afd155eebf568adc2075e13a68142b26e05ac08bbfc320">Reloc::PIC_</a> &&
+<a name="l01207"></a>01207 TM.<a class="code" href="classllvm_1_1TargetMachine.html#a5af2fed99951774b6a14d30ec6e73792">getSubtarget</a><<a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a>>().isDarwin();
+<a name="l01208"></a>01208 <span class="keywordflow">if</span> (isPIC) {
+<a name="l01209"></a>01209 HiOpFlags |= <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffaf464d229c08e6d5eb945d7b905a7c9fd">PPCII::MO_PIC_FLAG</a>;
+<a name="l01210"></a>01210 LoOpFlags |= <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffaf464d229c08e6d5eb945d7b905a7c9fd">PPCII::MO_PIC_FLAG</a>;
+<a name="l01211"></a>01211 }
+<a name="l01212"></a>01212
+<a name="l01213"></a>01213 <span class="comment">// If this is a reference to a global value that requires a non-lazy-ptr, make</span>
+<a name="l01214"></a>01214 <span class="comment">// sure that instruction lowering adds it.</span>
+<a name="l01215"></a>01215 <span class="keywordflow">if</span> (GV && TM.<a class="code" href="classllvm_1_1TargetMachine.html#a5af2fed99951774b6a14d30ec6e73792">getSubtarget</a><<a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a>>().<a class="code" href="classllvm_1_1PPCSubtarget.html#a94b8b75b7e75b19670b209830d2befab">hasLazyResolverStub</a>(GV, TM)) {
+<a name="l01216"></a>01216 HiOpFlags |= <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffa4c9eaf71e784335fbfdd96354cf46235">PPCII::MO_NLP_FLAG</a>;
+<a name="l01217"></a>01217 LoOpFlags |= <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffa4c9eaf71e784335fbfdd96354cf46235">PPCII::MO_NLP_FLAG</a>;
+<a name="l01218"></a>01218
+<a name="l01219"></a>01219 <span class="keywordflow">if</span> (GV->hasHiddenVisibility()) {
+<a name="l01220"></a>01220 HiOpFlags |= <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffa6ce0aaff74c60178c0210f31002c7f59">PPCII::MO_NLP_HIDDEN_FLAG</a>;
+<a name="l01221"></a>01221 LoOpFlags |= <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffa6ce0aaff74c60178c0210f31002c7f59">PPCII::MO_NLP_HIDDEN_FLAG</a>;
+<a name="l01222"></a>01222 }
+<a name="l01223"></a>01223 }
+<a name="l01224"></a>01224
+<a name="l01225"></a>01225 <span class="keywordflow">return</span> isPIC;
+<a name="l01226"></a>01226 }
+<a name="l01227"></a>01227
+<a name="l01228"></a><a class="code" href="PPCISelLowering_8cpp.html#ab5d4759731e493988eda569efb67233f">01228</a> <span class="keyword">static</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="PPCISelLowering_8cpp.html#ab5d4759731e493988eda569efb67233f">LowerLabelRef</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> HiPart, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LoPart, <span class="keywordtype">bool</span> isPIC,
+<a name="l01229"></a>01229 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG) {
+<a name="l01230"></a>01230 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = HiPart.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01231"></a>01231 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Zero = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(0, PtrVT);
+<a name="l01232"></a>01232 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> DL = HiPart.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l01233"></a>01233
+<a name="l01234"></a>01234 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ae3a56d8e7b43b7a68cbb0e7655a062cd" title="High address component (upper 16)">Hi</a> = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66afaa3b6d013f5589d52186fb31c1507de">PPCISD::Hi</a>, DL, PtrVT, HiPart, Zero);
+<a name="l01235"></a>01235 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ab68a439987d870da623ed899fa47344c" title="Low address component (lower 16)">Lo</a> = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abcb9c462158b362a5edc6a1d754c9edb">PPCISD::Lo</a>, DL, PtrVT, LoPart, Zero);
+<a name="l01236"></a>01236
+<a name="l01237"></a>01237 <span class="comment">// With PIC, the first instruction is actually "GR+hi(&G)".</span>
+<a name="l01238"></a>01238 <span class="keywordflow">if</span> (isPIC)
+<a name="l01239"></a>01239 Hi = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, DL, PtrVT,
+<a name="l01240"></a>01240 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">PPCISD::GlobalBaseReg</a>, DL, PtrVT), <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ae3a56d8e7b43b7a68cbb0e7655a062cd" title="High address component (upper 16)">Hi</a>);
+<a name="l01241"></a>01241
+<a name="l01242"></a>01242 <span class="comment">// Generate non-pic code that has direct accesses to the constant pool.</span>
+<a name="l01243"></a>01243 <span class="comment">// The address of the global is just (hi(&g)+lo(&g)).</span>
+<a name="l01244"></a>01244 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, DL, PtrVT, Hi, Lo);
+<a name="l01245"></a>01245 }
+<a name="l01246"></a>01246
+<a name="l01247"></a>01247 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerConstantPool(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l01248"></a>01248 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01249"></a>01249 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01250"></a>01250 <a class="code" href="classllvm_1_1ConstantPoolSDNode.html">ConstantPoolSDNode</a> *CP = cast<ConstantPoolSDNode>(Op);
+<a name="l01251"></a>01251 <span class="keyword">const</span> <a class="code" href="classllvm_1_1Constant.html" title="LLVM Constant Representation.">Constant</a> *<a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">C</a> = CP-><a class="code" href="classllvm_1_1ConstantPoolSDNode.html#aab74b88c9e364929ff1dd529ed24904b">getConstVal</a>();
+<a name="l01252"></a>01252
+<a name="l01253"></a>01253 <span class="comment">// 64-bit SVR4 ABI code is always position-independent.</span>
+<a name="l01254"></a>01254 <span class="comment">// The actual address of the GlobalValue is stored in the TOC.</span>
+<a name="l01255"></a>01255 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>() && PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>()) {
+<a name="l01256"></a>01256 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GA = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4a5973fcd1193bfff9158d5a83aebd1b">getTargetConstantPool</a>(C, PtrVT, CP-><a class="code" href="classllvm_1_1ConstantPoolSDNode.html#a130b74d7047dd920dfaea193ac8b0a3d">getAlignment</a>(), 0);
+<a name="l01257"></a>01257 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a5ac8e8dafc2dd10379a59ceff7b237d6">PPCISD::TOC_ENTRY</a>, CP-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>(), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, GA,
+<a name="l01258"></a>01258 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::X2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>));
+<a name="l01259"></a>01259 }
+<a name="l01260"></a>01260
+<a name="l01261"></a>01261 <span class="keywordtype">unsigned</span> MOHiFlag, MOLoFlag;
+<a name="l01262"></a>01262 <span class="keywordtype">bool</span> isPIC = <a class="code" href="PPCISelLowering_8cpp.html#adeb13b67584232ee5ddade3d82a0b23a">GetLabelAccessInfo</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>(), MOHiFlag, MOLoFlag);
+<a name="l01263"></a>01263 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CPIHi =
+<a name="l01264"></a>01264 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4a5973fcd1193bfff9158d5a83aebd1b">getTargetConstantPool</a>(C, PtrVT, CP-><a class="code" href="classllvm_1_1ConstantPoolSDNode.html#a130b74d7047dd920dfaea193ac8b0a3d">getAlignment</a>(), 0, MOHiFlag);
+<a name="l01265"></a>01265 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CPILo =
+<a name="l01266"></a>01266 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4a5973fcd1193bfff9158d5a83aebd1b">getTargetConstantPool</a>(C, PtrVT, CP-><a class="code" href="classllvm_1_1ConstantPoolSDNode.html#a130b74d7047dd920dfaea193ac8b0a3d">getAlignment</a>(), 0, MOLoFlag);
+<a name="l01267"></a>01267 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#ab5d4759731e493988eda569efb67233f">LowerLabelRef</a>(CPIHi, CPILo, isPIC, DAG);
+<a name="l01268"></a>01268 }
+<a name="l01269"></a>01269
+<a name="l01270"></a>01270 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerJumpTable(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01271"></a>01271 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01272"></a>01272 <a class="code" href="classllvm_1_1JumpTableSDNode.html">JumpTableSDNode</a> *JT = cast<JumpTableSDNode>(Op);
+<a name="l01273"></a>01273
+<a name="l01274"></a>01274 <span class="comment">// 64-bit SVR4 ABI code is always position-independent.</span>
+<a name="l01275"></a>01275 <span class="comment">// The actual address of the GlobalValue is stored in the TOC.</span>
+<a name="l01276"></a>01276 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>() && PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>()) {
+<a name="l01277"></a>01277 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GA = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a780c45d85d7380e1e8a85c1e1d192e85">getTargetJumpTable</a>(JT-><a class="code" href="classllvm_1_1JumpTableSDNode.html#a4de66dbb2dcc5ec355a196270aad93f6">getIndex</a>(), PtrVT);
+<a name="l01278"></a>01278 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a5ac8e8dafc2dd10379a59ceff7b237d6">PPCISD::TOC_ENTRY</a>, JT-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>(), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, GA,
+<a name="l01279"></a>01279 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::X2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>));
+<a name="l01280"></a>01280 }
+<a name="l01281"></a>01281
+<a name="l01282"></a>01282 <span class="keywordtype">unsigned</span> MOHiFlag, MOLoFlag;
+<a name="l01283"></a>01283 <span class="keywordtype">bool</span> isPIC = <a class="code" href="PPCISelLowering_8cpp.html#adeb13b67584232ee5ddade3d82a0b23a">GetLabelAccessInfo</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>(), MOHiFlag, MOLoFlag);
+<a name="l01284"></a>01284 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> JTIHi = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a780c45d85d7380e1e8a85c1e1d192e85">getTargetJumpTable</a>(JT-><a class="code" href="classllvm_1_1JumpTableSDNode.html#a4de66dbb2dcc5ec355a196270aad93f6">getIndex</a>(), PtrVT, MOHiFlag);
+<a name="l01285"></a>01285 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> JTILo = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a780c45d85d7380e1e8a85c1e1d192e85">getTargetJumpTable</a>(JT-><a class="code" href="classllvm_1_1JumpTableSDNode.html#a4de66dbb2dcc5ec355a196270aad93f6">getIndex</a>(), PtrVT, MOLoFlag);
+<a name="l01286"></a>01286 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#ab5d4759731e493988eda569efb67233f">LowerLabelRef</a>(JTIHi, JTILo, isPIC, DAG);
+<a name="l01287"></a>01287 }
+<a name="l01288"></a>01288
+<a name="l01289"></a>01289 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerBlockAddress(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l01290"></a>01290 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01291"></a>01291 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01292"></a>01292
+<a name="l01293"></a>01293 <span class="keyword">const</span> <a class="code" href="classllvm_1_1BlockAddress.html">BlockAddress</a> *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
+<a name="l01294"></a>01294
+<a name="l01295"></a>01295 <span class="keywordtype">unsigned</span> MOHiFlag, MOLoFlag;
+<a name="l01296"></a>01296 <span class="keywordtype">bool</span> isPIC = <a class="code" href="PPCISelLowering_8cpp.html#adeb13b67584232ee5ddade3d82a0b23a">GetLabelAccessInfo</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>(), MOHiFlag, MOLoFlag);
+<a name="l01297"></a>01297 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TgtBAHi = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a296c3fa055022ec4c28b5745df7efdda">getTargetBlockAddress</a>(BA, PtrVT, 0, MOHiFlag);
+<a name="l01298"></a>01298 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TgtBALo = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a296c3fa055022ec4c28b5745df7efdda">getTargetBlockAddress</a>(BA, PtrVT, 0, MOLoFlag);
+<a name="l01299"></a>01299 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#ab5d4759731e493988eda569efb67233f">LowerLabelRef</a>(TgtBAHi, TgtBALo, isPIC, DAG);
+<a name="l01300"></a>01300 }
+<a name="l01301"></a>01301
+<a name="l01302"></a>01302 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerGlobalTLSAddress(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l01303"></a>01303 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01304"></a>01304
+<a name="l01305"></a>01305 <a class="code" href="classllvm_1_1GlobalAddressSDNode.html">GlobalAddressSDNode</a> *GA = cast<GlobalAddressSDNode>(Op);
+<a name="l01306"></a>01306 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = GA-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01307"></a>01307 <span class="keyword">const</span> <a class="code" href="classllvm_1_1GlobalValue.html">GlobalValue</a> *GV = GA-><a class="code" href="classllvm_1_1GlobalAddressSDNode.html#ae4b1a0675562cdfa6c89c3f96989117b">getGlobal</a>();
+<a name="l01308"></a>01308 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = <a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l01309"></a>01309 <span class="keywordtype">bool</span> is64bit = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>();
+<a name="l01310"></a>01310
+<a name="l01311"></a>01311 <a class="code" href="namespacellvm_1_1TLSModel.html#a8911c5bfb68fc4ed3ac824f04f150120">TLSModel::Model</a> model = <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a21ff907aa3b0ada12ff6031429d4dec6">getTLSModel</a>(GV);
+<a name="l01312"></a>01312
+<a name="l01313"></a>01313 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TGAHi = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac42a2722cefd536e5c88535fd4c95288">getTargetGlobalAddress</a>(GV, dl, PtrVT, 0,
+<a name="l01314"></a>01314 <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffae22c14976a5870173f77303c121aa472">PPCII::MO_TPREL16_HA</a>);
+<a name="l01315"></a>01315 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TGALo = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac42a2722cefd536e5c88535fd4c95288">getTargetGlobalAddress</a>(GV, dl, PtrVT, 0,
+<a name="l01316"></a>01316 <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffaaa6a56334c04b6445549700b36ed2c07">PPCII::MO_TPREL16_LO</a>);
+<a name="l01317"></a>01317
+<a name="l01318"></a>01318 <span class="keywordflow">if</span> (model != <a class="code" href="namespacellvm_1_1TLSModel.html#a8911c5bfb68fc4ed3ac824f04f150120ae13ef3bbe423ce80086f0a684fd25753">TLSModel::LocalExec</a>)
+<a name="l01319"></a>01319 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"only local-exec TLS mode supported"</span>);
+<a name="l01320"></a>01320 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TLSReg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(is64bit ? PPC::X13 : PPC::R2,
+<a name="l01321"></a>01321 is64bit ? <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> : <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01322"></a>01322 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ae3a56d8e7b43b7a68cbb0e7655a062cd" title="High address component (upper 16)">Hi</a> = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66afaa3b6d013f5589d52186fb31c1507de">PPCISD::Hi</a>, dl, PtrVT, TGAHi, TLSReg);
+<a name="l01323"></a>01323 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abcb9c462158b362a5edc6a1d754c9edb">PPCISD::Lo</a>, dl, PtrVT, TGALo, Hi);
+<a name="l01324"></a>01324 }
+<a name="l01325"></a>01325
+<a name="l01326"></a>01326 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerGlobalAddress(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l01327"></a>01327 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01328"></a>01328 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01329"></a>01329 <a class="code" href="classllvm_1_1GlobalAddressSDNode.html">GlobalAddressSDNode</a> *GSDN = cast<GlobalAddressSDNode>(Op);
+<a name="l01330"></a>01330 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> DL = GSDN-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01331"></a>01331 <span class="keyword">const</span> <a class="code" href="classllvm_1_1GlobalValue.html">GlobalValue</a> *GV = GSDN-><a class="code" href="classllvm_1_1GlobalAddressSDNode.html#ae4b1a0675562cdfa6c89c3f96989117b">getGlobal</a>();
+<a name="l01332"></a>01332
+<a name="l01333"></a>01333 <span class="comment">// 64-bit SVR4 ABI code is always position-independent.</span>
+<a name="l01334"></a>01334 <span class="comment">// The actual address of the GlobalValue is stored in the TOC.</span>
+<a name="l01335"></a>01335 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>() && PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>()) {
+<a name="l01336"></a>01336 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GA = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac42a2722cefd536e5c88535fd4c95288">getTargetGlobalAddress</a>(GV, DL, PtrVT, GSDN-><a class="code" href="classllvm_1_1GlobalAddressSDNode.html#a6671fb68d5def7aa31d7eb4c1898d80a">getOffset</a>());
+<a name="l01337"></a>01337 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a5ac8e8dafc2dd10379a59ceff7b237d6">PPCISD::TOC_ENTRY</a>, DL, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, GA,
+<a name="l01338"></a>01338 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::X2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>));
+<a name="l01339"></a>01339 }
+<a name="l01340"></a>01340
+<a name="l01341"></a>01341 <span class="keywordtype">unsigned</span> MOHiFlag, MOLoFlag;
+<a name="l01342"></a>01342 <span class="keywordtype">bool</span> isPIC = <a class="code" href="PPCISelLowering_8cpp.html#adeb13b67584232ee5ddade3d82a0b23a">GetLabelAccessInfo</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>(), MOHiFlag, MOLoFlag, GV);
+<a name="l01343"></a>01343
+<a name="l01344"></a>01344 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GAHi =
+<a name="l01345"></a>01345 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac42a2722cefd536e5c88535fd4c95288">getTargetGlobalAddress</a>(GV, DL, PtrVT, GSDN-><a class="code" href="classllvm_1_1GlobalAddressSDNode.html#a6671fb68d5def7aa31d7eb4c1898d80a">getOffset</a>(), MOHiFlag);
+<a name="l01346"></a>01346 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GALo =
+<a name="l01347"></a>01347 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac42a2722cefd536e5c88535fd4c95288">getTargetGlobalAddress</a>(GV, DL, PtrVT, GSDN-><a class="code" href="classllvm_1_1GlobalAddressSDNode.html#a6671fb68d5def7aa31d7eb4c1898d80a">getOffset</a>(), MOLoFlag);
+<a name="l01348"></a>01348
+<a name="l01349"></a>01349 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ptr = <a class="code" href="PPCISelLowering_8cpp.html#ab5d4759731e493988eda569efb67233f">LowerLabelRef</a>(GAHi, GALo, isPIC, DAG);
+<a name="l01350"></a>01350
+<a name="l01351"></a>01351 <span class="comment">// If the global reference is actually to a non-lazy-pointer, we have to do an</span>
+<a name="l01352"></a>01352 <span class="comment">// extra load to get the address of the global.</span>
+<a name="l01353"></a>01353 <span class="keywordflow">if</span> (MOHiFlag & <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffa4c9eaf71e784335fbfdd96354cf46235">PPCII::MO_NLP_FLAG</a>)
+<a name="l01354"></a>01354 Ptr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, DL, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad755b1a25cf0c4507d5f615f64471ae9">getEntryNode</a>(), Ptr, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l01355"></a>01355 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01356"></a>01356 <span class="keywordflow">return</span> Ptr;
+<a name="l01357"></a>01357 }
+<a name="l01358"></a>01358
+<a name="l01359"></a>01359 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerSETCC(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01360"></a>01360 <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a> = cast<CondCodeSDNode>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2))-><span class="keyword">get</span>();
+<a name="l01361"></a>01361 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l01362"></a>01362
+<a name="l01363"></a>01363 <span class="comment">// If we're comparing for equality to zero, expose the fact that this is</span>
+<a name="l01364"></a>01364 <span class="comment">// implented as a ctlz/srl pair on ppc, so that the dag combiner can</span>
+<a name="l01365"></a>01365 <span class="comment">// fold the new nodes.</span>
+<a name="l01366"></a>01366 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *C = dyn_cast<ConstantSDNode>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l01367"></a>01367 <span class="keywordflow">if</span> (C->isNullValue() && CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a>) {
+<a name="l01368"></a>01368 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01369"></a>01369 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Zext = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01370"></a>01370 <span class="keywordflow">if</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5ebe5227fe53e0dcf4102a6ebf1594a2" title="bitsLT - Return true if this has less bits than VT.">bitsLT</a>(MVT::i32)) {
+<a name="l01371"></a>01371 VT = MVT::i32;
+<a name="l01372"></a>01372 Zext = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a93fdf85eff945f1a668b4915a051453e" title="ZERO_EXTEND - Used for integer types, zeroing the new bits.">ISD::ZERO_EXTEND</a>, dl, VT, Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0));
+<a name="l01373"></a>01373 }
+<a name="l01374"></a>01374 <span class="keywordtype">unsigned</span> Log2b = <a class="code" href="namespacellvm.html#a646986783f35e0fef8988f0f28d2589f">Log2_32</a>(VT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>());
+<a name="l01375"></a>01375 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Clz = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110add33c0ae9a63902e573fc1f92fc33f1c">ISD::CTLZ</a>, dl, VT, Zext);
+<a name="l01376"></a>01376 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Scc = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>, dl, VT, Clz,
+<a name="l01377"></a>01377 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(Log2b, MVT::i32));
+<a name="l01378"></a>01378 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae690127648393001a7d5b93dc23da7b3" title="TRUNCATE - Completely drop the high bits.">ISD::TRUNCATE</a>, dl, MVT::i32, Scc);
+<a name="l01379"></a>01379 }
+<a name="l01380"></a>01380 <span class="comment">// Leave comparisons against 0 and -1 alone for now, since they're usually</span>
+<a name="l01381"></a>01381 <span class="comment">// optimized. FIXME: revisit this when we can custom lower all setcc</span>
+<a name="l01382"></a>01382 <span class="comment">// optimizations.</span>
+<a name="l01383"></a>01383 <span class="keywordflow">if</span> (C->isAllOnesValue() || C->isNullValue())
+<a name="l01384"></a>01384 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l01385"></a>01385 }
+<a name="l01386"></a>01386
+<a name="l01387"></a>01387 <span class="comment">// If we have an integer seteq/setne, turn it into a compare against zero</span>
+<a name="l01388"></a>01388 <span class="comment">// by xor'ing the rhs with the lhs, which is faster than setting a</span>
+<a name="l01389"></a>01389 <span class="comment">// condition register, reading it back out, and masking the correct bit. The</span>
+<a name="l01390"></a>01390 <span class="comment">// normal approach here uses sub to do this instead of xor. Using xor exposes</span>
+<a name="l01391"></a>01391 <span class="comment">// the result to other bit-twiddling opportunities.</span>
+<a name="l01392"></a>01392 <a class="code" href="structllvm_1_1EVT.html">EVT</a> LHSVT = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01393"></a>01393 <span class="keywordflow">if</span> (LHSVT.<a class="code" href="structllvm_1_1EVT.html#a8cc407ac00df4edd4ec4d5168d6ecb26" title="isInteger - Return true if this is an integer, or a vector integer type.">isInteger</a>() && (CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a> || CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>)) {
+<a name="l01394"></a>01394 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01395"></a>01395 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Sub = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a>, dl, LHSVT, Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0),
+<a name="l01396"></a>01396 Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1));
+<a name="l01397"></a>01397 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#aaec11804ffd22ad34531e88df8fb2aa1">getSetCC</a>(dl, VT, Sub, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(0, LHSVT), <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>);
+<a name="l01398"></a>01398 }
+<a name="l01399"></a>01399 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l01400"></a>01400 }
+<a name="l01401"></a>01401
+<a name="l01402"></a>01402 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerVAARG(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l01403"></a>01403 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a> &Subtarget)<span class="keyword"> const </span>{
+<a name="l01404"></a>01404 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Node = Op.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>();
+<a name="l01405"></a>01405 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = Node-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l01406"></a>01406 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l01407"></a>01407 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InChain = Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l01408"></a>01408 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> VAListPtr = Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l01409"></a>01409 <span class="keyword">const</span> <a class="code" href="classllvm_1_1Value.html" title="LLVM Value Representation.">Value</a> *SV = cast<SrcValueSDNode>(Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2))->getValue();
+<a name="l01410"></a>01410 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Node-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01411"></a>01411
+<a name="l01412"></a>01412 assert(!Subtarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>() && <span class="stringliteral">"LowerVAARG is PPC32 only"</span>);
+<a name="l01413"></a>01413
+<a name="l01414"></a>01414 <span class="comment">// gpr_index</span>
+<a name="l01415"></a>01415 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GprIndex = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a0f9818b48624fb3fda605d6b9e854e60">getExtLoad</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a8d89c7da4444d9ec11667aa369abc5f7">ISD::ZEXTLOAD</a>, dl, MVT::i32, InChain,
+<a name="l01416"></a>01416 VAListPtr, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(SV), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>,
+<a name="l01417"></a>01417 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01418"></a>01418 InChain = GprIndex.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l01419"></a>01419
+<a name="l01420"></a>01420 <span class="keywordflow">if</span> (VT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>) {
+<a name="l01421"></a>01421 <span class="comment">// Check if GprIndex is even</span>
+<a name="l01422"></a>01422 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GprAnd = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, dl, MVT::i32, GprIndex,
+<a name="l01423"></a>01423 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, MVT::i32));
+<a name="l01424"></a>01424 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CC64 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#aaec11804ffd22ad34531e88df8fb2aa1">getSetCC</a>(dl, MVT::i32, GprAnd,
+<a name="l01425"></a>01425 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(0, MVT::i32), <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>);
+<a name="l01426"></a>01426 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GprIndexPlusOne = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, MVT::i32, GprIndex,
+<a name="l01427"></a>01427 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, MVT::i32));
+<a name="l01428"></a>01428 <span class="comment">// Align GprIndex to be even if it isn't</span>
+<a name="l01429"></a>01429 GprIndex = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, dl, MVT::i32, CC64, GprIndexPlusOne,
+<a name="l01430"></a>01430 GprIndex);
+<a name="l01431"></a>01431 }
+<a name="l01432"></a>01432
+<a name="l01433"></a>01433 <span class="comment">// fpr index is 1 byte after gpr</span>
+<a name="l01434"></a>01434 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FprPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, VAListPtr,
+<a name="l01435"></a>01435 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, MVT::i32));
+<a name="l01436"></a>01436
+<a name="l01437"></a>01437 <span class="comment">// fpr</span>
+<a name="l01438"></a>01438 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FprIndex = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a0f9818b48624fb3fda605d6b9e854e60">getExtLoad</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a8d89c7da4444d9ec11667aa369abc5f7">ISD::ZEXTLOAD</a>, dl, MVT::i32, InChain,
+<a name="l01439"></a>01439 FprPtr, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(SV), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>,
+<a name="l01440"></a>01440 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01441"></a>01441 InChain = FprIndex.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l01442"></a>01442
+<a name="l01443"></a>01443 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegSaveAreaPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, VAListPtr,
+<a name="l01444"></a>01444 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(8, MVT::i32));
+<a name="l01445"></a>01445
+<a name="l01446"></a>01446 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OverflowAreaPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, VAListPtr,
+<a name="l01447"></a>01447 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(4, MVT::i32));
+<a name="l01448"></a>01448
+<a name="l01449"></a>01449 <span class="comment">// areas</span>
+<a name="l01450"></a>01450 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OverflowArea = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(MVT::i32, dl, InChain, OverflowAreaPtr,
+<a name="l01451"></a>01451 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>,
+<a name="l01452"></a>01452 <span class="keyword">false</span>, 0);
+<a name="l01453"></a>01453 InChain = OverflowArea.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l01454"></a>01454
+<a name="l01455"></a>01455 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegSaveArea = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(MVT::i32, dl, InChain, RegSaveAreaPtr,
+<a name="l01456"></a>01456 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>,
+<a name="l01457"></a>01457 <span class="keyword">false</span>, 0);
+<a name="l01458"></a>01458 InChain = RegSaveArea.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l01459"></a>01459
+<a name="l01460"></a>01460 <span class="comment">// select overflow_area if index > 8</span>
+<a name="l01461"></a>01461 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CC = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#aaec11804ffd22ad34531e88df8fb2aa1">getSetCC</a>(dl, MVT::i32, VT.<a class="code" href="structllvm_1_1EVT.html#a8cc407ac00df4edd4ec4d5168d6ecb26" title="isInteger - Return true if this is an integer, or a vector integer type.">isInteger</a>() ? GprIndex : FprIndex,
+<a name="l01462"></a>01462 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(8, MVT::i32), <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>);
+<a name="l01463"></a>01463
+<a name="l01464"></a>01464 <span class="comment">// adjustment constant gpr_index * 4/8</span>
+<a name="l01465"></a>01465 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegConstant = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a>, dl, MVT::i32,
+<a name="l01466"></a>01466 VT.<a class="code" href="structllvm_1_1EVT.html#a8cc407ac00df4edd4ec4d5168d6ecb26" title="isInteger - Return true if this is an integer, or a vector integer type.">isInteger</a>() ? GprIndex : FprIndex,
+<a name="l01467"></a>01467 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(VT.<a class="code" href="structllvm_1_1EVT.html#a8cc407ac00df4edd4ec4d5168d6ecb26" title="isInteger - Return true if this is an integer, or a vector integer type.">isInteger</a>() ? 4 : 8,
+<a name="l01468"></a>01468 MVT::i32));
+<a name="l01469"></a>01469
+<a name="l01470"></a>01470 <span class="comment">// OurReg = RegSaveArea + RegConstant</span>
+<a name="l01471"></a>01471 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OurReg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, RegSaveArea,
+<a name="l01472"></a>01472 RegConstant);
+<a name="l01473"></a>01473
+<a name="l01474"></a>01474 <span class="comment">// Floating types are 32 bytes into RegSaveArea</span>
+<a name="l01475"></a>01475 <span class="keywordflow">if</span> (VT.<a class="code" href="structllvm_1_1EVT.html#afc4147764cdb5599c67f747813ef9bdc" title="isFloatingPoint - Return true if this is a FP, or a vector FP type.">isFloatingPoint</a>())
+<a name="l01476"></a>01476 OurReg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, OurReg,
+<a name="l01477"></a>01477 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(32, MVT::i32));
+<a name="l01478"></a>01478
+<a name="l01479"></a>01479 <span class="comment">// increase {f,g}pr_index by 1 (or 2 if VT is i64)</span>
+<a name="l01480"></a>01480 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> IndexPlus1 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, MVT::i32,
+<a name="l01481"></a>01481 VT.<a class="code" href="structllvm_1_1EVT.html#a8cc407ac00df4edd4ec4d5168d6ecb26" title="isInteger - Return true if this is an integer, or a vector integer type.">isInteger</a>() ? GprIndex : FprIndex,
+<a name="l01482"></a>01482 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(VT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> ? 2 : 1,
+<a name="l01483"></a>01483 MVT::i32));
+<a name="l01484"></a>01484
+<a name="l01485"></a>01485 InChain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4046a9f92b29865c08e6df8815e1402b">getTruncStore</a>(InChain, dl, IndexPlus1,
+<a name="l01486"></a>01486 VT.<a class="code" href="structllvm_1_1EVT.html#a8cc407ac00df4edd4ec4d5168d6ecb26" title="isInteger - Return true if this is an integer, or a vector integer type.">isInteger</a>() ? VAListPtr : FprPtr,
+<a name="l01487"></a>01487 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(SV),
+<a name="l01488"></a>01488 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01489"></a>01489
+<a name="l01490"></a>01490 <span class="comment">// determine if we should load from reg_save_area or overflow_area</span>
+<a name="l01491"></a>01491 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Result = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, dl, PtrVT, CC, OurReg, OverflowArea);
+<a name="l01492"></a>01492
+<a name="l01493"></a>01493 <span class="comment">// increase overflow_area by 4/8 if gpr/fpr > 8</span>
+<a name="l01494"></a>01494 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OverflowAreaPlusN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, OverflowArea,
+<a name="l01495"></a>01495 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(VT.<a class="code" href="structllvm_1_1EVT.html#a8cc407ac00df4edd4ec4d5168d6ecb26" title="isInteger - Return true if this is an integer, or a vector integer type.">isInteger</a>() ? 4 : 8,
+<a name="l01496"></a>01496 MVT::i32));
+<a name="l01497"></a>01497
+<a name="l01498"></a>01498 OverflowArea = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, dl, MVT::i32, CC, OverflowArea,
+<a name="l01499"></a>01499 OverflowAreaPlusN);
+<a name="l01500"></a>01500
+<a name="l01501"></a>01501 InChain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4046a9f92b29865c08e6df8815e1402b">getTruncStore</a>(InChain, dl, OverflowArea,
+<a name="l01502"></a>01502 OverflowAreaPtr,
+<a name="l01503"></a>01503 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l01504"></a>01504 MVT::i32, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01505"></a>01505
+<a name="l01506"></a>01506 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(VT, dl, InChain, Result, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l01507"></a>01507 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01508"></a>01508 }
+<a name="l01509"></a>01509
+<a name="l01510"></a>01510 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerADJUST_TRAMPOLINE(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l01511"></a>01511 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01512"></a>01512 <span class="keywordflow">return</span> Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01513"></a>01513 }
+<a name="l01514"></a>01514
+<a name="l01515"></a>01515 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerINIT_TRAMPOLINE(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l01516"></a>01516 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l01517"></a>01517 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01518"></a>01518 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Trmp = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1); <span class="comment">// trampoline</span>
+<a name="l01519"></a>01519 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FPtr = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2); <span class="comment">// nested function</span>
+<a name="l01520"></a>01520 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Nest = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(3); <span class="comment">// 'nest' parameter value</span>
+<a name="l01521"></a>01521 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l01522"></a>01522
+<a name="l01523"></a>01523 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l01524"></a>01524 <span class="keywordtype">bool</span> isPPC64 = (PtrVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l01525"></a>01525 <a class="code" href="classllvm_1_1Type.html">Type</a> *IntPtrTy =
+<a name="l01526"></a>01526 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a0fe41e2de0ccd3e95c6645b52175c838">getDataLayout</a>()-><a class="code" href="classllvm_1_1DataLayout.html#ae84bb2408dfffa4e8b5fe2ce0714a3bd">getIntPtrType</a>(
+<a name="l01527"></a>01527 *DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>());
+<a name="l01528"></a>01528
+<a name="l01529"></a>01529 <a class="code" href="classllvm_1_1TargetLowering.html#ab6132d2ff56c64c551cf71e714dbb5c2">TargetLowering::ArgListTy</a> Args;
+<a name="l01530"></a>01530 <a class="code" href="structllvm_1_1TargetLowering_1_1ArgListEntry.html">TargetLowering::ArgListEntry</a> Entry;
+<a name="l01531"></a>01531
+<a name="l01532"></a>01532 Entry.<a class="code" href="structllvm_1_1TargetLowering_1_1ArgListEntry.html#a5d2b21233cb3005cfa01f9cfb260f094">Ty</a> = IntPtrTy;
+<a name="l01533"></a>01533 Entry.<a class="code" href="structllvm_1_1TargetLowering_1_1ArgListEntry.html#a7d3f92aa62dcbaa4321822b441e384e6">Node</a> = Trmp; Args.push_back(Entry);
+<a name="l01534"></a>01534
+<a name="l01535"></a>01535 <span class="comment">// TrampSize == (isPPC64 ? 48 : 40);</span>
+<a name="l01536"></a>01536 Entry.<a class="code" href="structllvm_1_1TargetLowering_1_1ArgListEntry.html#a7d3f92aa62dcbaa4321822b441e384e6">Node</a> = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(isPPC64 ? 48 : 40,
+<a name="l01537"></a>01537 isPPC64 ? <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> : MVT::i32);
+<a name="l01538"></a>01538 Args.push_back(Entry);
+<a name="l01539"></a>01539
+<a name="l01540"></a>01540 Entry.<a class="code" href="structllvm_1_1TargetLowering_1_1ArgListEntry.html#a7d3f92aa62dcbaa4321822b441e384e6">Node</a> = FPtr; Args.push_back(Entry);
+<a name="l01541"></a>01541 Entry.<a class="code" href="structllvm_1_1TargetLowering_1_1ArgListEntry.html#a7d3f92aa62dcbaa4321822b441e384e6">Node</a> = Nest; Args.push_back(Entry);
+<a name="l01542"></a>01542
+<a name="l01543"></a>01543 <span class="comment">// Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)</span>
+<a name="l01544"></a>01544 <a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html">TargetLowering::CallLoweringInfo</a> CLI(Chain,
+<a name="l01545"></a>01545 <a class="code" href="classllvm_1_1Type.html#a6e20e76960d952de088354cbcd14c3ab">Type::getVoidTy</a>(*DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>()),
+<a name="l01546"></a>01546 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0,
+<a name="l01547"></a>01547 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">CallingConv::C</a>,
+<a name="l01548"></a>01548 <span class="comment">/*isTailCall=*/</span><span class="keyword">false</span>,
+<a name="l01549"></a>01549 <span class="comment">/*doesNotRet=*/</span><span class="keyword">false</span>,
+<a name="l01550"></a>01550 <span class="comment">/*isReturnValueUsed=*/</span><span class="keyword">true</span>,
+<a name="l01551"></a>01551 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#aa8f1c26a4e070ead6c67b4e9a5d93124">getExternalSymbol</a>(<span class="stringliteral">"__trampoline_setup"</span>, PtrVT),
+<a name="l01552"></a>01552 Args, DAG, dl);
+<a name="l01553"></a>01553 std::pair<SDValue, SDValue> CallResult = <a class="code" href="classllvm_1_1TargetLowering.html#a395ec1cfea698db112b7e8709dca547d">LowerCallTo</a>(CLI);
+<a name="l01554"></a>01554
+<a name="l01555"></a>01555 <span class="keywordflow">return</span> CallResult.second;
+<a name="l01556"></a>01556 }
+<a name="l01557"></a>01557
+<a name="l01558"></a>01558 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerVASTART(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l01559"></a>01559 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a> &Subtarget)<span class="keyword"> const </span>{
+<a name="l01560"></a>01560 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l01561"></a>01561 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FuncInfo = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l01562"></a>01562
+<a name="l01563"></a>01563 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l01564"></a>01564
+<a name="l01565"></a>01565 <span class="keywordflow">if</span> (Subtarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#a27ef3d0113fbcca318c3ed2a86116932">isDarwinABI</a>() || Subtarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>()) {
+<a name="l01566"></a>01566 <span class="comment">// vastart just stores the address of the VarArgsFrameIndex slot into the</span>
+<a name="l01567"></a>01567 <span class="comment">// memory location argument.</span>
+<a name="l01568"></a>01568 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l01569"></a>01569 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FR = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a0a78984133f621514980f087442645b4">getVarArgsFrameIndex</a>(), PtrVT);
+<a name="l01570"></a>01570 <span class="keyword">const</span> <a class="code" href="classllvm_1_1Value.html" title="LLVM Value Representation.">Value</a> *SV = cast<SrcValueSDNode>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2))->getValue();
+<a name="l01571"></a>01571 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), dl, FR, Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1),
+<a name="l01572"></a>01572 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(SV),
+<a name="l01573"></a>01573 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01574"></a>01574 }
+<a name="l01575"></a>01575
+<a name="l01576"></a>01576 <span class="comment">// For the 32-bit SVR4 ABI we follow the layout of the va_list struct.</span>
+<a name="l01577"></a>01577 <span class="comment">// We suppose the given va_list is already allocated.</span>
+<a name="l01578"></a>01578 <span class="comment">//</span>
+<a name="l01579"></a>01579 <span class="comment">// typedef struct {</span>
+<a name="l01580"></a>01580 <span class="comment">// char gpr; /* index into the array of 8 GPRs</span>
+<a name="l01581"></a>01581 <span class="comment">// * stored in the register save area</span>
+<a name="l01582"></a>01582 <span class="comment">// * gpr=0 corresponds to r3,</span>
+<a name="l01583"></a>01583 <span class="comment">// * gpr=1 to r4, etc.</span>
+<a name="l01584"></a>01584 <span class="comment">// */</span>
+<a name="l01585"></a>01585 <span class="comment">// char fpr; /* index into the array of 8 FPRs</span>
+<a name="l01586"></a>01586 <span class="comment">// * stored in the register save area</span>
+<a name="l01587"></a>01587 <span class="comment">// * fpr=0 corresponds to f1,</span>
+<a name="l01588"></a>01588 <span class="comment">// * fpr=1 to f2, etc.</span>
+<a name="l01589"></a>01589 <span class="comment">// */</span>
+<a name="l01590"></a>01590 <span class="comment">// char *overflow_arg_area;</span>
+<a name="l01591"></a>01591 <span class="comment">// /* location on stack that holds</span>
+<a name="l01592"></a>01592 <span class="comment">// * the next overflow argument</span>
+<a name="l01593"></a>01593 <span class="comment">// */</span>
+<a name="l01594"></a>01594 <span class="comment">// char *reg_save_area;</span>
+<a name="l01595"></a>01595 <span class="comment">// /* where r3:r10 and f1:f8 (if saved)</span>
+<a name="l01596"></a>01596 <span class="comment">// * are stored</span>
+<a name="l01597"></a>01597 <span class="comment">// */</span>
+<a name="l01598"></a>01598 <span class="comment">// } va_list[1];</span>
+<a name="l01599"></a>01599
+<a name="l01600"></a>01600
+<a name="l01601"></a>01601 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ArgGPR = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a3aa70a123e676b63f9de9f668997f7e3">getVarArgsNumGPR</a>(), MVT::i32);
+<a name="l01602"></a>01602 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ArgFPR = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a2178fdaddb3a80610707339be13fa6e0">getVarArgsNumFPR</a>(), MVT::i32);
+<a name="l01603"></a>01603
+<a name="l01604"></a>01604
+<a name="l01605"></a>01605 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l01606"></a>01606
+<a name="l01607"></a>01607 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> StackOffsetFI = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a2c04006f5187665a2b06483b76c1917a">getVarArgsStackOffset</a>(),
+<a name="l01608"></a>01608 PtrVT);
+<a name="l01609"></a>01609 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FR = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a0a78984133f621514980f087442645b4">getVarArgsFrameIndex</a>(),
+<a name="l01610"></a>01610 PtrVT);
+<a name="l01611"></a>01611
+<a name="l01612"></a>01612 uint64_t FrameOffset = PtrVT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8;
+<a name="l01613"></a>01613 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ConstFrameOffset = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(FrameOffset, PtrVT);
+<a name="l01614"></a>01614
+<a name="l01615"></a>01615 uint64_t StackOffset = PtrVT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8 - 1;
+<a name="l01616"></a>01616 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ConstStackOffset = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(StackOffset, PtrVT);
+<a name="l01617"></a>01617
+<a name="l01618"></a>01618 uint64_t FPROffset = 1;
+<a name="l01619"></a>01619 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ConstFPROffset = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(FPROffset, PtrVT);
+<a name="l01620"></a>01620
+<a name="l01621"></a>01621 <span class="keyword">const</span> <a class="code" href="classllvm_1_1Value.html" title="LLVM Value Representation.">Value</a> *SV = cast<SrcValueSDNode>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2))->getValue();
+<a name="l01622"></a>01622
+<a name="l01623"></a>01623 <span class="comment">// Store first byte : number of int regs</span>
+<a name="l01624"></a>01624 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> firstStore = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4046a9f92b29865c08e6df8815e1402b">getTruncStore</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), dl, ArgGPR,
+<a name="l01625"></a>01625 Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1),
+<a name="l01626"></a>01626 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(SV),
+<a name="l01627"></a>01627 MVT::i8, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01628"></a>01628 uint64_t nextOffset = FPROffset;
+<a name="l01629"></a>01629 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> nextPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1),
+<a name="l01630"></a>01630 ConstFPROffset);
+<a name="l01631"></a>01631
+<a name="l01632"></a>01632 <span class="comment">// Store second byte : number of float regs</span>
+<a name="l01633"></a>01633 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> secondStore =
+<a name="l01634"></a>01634 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4046a9f92b29865c08e6df8815e1402b">getTruncStore</a>(firstStore, dl, ArgFPR, nextPtr,
+<a name="l01635"></a>01635 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(SV, nextOffset), MVT::i8,
+<a name="l01636"></a>01636 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01637"></a>01637 nextOffset += StackOffset;
+<a name="l01638"></a>01638 nextPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, nextPtr, ConstStackOffset);
+<a name="l01639"></a>01639
+<a name="l01640"></a>01640 <span class="comment">// Store second word : arguments given on stack</span>
+<a name="l01641"></a>01641 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> thirdStore =
+<a name="l01642"></a>01642 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(secondStore, dl, StackOffsetFI, nextPtr,
+<a name="l01643"></a>01643 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(SV, nextOffset),
+<a name="l01644"></a>01644 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01645"></a>01645 nextOffset += FrameOffset;
+<a name="l01646"></a>01646 nextPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, nextPtr, ConstFrameOffset);
+<a name="l01647"></a>01647
+<a name="l01648"></a>01648 <span class="comment">// Store third word : arguments given in registers</span>
+<a name="l01649"></a>01649 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(thirdStore, dl, FR, nextPtr,
+<a name="l01650"></a>01650 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(SV, nextOffset),
+<a name="l01651"></a>01651 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01652"></a>01652
+<a name="l01653"></a>01653 }
+<a name="l01654"></a>01654
+<a name="l01655"></a>01655 <span class="preprocessor">#include "PPCGenCallingConv.inc"</span>
+<a name="l01656"></a>01656
+<a name="l01657"></a><a class="code" href="PPCISelLowering_8cpp.html#a4681e9291a864ce414f99b9993fa1c4f">01657</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#a4681e9291a864ce414f99b9993fa1c4f">CC_PPC_SVR4_Custom_Dummy</a>(<span class="keywordtype">unsigned</span> &ValNo, <a class="code" href="classllvm_1_1MVT.html">MVT</a> &ValVT, <a class="code" href="classllvm_1_1MVT.html">MVT</a> &LocVT,
+<a name="l01658"></a>01658 <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45">CCValAssign::LocInfo</a> &LocInfo,
+<a name="l01659"></a>01659 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> &ArgFlags,
+<a name="l01660"></a>01660 <a class="code" href="classllvm_1_1CCState.html">CCState</a> &State) {
+<a name="l01661"></a>01661 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01662"></a>01662 }
+<a name="l01663"></a>01663
+<a name="l01664"></a><a class="code" href="PPCISelLowering_8cpp.html#a39f14542b4ad3861660fea58481d7409">01664</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#a39f14542b4ad3861660fea58481d7409">CC_PPC_SVR4_Custom_AlignArgRegs</a>(<span class="keywordtype">unsigned</span> &ValNo, <a class="code" href="classllvm_1_1MVT.html">MVT</a> &ValVT,
+<a name="l01665"></a>01665 <a class="code" href="classllvm_1_1MVT.html">MVT</a> &LocVT,
+<a name="l01666"></a>01666 <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45">CCValAssign::LocInfo</a> &LocInfo,
+<a name="l01667"></a>01667 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> &ArgFlags,
+<a name="l01668"></a>01668 <a class="code" href="classllvm_1_1CCState.html">CCState</a> &State) {
+<a name="l01669"></a>01669 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t ArgRegs[] = {
+<a name="l01670"></a>01670 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+<a name="l01671"></a>01671 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+<a name="l01672"></a>01672 };
+<a name="l01673"></a>01673 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumArgRegs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(ArgRegs);
+<a name="l01674"></a>01674
+<a name="l01675"></a>01675 <span class="keywordtype">unsigned</span> RegNum = State.<a class="code" href="classllvm_1_1CCState.html#aea636e30afd00adc2d5df11e73fb205c">getFirstUnallocated</a>(ArgRegs, NumArgRegs);
+<a name="l01676"></a>01676
+<a name="l01677"></a>01677 <span class="comment">// Skip one register if the first unallocated register has an even register</span>
+<a name="l01678"></a>01678 <span class="comment">// number and there are still argument registers available which have not been</span>
+<a name="l01679"></a>01679 <span class="comment">// allocated yet. RegNum is actually an index into ArgRegs, which means we</span>
+<a name="l01680"></a>01680 <span class="comment">// need to skip a register if RegNum is odd.</span>
+<a name="l01681"></a>01681 <span class="keywordflow">if</span> (RegNum != NumArgRegs && RegNum % 2 == 1) {
+<a name="l01682"></a>01682 State.<a class="code" href="classllvm_1_1CCState.html#a5a67878322183059c969a26b2f232031">AllocateReg</a>(ArgRegs[RegNum]);
+<a name="l01683"></a>01683 }
+<a name="l01684"></a>01684
+<a name="l01685"></a>01685 <span class="comment">// Always return false here, as this function only makes sure that the first</span>
+<a name="l01686"></a>01686 <span class="comment">// unallocated register has an odd register number and does not actually</span>
+<a name="l01687"></a>01687 <span class="comment">// allocate a register for the current argument.</span>
+<a name="l01688"></a>01688 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01689"></a>01689 }
+<a name="l01690"></a>01690
+<a name="l01691"></a><a class="code" href="PPCISelLowering_8cpp.html#af90d91f7fcb6fe7789fd8d9a8641f7e4">01691</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#af90d91f7fcb6fe7789fd8d9a8641f7e4">CC_PPC_SVR4_Custom_AlignFPArgRegs</a>(<span class="keywordtype">unsigned</span> &ValNo, <a class="code" href="classllvm_1_1MVT.html">MVT</a> &ValVT,
+<a name="l01692"></a>01692 <a class="code" href="classllvm_1_1MVT.html">MVT</a> &LocVT,
+<a name="l01693"></a>01693 <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45">CCValAssign::LocInfo</a> &LocInfo,
+<a name="l01694"></a>01694 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> &ArgFlags,
+<a name="l01695"></a>01695 <a class="code" href="classllvm_1_1CCState.html">CCState</a> &State) {
+<a name="l01696"></a>01696 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t ArgRegs[] = {
+<a name="l01697"></a>01697 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+<a name="l01698"></a>01698 PPC::F8
+<a name="l01699"></a>01699 };
+<a name="l01700"></a>01700
+<a name="l01701"></a>01701 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumArgRegs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(ArgRegs);
+<a name="l01702"></a>01702
+<a name="l01703"></a>01703 <span class="keywordtype">unsigned</span> RegNum = State.<a class="code" href="classllvm_1_1CCState.html#aea636e30afd00adc2d5df11e73fb205c">getFirstUnallocated</a>(ArgRegs, NumArgRegs);
+<a name="l01704"></a>01704
+<a name="l01705"></a>01705 <span class="comment">// If there is only one Floating-point register left we need to put both f64</span>
+<a name="l01706"></a>01706 <span class="comment">// values of a split ppc_fp128 value on the stack.</span>
+<a name="l01707"></a>01707 <span class="keywordflow">if</span> (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
+<a name="l01708"></a>01708 State.<a class="code" href="classllvm_1_1CCState.html#a5a67878322183059c969a26b2f232031">AllocateReg</a>(ArgRegs[RegNum]);
+<a name="l01709"></a>01709 }
+<a name="l01710"></a>01710
+<a name="l01711"></a>01711 <span class="comment">// Always return false here, as this function only makes sure that the two f64</span>
+<a name="l01712"></a>01712 <span class="comment">// values a ppc_fp128 value is split into are both passed in registers or both</span>
+<a name="l01713"></a>01713 <span class="comment">// passed on the stack and does not actually allocate a register for the</span>
+<a name="l01714"></a>01714 <span class="comment">// current argument.</span>
+<a name="l01715"></a>01715 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01716"></a>01716 }
+<a name="l01717"></a>01717 <span class="comment"></span>
+<a name="l01718"></a>01718 <span class="comment">/// GetFPR - Get the set of FP registers that should be allocated for arguments,</span>
+<a name="l01719"></a>01719 <span class="comment">/// on Darwin.</span>
+<a name="l01720"></a><a class="code" href="PPCISelLowering_8cpp.html#a1cbd108eaf5aca7619ff85c02489c3a1">01720</a> <span class="comment"></span><span class="keyword">static</span> <span class="keyword">const</span> uint16_t *<a class="code" href="PPCISelLowering_8cpp.html#a1cbd108eaf5aca7619ff85c02489c3a1">GetFPR</a>() {
+<a name="l01721"></a>01721 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t FPR[] = {
+<a name="l01722"></a>01722 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+<a name="l01723"></a>01723 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
+<a name="l01724"></a>01724 };
+<a name="l01725"></a>01725
+<a name="l01726"></a>01726 <span class="keywordflow">return</span> FPR;
+<a name="l01727"></a>01727 }
+<a name="l01728"></a>01728 <span class="comment"></span>
+<a name="l01729"></a>01729 <span class="comment">/// CalculateStackSlotSize - Calculates the size reserved for this argument on</span>
+<a name="l01730"></a>01730 <span class="comment">/// the stack.</span>
+<a name="l01731"></a><a class="code" href="PPCISelLowering_8cpp.html#aacd7e508c9e6dd17afc738da27b87bc2">01731</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">unsigned</span> <a class="code" href="PPCISelLowering_8cpp.html#aacd7e508c9e6dd17afc738da27b87bc2">CalculateStackSlotSize</a>(<a class="code" href="structllvm_1_1EVT.html">EVT</a> ArgVT, <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags,
+<a name="l01732"></a>01732 <span class="keywordtype">unsigned</span> PtrByteSize) {
+<a name="l01733"></a>01733 <span class="keywordtype">unsigned</span> ArgSize = ArgVT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8;
+<a name="l01734"></a>01734 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a34ee642bf0fb623f775e04e0e60d9b26">isByVal</a>())
+<a name="l01735"></a>01735 ArgSize = Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a20485215f1c6f05a5c5209725c93de2f">getByValSize</a>();
+<a name="l01736"></a>01736 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
+<a name="l01737"></a>01737
+<a name="l01738"></a>01738 <span class="keywordflow">return</span> ArgSize;
+<a name="l01739"></a>01739 }
+<a name="l01740"></a>01740
+<a name="l01741"></a>01741 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l01742"></a>01742 PPCTargetLowering::LowerFormalArguments(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l01743"></a>01743 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l01744"></a>01744 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a>
+<a name="l01745"></a>01745 &<a class="code" href="namespacellvm_1_1MipsISD.html#a7a7035feda1dc16252a7a15a7e230122ad5006873d15f9569d1cf09deef3c6363">Ins</a>,
+<a name="l01746"></a>01746 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l01747"></a>01747 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"></span>
+<a name="l01748"></a>01748 <span class="keyword"> const </span>{
+<a name="l01749"></a>01749 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>()) {
+<a name="l01750"></a>01750 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>())
+<a name="l01751"></a>01751 <span class="keywordflow">return</span> LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
+<a name="l01752"></a>01752 dl, DAG, InVals);
+<a name="l01753"></a>01753 <span class="keywordflow">else</span>
+<a name="l01754"></a>01754 <span class="keywordflow">return</span> LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
+<a name="l01755"></a>01755 dl, DAG, InVals);
+<a name="l01756"></a>01756 } <span class="keywordflow">else</span> {
+<a name="l01757"></a>01757 <span class="keywordflow">return</span> LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
+<a name="l01758"></a>01758 dl, DAG, InVals);
+<a name="l01759"></a>01759 }
+<a name="l01760"></a>01760 }
+<a name="l01761"></a>01761
+<a name="l01762"></a>01762 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l01763"></a>01763 PPCTargetLowering::LowerFormalArguments_32SVR4(
+<a name="l01764"></a>01764 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l01765"></a>01765 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l01766"></a>01766 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a>
+<a name="l01767"></a>01767 &Ins,
+<a name="l01768"></a>01768 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l01769"></a>01769 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l01770"></a>01770
+<a name="l01771"></a>01771 <span class="comment">// 32-bit SVR4 ABI Stack Frame Layout:</span>
+<a name="l01772"></a>01772 <span class="comment">// +-----------------------------------+</span>
+<a name="l01773"></a>01773 <span class="comment">// +--> | Back chain |</span>
+<a name="l01774"></a>01774 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01775"></a>01775 <span class="comment">// | | Floating-point register save area |</span>
+<a name="l01776"></a>01776 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01777"></a>01777 <span class="comment">// | | General register save area |</span>
+<a name="l01778"></a>01778 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01779"></a>01779 <span class="comment">// | | CR save word |</span>
+<a name="l01780"></a>01780 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01781"></a>01781 <span class="comment">// | | VRSAVE save word |</span>
+<a name="l01782"></a>01782 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01783"></a>01783 <span class="comment">// | | Alignment padding |</span>
+<a name="l01784"></a>01784 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01785"></a>01785 <span class="comment">// | | Vector register save area |</span>
+<a name="l01786"></a>01786 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01787"></a>01787 <span class="comment">// | | Local variable space |</span>
+<a name="l01788"></a>01788 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01789"></a>01789 <span class="comment">// | | Parameter list area |</span>
+<a name="l01790"></a>01790 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01791"></a>01791 <span class="comment">// | | LR save word |</span>
+<a name="l01792"></a>01792 <span class="comment">// | +-----------------------------------+</span>
+<a name="l01793"></a>01793 <span class="comment">// SP--> +--- | Back chain |</span>
+<a name="l01794"></a>01794 <span class="comment">// +-----------------------------------+</span>
+<a name="l01795"></a>01795 <span class="comment">//</span>
+<a name="l01796"></a>01796 <span class="comment">// Specifications:</span>
+<a name="l01797"></a>01797 <span class="comment">// System V Application Binary Interface PowerPC Processor Supplement</span>
+<a name="l01798"></a>01798 <span class="comment">// AltiVec Technology Programming Interface Manual</span>
+<a name="l01799"></a>01799
+<a name="l01800"></a>01800 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l01801"></a>01801 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l01802"></a>01802 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FuncInfo = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l01803"></a>01803
+<a name="l01804"></a>01804 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l01805"></a>01805 <span class="comment">// Potential tail calls could cause overwriting of argument stack slots.</span>
+<a name="l01806"></a>01806 <span class="keywordtype">bool</span> isImmutable = !(<a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ab1fb67187fc37e569cc5171cbebba873">Options</a>.<a class="code" href="classllvm_1_1TargetOptions.html#ad54fc81a4ef7ab96137a9b6e78fdf838">GuaranteedTailCallOpt</a> &&
+<a name="l01807"></a>01807 (CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a>));
+<a name="l01808"></a>01808 <span class="keywordtype">unsigned</span> PtrByteSize = 4;
+<a name="l01809"></a>01809
+<a name="l01810"></a>01810 <span class="comment">// Assign locations to all of the incoming arguments.</span>
+<a name="l01811"></a>01811 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<CCValAssign, 16></a> ArgLocs;
+<a name="l01812"></a>01812 <a class="code" href="classllvm_1_1CCState.html">CCState</a> CCInfo(CallConv, isVarArg, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>(),
+<a name="l01813"></a>01813 <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>(), ArgLocs, *DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>());
+<a name="l01814"></a>01814
+<a name="l01815"></a>01815 <span class="comment">// Reserve space for the linkage area on the stack.</span>
+<a name="l01816"></a>01816 CCInfo.<a class="code" href="classllvm_1_1CCState.html#accd683afb417ec1f0f44c62c8b5a8fc4">AllocateStack</a>(<a class="code" href="classllvm_1_1PPCFrameLowering.html#ab90d8608756fd53ed946d0eab8ad6cb7">PPCFrameLowering::getLinkageSize</a>(<span class="keyword">false</span>, <span class="keyword">false</span>), PtrByteSize);
+<a name="l01817"></a>01817
+<a name="l01818"></a>01818 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
+<a name="l01819"></a>01819
+<a name="l01820"></a>01820 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = ArgLocs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i != e; ++i) {
+<a name="l01821"></a>01821 <a class="code" href="classllvm_1_1CCValAssign.html" title="CCValAssign - Represent assignment of one arg/retval to a location.">CCValAssign</a> &VA = ArgLocs[i];
+<a name="l01822"></a>01822
+<a name="l01823"></a>01823 <span class="comment">// Arguments stored in registers.</span>
+<a name="l01824"></a>01824 <span class="keywordflow">if</span> (VA.<a class="code" href="classllvm_1_1CCValAssign.html#afcfd7d2322b397d0d55a4595dea52e3c">isRegLoc</a>()) {
+<a name="l01825"></a>01825 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *RC;
+<a name="l01826"></a>01826 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ValVT = VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae603fba6e8709cb50d43f38c4305e46b">getValVT</a>();
+<a name="l01827"></a>01827
+<a name="l01828"></a>01828 <span class="keywordflow">switch</span> (ValVT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l01829"></a>01829 <span class="keywordflow">default</span>:
+<a name="l01830"></a>01830 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"ValVT not supported by formal arguments Lowering"</span>);
+<a name="l01831"></a>01831 <span class="keywordflow">case</span> MVT::i32:
+<a name="l01832"></a>01832 RC = &PPC::GPRCRegClass;
+<a name="l01833"></a>01833 <span class="keywordflow">break</span>;
+<a name="l01834"></a>01834 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>:
+<a name="l01835"></a>01835 RC = &PPC::F4RCRegClass;
+<a name="l01836"></a>01836 <span class="keywordflow">break</span>;
+<a name="l01837"></a>01837 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>:
+<a name="l01838"></a>01838 RC = &PPC::F8RCRegClass;
+<a name="l01839"></a>01839 <span class="keywordflow">break</span>;
+<a name="l01840"></a>01840 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>:
+<a name="l01841"></a>01841 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>:
+<a name="l01842"></a>01842 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>:
+<a name="l01843"></a>01843 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l01844"></a>01844 RC = &PPC::VRRCRegClass;
+<a name="l01845"></a>01845 <span class="keywordflow">break</span>;
+<a name="l01846"></a>01846 }
+<a name="l01847"></a>01847
+<a name="l01848"></a>01848 <span class="comment">// Transform the arguments stored in physical registers into virtual ones.</span>
+<a name="l01849"></a>01849 <span class="keywordtype">unsigned</span> <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a> = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(VA.<a class="code" href="classllvm_1_1CCValAssign.html#a5cb182c203efa2f1fc4797fb76b15daf">getLocReg</a>(), RC);
+<a name="l01850"></a>01850 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ArgValue = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, Reg, ValVT);
+<a name="l01851"></a>01851
+<a name="l01852"></a>01852 InVals.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(ArgValue);
+<a name="l01853"></a>01853 } <span class="keywordflow">else</span> {
+<a name="l01854"></a>01854 <span class="comment">// Argument stored in memory.</span>
+<a name="l01855"></a>01855 assert(VA.<a class="code" href="classllvm_1_1CCValAssign.html#a5b5b7a20dd6b367935d4f44744ab6e08">isMemLoc</a>());
+<a name="l01856"></a>01856
+<a name="l01857"></a>01857 <span class="keywordtype">unsigned</span> ArgSize = VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae59804b87136d0ddf452a25b025b768c">getLocVT</a>().<a class="code" href="classllvm_1_1MVT.html#a423166b2b5d1010162dde0003e5ad09c">getSizeInBits</a>() / 8;
+<a name="l01858"></a>01858 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(ArgSize, VA.<a class="code" href="classllvm_1_1CCValAssign.html#a7b19fa41486ca39142442dd962c8d3b6">getLocMemOffset</a>(),
+<a name="l01859"></a>01859 isImmutable);
+<a name="l01860"></a>01860
+<a name="l01861"></a>01861 <span class="comment">// Create load nodes to retrieve arguments from the stack.</span>
+<a name="l01862"></a>01862 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l01863"></a>01863 InVals.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae603fba6e8709cb50d43f38c4305e46b">getValVT</a>(), dl, Chain, FIN,
+<a name="l01864"></a>01864 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l01865"></a>01865 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0));
+<a name="l01866"></a>01866 }
+<a name="l01867"></a>01867 }
+<a name="l01868"></a>01868
+<a name="l01869"></a>01869 <span class="comment">// Assign locations to all of the incoming aggregate by value arguments.</span>
+<a name="l01870"></a>01870 <span class="comment">// Aggregates passed by value are stored in the local variable space of the</span>
+<a name="l01871"></a>01871 <span class="comment">// caller's stack frame, right above the parameter list area.</span>
+<a name="l01872"></a>01872 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<CCValAssign, 16></a> ByValArgLocs;
+<a name="l01873"></a>01873 <a class="code" href="classllvm_1_1CCState.html">CCState</a> CCByValInfo(CallConv, isVarArg, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>(),
+<a name="l01874"></a>01874 <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>(), ByValArgLocs, *DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>());
+<a name="l01875"></a>01875
+<a name="l01876"></a>01876 <span class="comment">// Reserve stack space for the allocations in CCInfo.</span>
+<a name="l01877"></a>01877 CCByValInfo.<a class="code" href="classllvm_1_1CCState.html#accd683afb417ec1f0f44c62c8b5a8fc4">AllocateStack</a>(CCInfo.getNextStackOffset(), PtrByteSize);
+<a name="l01878"></a>01878
+<a name="l01879"></a>01879 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
+<a name="l01880"></a>01880
+<a name="l01881"></a>01881 <span class="comment">// Area that is at least reserved in the caller of this function.</span>
+<a name="l01882"></a>01882 <span class="keywordtype">unsigned</span> MinReservedArea = CCByValInfo.getNextStackOffset();
+<a name="l01883"></a>01883
+<a name="l01884"></a>01884 <span class="comment">// Set the size that is at least reserved in caller of this function. Tail</span>
+<a name="l01885"></a>01885 <span class="comment">// call optimized function's reserved stack space needs to be aligned so that</span>
+<a name="l01886"></a>01886 <span class="comment">// taking the difference between two stack areas will result in an aligned</span>
+<a name="l01887"></a>01887 <span class="comment">// stack.</span>
+<a name="l01888"></a>01888 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l01889"></a>01889
+<a name="l01890"></a>01890 MinReservedArea =
+<a name="l01891"></a>01891 std::max(MinReservedArea,
+<a name="l01892"></a>01892 <a class="code" href="classllvm_1_1PPCFrameLowering.html#ad6cf9c804045cfe1b414dd12b18e86ca">PPCFrameLowering::getMinCallFrameSize</a>(<span class="keyword">false</span>, <span class="keyword">false</span>));
+<a name="l01893"></a>01893
+<a name="l01894"></a>01894 <span class="keywordtype">unsigned</span> TargetAlign = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a02aa9d4cbd6ffcc70dfe1143ec0995ef">getFrameLowering</a>()->
+<a name="l01895"></a>01895 getStackAlignment();
+<a name="l01896"></a>01896 <span class="keywordtype">unsigned</span> AlignMask = TargetAlign-1;
+<a name="l01897"></a>01897 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
+<a name="l01898"></a>01898
+<a name="l01899"></a>01899 FI-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a8e0b7625b4133471e51249e77ef84c81">setMinReservedArea</a>(MinReservedArea);
+<a name="l01900"></a>01900
+<a name="l01901"></a>01901 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> MemOps;
+<a name="l01902"></a>01902
+<a name="l01903"></a>01903 <span class="comment">// If the function takes variable number of arguments, make a frame index for</span>
+<a name="l01904"></a>01904 <span class="comment">// the start of the first vararg value... for expansion of llvm.va_start.</span>
+<a name="l01905"></a>01905 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l01906"></a>01906 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t GPArgRegs[] = {
+<a name="l01907"></a>01907 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+<a name="l01908"></a>01908 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+<a name="l01909"></a>01909 };
+<a name="l01910"></a>01910 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumGPArgRegs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(GPArgRegs);
+<a name="l01911"></a>01911
+<a name="l01912"></a>01912 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t FPArgRegs[] = {
+<a name="l01913"></a>01913 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
+<a name="l01914"></a>01914 PPC::F8
+<a name="l01915"></a>01915 };
+<a name="l01916"></a>01916 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumFPArgRegs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(FPArgRegs);
+<a name="l01917"></a>01917
+<a name="l01918"></a>01918 FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a4555f7c774794316ae5ce15ff8cda889">setVarArgsNumGPR</a>(CCInfo.getFirstUnallocated(GPArgRegs,
+<a name="l01919"></a>01919 NumGPArgRegs));
+<a name="l01920"></a>01920 FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a0d10581957463a46f2142a8e5efbd1f8">setVarArgsNumFPR</a>(CCInfo.getFirstUnallocated(FPArgRegs,
+<a name="l01921"></a>01921 NumFPArgRegs));
+<a name="l01922"></a>01922
+<a name="l01923"></a>01923 <span class="comment">// Make room for NumGPArgRegs and NumFPArgRegs.</span>
+<a name="l01924"></a>01924 <span class="keywordtype">int</span> Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
+<a name="l01925"></a>01925 NumFPArgRegs * <a class="code" href="structllvm_1_1EVT.html">EVT</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>).<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8;
+<a name="l01926"></a>01926
+<a name="l01927"></a>01927 FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#ac48baf3479d85046d9613e91423bb05b">setVarArgsStackOffset</a>(
+<a name="l01928"></a>01928 MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(PtrVT.getSizeInBits()/8,
+<a name="l01929"></a>01929 CCInfo.getNextStackOffset(), <span class="keyword">true</span>));
+<a name="l01930"></a>01930
+<a name="l01931"></a>01931 FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#ada6f0ce61d2e0bfaef869dffc2d643ed">setVarArgsFrameIndex</a>(MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#acd4dd34a1fe2579c4e2a349aacd76bcb">CreateStackObject</a>(Depth, 8, <span class="keyword">false</span>));
+<a name="l01932"></a>01932 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a0a78984133f621514980f087442645b4">getVarArgsFrameIndex</a>(), PtrVT);
+<a name="l01933"></a>01933
+<a name="l01934"></a>01934 <span class="comment">// The fixed integer arguments of a variadic function are stored to the</span>
+<a name="l01935"></a>01935 <span class="comment">// VarArgsFrameIndex on the stack so that they may be loaded by deferencing</span>
+<a name="l01936"></a>01936 <span class="comment">// the result of va_next.</span>
+<a name="l01937"></a>01937 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
+<a name="l01938"></a>01938 <span class="comment">// Get an existing live-in vreg, or add a new one.</span>
+<a name="l01939"></a>01939 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a957027d4e9d0442f3bf1a0d7db0ba253">getLiveInVirtReg</a>(GPArgRegs[GPRIndex]);
+<a name="l01940"></a>01940 <span class="keywordflow">if</span> (!VReg)
+<a name="l01941"></a>01941 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
+<a name="l01942"></a>01942
+<a name="l01943"></a>01943 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, PtrVT);
+<a name="l01944"></a>01944 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1SPII.html#add994c36633ba2d8f6a1366b775e88a6a36b3dd3b84fde3f8494a9b18af131856">Store</a> = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l01945"></a>01945 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01946"></a>01946 MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l01947"></a>01947 <span class="comment">// Increment the address by four for the next argument to store</span>
+<a name="l01948"></a>01948 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(PtrVT.getSizeInBits()/8, PtrVT);
+<a name="l01949"></a>01949 FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), FIN, PtrOff);
+<a name="l01950"></a>01950 }
+<a name="l01951"></a>01951
+<a name="l01952"></a>01952 <span class="comment">// FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6</span>
+<a name="l01953"></a>01953 <span class="comment">// is set.</span>
+<a name="l01954"></a>01954 <span class="comment">// The double arguments are stored to the VarArgsFrameIndex</span>
+<a name="l01955"></a>01955 <span class="comment">// on the stack.</span>
+<a name="l01956"></a>01956 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
+<a name="l01957"></a>01957 <span class="comment">// Get an existing live-in vreg, or add a new one.</span>
+<a name="l01958"></a>01958 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a957027d4e9d0442f3bf1a0d7db0ba253">getLiveInVirtReg</a>(FPArgRegs[FPRIndex]);
+<a name="l01959"></a>01959 <span class="keywordflow">if</span> (!VReg)
+<a name="l01960"></a>01960 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
+<a name="l01961"></a>01961
+<a name="l01962"></a>01962 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>);
+<a name="l01963"></a>01963 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l01964"></a>01964 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l01965"></a>01965 MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l01966"></a>01966 <span class="comment">// Increment the address by eight for the next argument to store</span>
+<a name="l01967"></a>01967 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(<a class="code" href="structllvm_1_1EVT.html">EVT</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>).getSizeInBits()/8,
+<a name="l01968"></a>01968 PtrVT);
+<a name="l01969"></a>01969 FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), FIN, PtrOff);
+<a name="l01970"></a>01970 }
+<a name="l01971"></a>01971 }
+<a name="l01972"></a>01972
+<a name="l01973"></a>01973 <span class="keywordflow">if</span> (!MemOps.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l01974"></a>01974 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad469508535ce2082a1ab1f0e429187b8">ISD::TokenFactor</a>, dl,
+<a name="l01975"></a>01975 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, &MemOps[0], MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l01976"></a>01976
+<a name="l01977"></a>01977 <span class="keywordflow">return</span> Chain;
+<a name="l01978"></a>01978 }
+<a name="l01979"></a>01979
+<a name="l01980"></a>01980 <span class="comment">// PPC64 passes i8, i16, and i32 values in i64 registers. Promote</span>
+<a name="l01981"></a>01981 <span class="comment">// value to MVT::i64 and then truncate to the correct register size.</span>
+<a name="l01982"></a>01982 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l01983"></a>01983 PPCTargetLowering::extendArgForPPC64(<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags, <a class="code" href="structllvm_1_1EVT.html">EVT</a> ObjectVT,
+<a name="l01984"></a>01984 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ArgVal,
+<a name="l01985"></a>01985 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl)<span class="keyword"> const </span>{
+<a name="l01986"></a>01986 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#ae3d1eab6cbe1d4d2bd95ac0844bdee8f">isSExt</a>())
+<a name="l01987"></a>01987 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aee4f13218bdbb5c5697f7e786618ecb2">ISD::AssertSext</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, ArgVal,
+<a name="l01988"></a>01988 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ab8ba6b05ad4fa7517f2e23b26f84ae1b">getValueType</a>(ObjectVT));
+<a name="l01989"></a>01989 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a0414ddd7827c97349dd4d7ffe34d0798">isZExt</a>())
+<a name="l01990"></a>01990 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110af23301e60475124fd80a2cb51f6ba863">ISD::AssertZext</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, ArgVal,
+<a name="l01991"></a>01991 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ab8ba6b05ad4fa7517f2e23b26f84ae1b">getValueType</a>(ObjectVT));
+<a name="l01992"></a>01992
+<a name="l01993"></a>01993 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae690127648393001a7d5b93dc23da7b3" title="TRUNCATE - Completely drop the high bits.">ISD::TRUNCATE</a>, dl, MVT::i32, ArgVal);
+<a name="l01994"></a>01994 }
+<a name="l01995"></a>01995
+<a name="l01996"></a>01996 <span class="comment">// Set the size that is at least reserved in caller of this function. Tail</span>
+<a name="l01997"></a>01997 <span class="comment">// call optimized functions' reserved stack space needs to be aligned so that</span>
+<a name="l01998"></a>01998 <span class="comment">// taking the difference between two stack areas will result in an aligned</span>
+<a name="l01999"></a>01999 <span class="comment">// stack.</span>
+<a name="l02000"></a>02000 <span class="keywordtype">void</span>
+<a name="l02001"></a>02001 PPCTargetLowering::setMinReservedArea(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l02002"></a>02002 <span class="keywordtype">unsigned</span> nAltivecParamsAtEnd,
+<a name="l02003"></a>02003 <span class="keywordtype">unsigned</span> MinReservedArea,
+<a name="l02004"></a>02004 <span class="keywordtype">bool</span> isPPC64)<span class="keyword"> const </span>{
+<a name="l02005"></a>02005 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l02006"></a>02006 <span class="comment">// Add the Altivec parameters at the end, if needed.</span>
+<a name="l02007"></a>02007 <span class="keywordflow">if</span> (nAltivecParamsAtEnd) {
+<a name="l02008"></a>02008 MinReservedArea = ((MinReservedArea+15)/16)*16;
+<a name="l02009"></a>02009 MinReservedArea += 16*nAltivecParamsAtEnd;
+<a name="l02010"></a>02010 }
+<a name="l02011"></a>02011 MinReservedArea =
+<a name="l02012"></a>02012 std::max(MinReservedArea,
+<a name="l02013"></a>02013 <a class="code" href="classllvm_1_1PPCFrameLowering.html#ad6cf9c804045cfe1b414dd12b18e86ca">PPCFrameLowering::getMinCallFrameSize</a>(isPPC64, <span class="keyword">true</span>));
+<a name="l02014"></a>02014 <span class="keywordtype">unsigned</span> TargetAlign
+<a name="l02015"></a>02015 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a02aa9d4cbd6ffcc70dfe1143ec0995ef">getFrameLowering</a>()->
+<a name="l02016"></a>02016 getStackAlignment();
+<a name="l02017"></a>02017 <span class="keywordtype">unsigned</span> AlignMask = TargetAlign-1;
+<a name="l02018"></a>02018 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
+<a name="l02019"></a>02019 FI-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a8e0b7625b4133471e51249e77ef84c81">setMinReservedArea</a>(MinReservedArea);
+<a name="l02020"></a>02020 }
+<a name="l02021"></a>02021
+<a name="l02022"></a>02022 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l02023"></a>02023 PPCTargetLowering::LowerFormalArguments_64SVR4(
+<a name="l02024"></a>02024 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l02025"></a>02025 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l02026"></a>02026 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a>
+<a name="l02027"></a>02027 &Ins,
+<a name="l02028"></a>02028 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l02029"></a>02029 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l02030"></a>02030 <span class="comment">// TODO: add description of PPC stack frame format, or at least some docs.</span>
+<a name="l02031"></a>02031 <span class="comment">//</span>
+<a name="l02032"></a>02032 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l02033"></a>02033 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l02034"></a>02034 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FuncInfo = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l02035"></a>02035
+<a name="l02036"></a>02036 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l02037"></a>02037 <span class="comment">// Potential tail calls could cause overwriting of argument stack slots.</span>
+<a name="l02038"></a>02038 <span class="keywordtype">bool</span> isImmutable = !(<a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ab1fb67187fc37e569cc5171cbebba873">Options</a>.<a class="code" href="classllvm_1_1TargetOptions.html#ad54fc81a4ef7ab96137a9b6e78fdf838">GuaranteedTailCallOpt</a> &&
+<a name="l02039"></a>02039 (CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a>));
+<a name="l02040"></a>02040 <span class="keywordtype">unsigned</span> PtrByteSize = 8;
+<a name="l02041"></a>02041
+<a name="l02042"></a>02042 <span class="keywordtype">unsigned</span> ArgOffset = <a class="code" href="classllvm_1_1PPCFrameLowering.html#ab90d8608756fd53ed946d0eab8ad6cb7">PPCFrameLowering::getLinkageSize</a>(<span class="keyword">true</span>, <span class="keyword">true</span>);
+<a name="l02043"></a>02043 <span class="comment">// Area that is at least reserved in caller of this function.</span>
+<a name="l02044"></a>02044 <span class="keywordtype">unsigned</span> MinReservedArea = ArgOffset;
+<a name="l02045"></a>02045
+<a name="l02046"></a>02046 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t GPR[] = {
+<a name="l02047"></a>02047 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+<a name="l02048"></a>02048 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
+<a name="l02049"></a>02049 };
+<a name="l02050"></a>02050
+<a name="l02051"></a>02051 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t *FPR = <a class="code" href="PPCISelLowering_8cpp.html#a1cbd108eaf5aca7619ff85c02489c3a1">GetFPR</a>();
+<a name="l02052"></a>02052
+<a name="l02053"></a>02053 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t VR[] = {
+<a name="l02054"></a>02054 <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">PPC::V2</a>, PPC::V3, <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca72ebe5e08d40fbab96c046e017576a32">PPC::V4</a>, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
+<a name="l02055"></a>02055 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
+<a name="l02056"></a>02056 };
+<a name="l02057"></a>02057
+<a name="l02058"></a>02058 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> Num_GPR_Regs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(GPR);
+<a name="l02059"></a>02059 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> Num_FPR_Regs = 13;
+<a name="l02060"></a>02060 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> Num_VR_Regs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(VR);
+<a name="l02061"></a>02061
+<a name="l02062"></a>02062 <span class="keywordtype">unsigned</span> GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
+<a name="l02063"></a>02063
+<a name="l02064"></a>02064 <span class="comment">// Add DAG nodes to load the arguments or copy them out of registers. On</span>
+<a name="l02065"></a>02065 <span class="comment">// entry to a function on PPC, the arguments start after the linkage area,</span>
+<a name="l02066"></a>02066 <span class="comment">// although the first ones are often in registers.</span>
+<a name="l02067"></a>02067
+<a name="l02068"></a>02068 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> MemOps;
+<a name="l02069"></a>02069 <span class="keywordtype">unsigned</span> nAltivecParamsAtEnd = 0;
+<a name="l02070"></a>02070 <a class="code" href="classllvm_1_1ilist__iterator.html">Function::const_arg_iterator</a> FuncArg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ad784a6594990530bffb2018aeeed56f3">getFunction</a>()-><a class="code" href="classllvm_1_1Function.html#a8bf193a781a92cae52d7f9216d0824f8">arg_begin</a>();
+<a name="l02071"></a>02071 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> ArgNo = 0, e = Ins.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); ArgNo != e; ++ArgNo, ++FuncArg) {
+<a name="l02072"></a>02072 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ArgVal;
+<a name="l02073"></a>02073 <span class="keywordtype">bool</span> needsLoad = <span class="keyword">false</span>;
+<a name="l02074"></a>02074 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ObjectVT = Ins[ArgNo].VT;
+<a name="l02075"></a>02075 <span class="keywordtype">unsigned</span> ObjSize = ObjectVT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8;
+<a name="l02076"></a>02076 <span class="keywordtype">unsigned</span> ArgSize = ObjSize;
+<a name="l02077"></a>02077 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags = Ins[ArgNo].Flags;
+<a name="l02078"></a>02078
+<a name="l02079"></a>02079 <span class="keywordtype">unsigned</span> CurArgOffset = ArgOffset;
+<a name="l02080"></a>02080
+<a name="l02081"></a>02081 <span class="comment">// Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.</span>
+<a name="l02082"></a>02082 <span class="keywordflow">if</span> (ObjectVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a> || ObjectVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a> ||
+<a name="l02083"></a>02083 ObjectVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a> || ObjectVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>) {
+<a name="l02084"></a>02084 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l02085"></a>02085 MinReservedArea = ((MinReservedArea+15)/16)*16;
+<a name="l02086"></a>02086 MinReservedArea += <a class="code" href="PPCISelLowering_8cpp.html#aacd7e508c9e6dd17afc738da27b87bc2">CalculateStackSlotSize</a>(ObjectVT,
+<a name="l02087"></a>02087 Flags,
+<a name="l02088"></a>02088 PtrByteSize);
+<a name="l02089"></a>02089 } <span class="keywordflow">else</span>
+<a name="l02090"></a>02090 nAltivecParamsAtEnd++;
+<a name="l02091"></a>02091 } <span class="keywordflow">else</span>
+<a name="l02092"></a>02092 <span class="comment">// Calculate min reserved area.</span>
+<a name="l02093"></a>02093 MinReservedArea += <a class="code" href="PPCISelLowering_8cpp.html#aacd7e508c9e6dd17afc738da27b87bc2">CalculateStackSlotSize</a>(Ins[ArgNo].VT,
+<a name="l02094"></a>02094 Flags,
+<a name="l02095"></a>02095 PtrByteSize);
+<a name="l02096"></a>02096
+<a name="l02097"></a>02097 <span class="comment">// FIXME the codegen can be much improved in some cases.</span>
+<a name="l02098"></a>02098 <span class="comment">// We do not have to keep everything in memory.</span>
+<a name="l02099"></a>02099 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a34ee642bf0fb623f775e04e0e60d9b26">isByVal</a>()) {
+<a name="l02100"></a>02100 <span class="comment">// ObjSize is the true size, ArgSize rounded up to multiple of registers.</span>
+<a name="l02101"></a>02101 ObjSize = Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a20485215f1c6f05a5c5209725c93de2f">getByValSize</a>();
+<a name="l02102"></a>02102 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
+<a name="l02103"></a>02103 <span class="comment">// Empty aggregate parameters do not take up registers. Examples:</span>
+<a name="l02104"></a>02104 <span class="comment">// struct { } a;</span>
+<a name="l02105"></a>02105 <span class="comment">// union { } b;</span>
+<a name="l02106"></a>02106 <span class="comment">// int c[0];</span>
+<a name="l02107"></a>02107 <span class="comment">// etc. However, we have to provide a place-holder in InVals, so</span>
+<a name="l02108"></a>02108 <span class="comment">// pretend we have an 8-byte item at the current address for that</span>
+<a name="l02109"></a>02109 <span class="comment">// purpose.</span>
+<a name="l02110"></a>02110 <span class="keywordflow">if</span> (!ObjSize) {
+<a name="l02111"></a>02111 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(PtrByteSize, ArgOffset, <span class="keyword">true</span>);
+<a name="l02112"></a>02112 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l02113"></a>02113 InVals.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(FIN);
+<a name="l02114"></a>02114 <span class="keywordflow">continue</span>;
+<a name="l02115"></a>02115 }
+<a name="l02116"></a>02116 <span class="comment">// All aggregates smaller than 8 bytes must be passed right-justified.</span>
+<a name="l02117"></a>02117 <span class="keywordflow">if</span> (ObjSize < PtrByteSize)
+<a name="l02118"></a>02118 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
+<a name="l02119"></a>02119 <span class="comment">// The value of the object is its address.</span>
+<a name="l02120"></a>02120 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(ObjSize, CurArgOffset, <span class="keyword">true</span>);
+<a name="l02121"></a>02121 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l02122"></a>02122 InVals.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(FIN);
+<a name="l02123"></a>02123
+<a name="l02124"></a>02124 <span class="keywordflow">if</span> (ObjSize < 8) {
+<a name="l02125"></a>02125 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02126"></a>02126 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::G8RCRegClass);
+<a name="l02127"></a>02127 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, PtrVT);
+<a name="l02128"></a>02128 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1SPII.html#add994c36633ba2d8f6a1366b775e88a6a36b3dd3b84fde3f8494a9b18af131856">Store</a>;
+<a name="l02129"></a>02129
+<a name="l02130"></a>02130 <span class="keywordflow">if</span> (ObjSize==1 || ObjSize==2 || ObjSize==4) {
+<a name="l02131"></a>02131 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ObjType = (ObjSize == 1 ? MVT::i8 :
+<a name="l02132"></a>02132 (ObjSize == 2 ? <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a> : MVT::i32));
+<a name="l02133"></a>02133 Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4046a9f92b29865c08e6df8815e1402b">getTruncStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l02134"></a>02134 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(FuncArg, CurArgOffset),
+<a name="l02135"></a>02135 ObjType, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02136"></a>02136 } <span class="keywordflow">else</span> {
+<a name="l02137"></a>02137 <span class="comment">// For sizes that don't fit a truncating store (3, 5, 6, 7),</span>
+<a name="l02138"></a>02138 <span class="comment">// store the whole register as-is to the parameter save area</span>
+<a name="l02139"></a>02139 <span class="comment">// slot. The address of the parameter was already calculated</span>
+<a name="l02140"></a>02140 <span class="comment">// above (InVals.push_back(FIN)) to be the right-justified</span>
+<a name="l02141"></a>02141 <span class="comment">// offset within the slot. For this store, we need a new</span>
+<a name="l02142"></a>02142 <span class="comment">// frame index that points at the beginning of the slot.</span>
+<a name="l02143"></a>02143 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(PtrByteSize, ArgOffset, <span class="keyword">true</span>);
+<a name="l02144"></a>02144 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l02145"></a>02145 Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l02146"></a>02146 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(FuncArg, ArgOffset),
+<a name="l02147"></a>02147 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02148"></a>02148 }
+<a name="l02149"></a>02149
+<a name="l02150"></a>02150 MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l02151"></a>02151 ++GPR_idx;
+<a name="l02152"></a>02152 }
+<a name="l02153"></a>02153 <span class="comment">// Whether we copied from a register or not, advance the offset</span>
+<a name="l02154"></a>02154 <span class="comment">// into the parameter save area by a full doubleword.</span>
+<a name="l02155"></a>02155 ArgOffset += PtrByteSize;
+<a name="l02156"></a>02156 <span class="keywordflow">continue</span>;
+<a name="l02157"></a>02157 }
+<a name="l02158"></a>02158
+<a name="l02159"></a>02159 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j = 0; j < ArgSize; j += PtrByteSize) {
+<a name="l02160"></a>02160 <span class="comment">// Store whatever pieces of the object are in registers</span>
+<a name="l02161"></a>02161 <span class="comment">// to memory. ArgOffset will be the address of the beginning</span>
+<a name="l02162"></a>02162 <span class="comment">// of the object.</span>
+<a name="l02163"></a>02163 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02164"></a>02164 <span class="keywordtype">unsigned</span> VReg;
+<a name="l02165"></a>02165 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::G8RCRegClass);
+<a name="l02166"></a>02166 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(PtrByteSize, ArgOffset, <span class="keyword">true</span>);
+<a name="l02167"></a>02167 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l02168"></a>02168 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, PtrVT);
+<a name="l02169"></a>02169 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l02170"></a>02170 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(FuncArg, ArgOffset),
+<a name="l02171"></a>02171 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02172"></a>02172 MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l02173"></a>02173 ++GPR_idx;
+<a name="l02174"></a>02174 ArgOffset += PtrByteSize;
+<a name="l02175"></a>02175 } <span class="keywordflow">else</span> {
+<a name="l02176"></a>02176 ArgOffset += ArgSize - j;
+<a name="l02177"></a>02177 <span class="keywordflow">break</span>;
+<a name="l02178"></a>02178 }
+<a name="l02179"></a>02179 }
+<a name="l02180"></a>02180 <span class="keywordflow">continue</span>;
+<a name="l02181"></a>02181 }
+<a name="l02182"></a>02182
+<a name="l02183"></a>02183 <span class="keywordflow">switch</span> (ObjectVT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l02184"></a>02184 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unhandled argument type!"</span>);
+<a name="l02185"></a>02185 <span class="keywordflow">case</span> MVT::i32:
+<a name="l02186"></a>02186 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>:
+<a name="l02187"></a>02187 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02188"></a>02188 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::G8RCRegClass);
+<a name="l02189"></a>02189 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l02190"></a>02190
+<a name="l02191"></a>02191 <span class="keywordflow">if</span> (ObjectVT == MVT::i32)
+<a name="l02192"></a>02192 <span class="comment">// PPC64 passes i8, i16, and i32 values in i64 registers. Promote</span>
+<a name="l02193"></a>02193 <span class="comment">// value to MVT::i64 and then truncate to the correct register size.</span>
+<a name="l02194"></a>02194 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
+<a name="l02195"></a>02195
+<a name="l02196"></a>02196 ++GPR_idx;
+<a name="l02197"></a>02197 } <span class="keywordflow">else</span> {
+<a name="l02198"></a>02198 needsLoad = <span class="keyword">true</span>;
+<a name="l02199"></a>02199 ArgSize = PtrByteSize;
+<a name="l02200"></a>02200 }
+<a name="l02201"></a>02201 ArgOffset += 8;
+<a name="l02202"></a>02202 <span class="keywordflow">break</span>;
+<a name="l02203"></a>02203
+<a name="l02204"></a>02204 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>:
+<a name="l02205"></a>02205 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>:
+<a name="l02206"></a>02206 <span class="comment">// Every 8 bytes of argument space consumes one of the GPRs available for</span>
+<a name="l02207"></a>02207 <span class="comment">// argument passing.</span>
+<a name="l02208"></a>02208 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02209"></a>02209 ++GPR_idx;
+<a name="l02210"></a>02210 }
+<a name="l02211"></a>02211 <span class="keywordflow">if</span> (FPR_idx != Num_FPR_Regs) {
+<a name="l02212"></a>02212 <span class="keywordtype">unsigned</span> VReg;
+<a name="l02213"></a>02213
+<a name="l02214"></a>02214 <span class="keywordflow">if</span> (ObjectVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>)
+<a name="l02215"></a>02215 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(FPR[FPR_idx], &PPC::F4RCRegClass);
+<a name="l02216"></a>02216 <span class="keywordflow">else</span>
+<a name="l02217"></a>02217 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(FPR[FPR_idx], &PPC::F8RCRegClass);
+<a name="l02218"></a>02218
+<a name="l02219"></a>02219 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, ObjectVT);
+<a name="l02220"></a>02220 ++FPR_idx;
+<a name="l02221"></a>02221 } <span class="keywordflow">else</span> {
+<a name="l02222"></a>02222 needsLoad = <span class="keyword">true</span>;
+<a name="l02223"></a>02223 ArgSize = PtrByteSize;
+<a name="l02224"></a>02224 }
+<a name="l02225"></a>02225
+<a name="l02226"></a>02226 ArgOffset += 8;
+<a name="l02227"></a>02227 <span class="keywordflow">break</span>;
+<a name="l02228"></a>02228 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l02229"></a>02229 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>:
+<a name="l02230"></a>02230 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>:
+<a name="l02231"></a>02231 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>:
+<a name="l02232"></a>02232 <span class="comment">// Note that vector arguments in registers don't reserve stack space,</span>
+<a name="l02233"></a>02233 <span class="comment">// except in varargs functions.</span>
+<a name="l02234"></a>02234 <span class="keywordflow">if</span> (VR_idx != Num_VR_Regs) {
+<a name="l02235"></a>02235 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(VR[VR_idx], &PPC::VRRCRegClass);
+<a name="l02236"></a>02236 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, ObjectVT);
+<a name="l02237"></a>02237 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l02238"></a>02238 <span class="keywordflow">while</span> ((ArgOffset % 16) != 0) {
+<a name="l02239"></a>02239 ArgOffset += PtrByteSize;
+<a name="l02240"></a>02240 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs)
+<a name="l02241"></a>02241 GPR_idx++;
+<a name="l02242"></a>02242 }
+<a name="l02243"></a>02243 ArgOffset += 16;
+<a name="l02244"></a>02244 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); <span class="comment">// FIXME correct for ppc64?</span>
+<a name="l02245"></a>02245 }
+<a name="l02246"></a>02246 ++VR_idx;
+<a name="l02247"></a>02247 } <span class="keywordflow">else</span> {
+<a name="l02248"></a>02248 <span class="comment">// Vectors are aligned.</span>
+<a name="l02249"></a>02249 ArgOffset = ((ArgOffset+15)/16)*16;
+<a name="l02250"></a>02250 CurArgOffset = ArgOffset;
+<a name="l02251"></a>02251 ArgOffset += 16;
+<a name="l02252"></a>02252 needsLoad = <span class="keyword">true</span>;
+<a name="l02253"></a>02253 }
+<a name="l02254"></a>02254 <span class="keywordflow">break</span>;
+<a name="l02255"></a>02255 }
+<a name="l02256"></a>02256
+<a name="l02257"></a>02257 <span class="comment">// We need to load the argument to a virtual register if we determined</span>
+<a name="l02258"></a>02258 <span class="comment">// above that we ran out of physical registers of the appropriate type.</span>
+<a name="l02259"></a>02259 <span class="keywordflow">if</span> (needsLoad) {
+<a name="l02260"></a>02260 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(ObjSize,
+<a name="l02261"></a>02261 CurArgOffset + (ArgSize - ObjSize),
+<a name="l02262"></a>02262 isImmutable);
+<a name="l02263"></a>02263 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l02264"></a>02264 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(ObjectVT, dl, Chain, FIN, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l02265"></a>02265 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02266"></a>02266 }
+<a name="l02267"></a>02267
+<a name="l02268"></a>02268 InVals.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(ArgVal);
+<a name="l02269"></a>02269 }
+<a name="l02270"></a>02270
+<a name="l02271"></a>02271 <span class="comment">// Set the size that is at least reserved in caller of this function. Tail</span>
+<a name="l02272"></a>02272 <span class="comment">// call optimized functions' reserved stack space needs to be aligned so that</span>
+<a name="l02273"></a>02273 <span class="comment">// taking the difference between two stack areas will result in an aligned</span>
+<a name="l02274"></a>02274 <span class="comment">// stack.</span>
+<a name="l02275"></a>02275 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, <span class="keyword">true</span>);
+<a name="l02276"></a>02276
+<a name="l02277"></a>02277 <span class="comment">// If the function takes variable number of arguments, make a frame index for</span>
+<a name="l02278"></a>02278 <span class="comment">// the start of the first vararg value... for expansion of llvm.va_start.</span>
+<a name="l02279"></a>02279 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l02280"></a>02280 <span class="keywordtype">int</span> Depth = ArgOffset;
+<a name="l02281"></a>02281
+<a name="l02282"></a>02282 FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#ada6f0ce61d2e0bfaef869dffc2d643ed">setVarArgsFrameIndex</a>(
+<a name="l02283"></a>02283 MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(PtrByteSize, Depth, <span class="keyword">true</span>));
+<a name="l02284"></a>02284 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a0a78984133f621514980f087442645b4">getVarArgsFrameIndex</a>(), PtrVT);
+<a name="l02285"></a>02285
+<a name="l02286"></a>02286 <span class="comment">// If this function is vararg, store any remaining integer argument regs</span>
+<a name="l02287"></a>02287 <span class="comment">// to their spots on the stack so that they may be loaded by deferencing the</span>
+<a name="l02288"></a>02288 <span class="comment">// result of va_next.</span>
+<a name="l02289"></a>02289 <span class="keywordflow">for</span> (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
+<a name="l02290"></a>02290 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::G8RCRegClass);
+<a name="l02291"></a>02291 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, PtrVT);
+<a name="l02292"></a>02292 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l02293"></a>02293 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02294"></a>02294 MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l02295"></a>02295 <span class="comment">// Increment the address by four for the next argument to store</span>
+<a name="l02296"></a>02296 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(PtrByteSize, PtrVT);
+<a name="l02297"></a>02297 FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), FIN, PtrOff);
+<a name="l02298"></a>02298 }
+<a name="l02299"></a>02299 }
+<a name="l02300"></a>02300
+<a name="l02301"></a>02301 <span class="keywordflow">if</span> (!MemOps.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l02302"></a>02302 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad469508535ce2082a1ab1f0e429187b8">ISD::TokenFactor</a>, dl,
+<a name="l02303"></a>02303 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, &MemOps[0], MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l02304"></a>02304
+<a name="l02305"></a>02305 <span class="keywordflow">return</span> Chain;
+<a name="l02306"></a>02306 }
+<a name="l02307"></a>02307
+<a name="l02308"></a>02308 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l02309"></a>02309 PPCTargetLowering::LowerFormalArguments_Darwin(
+<a name="l02310"></a>02310 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l02311"></a>02311 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l02312"></a>02312 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a>
+<a name="l02313"></a>02313 &Ins,
+<a name="l02314"></a>02314 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l02315"></a>02315 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l02316"></a>02316 <span class="comment">// TODO: add description of PPC stack frame format, or at least some docs.</span>
+<a name="l02317"></a>02317 <span class="comment">//</span>
+<a name="l02318"></a>02318 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l02319"></a>02319 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l02320"></a>02320 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FuncInfo = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l02321"></a>02321
+<a name="l02322"></a>02322 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l02323"></a>02323 <span class="keywordtype">bool</span> isPPC64 = PtrVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>;
+<a name="l02324"></a>02324 <span class="comment">// Potential tail calls could cause overwriting of argument stack slots.</span>
+<a name="l02325"></a>02325 <span class="keywordtype">bool</span> isImmutable = !(<a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ab1fb67187fc37e569cc5171cbebba873">Options</a>.<a class="code" href="classllvm_1_1TargetOptions.html#ad54fc81a4ef7ab96137a9b6e78fdf838">GuaranteedTailCallOpt</a> &&
+<a name="l02326"></a>02326 (CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a>));
+<a name="l02327"></a>02327 <span class="keywordtype">unsigned</span> PtrByteSize = isPPC64 ? 8 : 4;
+<a name="l02328"></a>02328
+<a name="l02329"></a>02329 <span class="keywordtype">unsigned</span> ArgOffset = <a class="code" href="classllvm_1_1PPCFrameLowering.html#ab90d8608756fd53ed946d0eab8ad6cb7">PPCFrameLowering::getLinkageSize</a>(isPPC64, <span class="keyword">true</span>);
+<a name="l02330"></a>02330 <span class="comment">// Area that is at least reserved in caller of this function.</span>
+<a name="l02331"></a>02331 <span class="keywordtype">unsigned</span> MinReservedArea = ArgOffset;
+<a name="l02332"></a>02332
+<a name="l02333"></a>02333 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t GPR_32[] = { <span class="comment">// 32-bit registers.</span>
+<a name="l02334"></a>02334 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+<a name="l02335"></a>02335 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+<a name="l02336"></a>02336 };
+<a name="l02337"></a>02337 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t GPR_64[] = { <span class="comment">// 64-bit registers.</span>
+<a name="l02338"></a>02338 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+<a name="l02339"></a>02339 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
+<a name="l02340"></a>02340 };
+<a name="l02341"></a>02341
+<a name="l02342"></a>02342 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t *FPR = <a class="code" href="PPCISelLowering_8cpp.html#a1cbd108eaf5aca7619ff85c02489c3a1">GetFPR</a>();
+<a name="l02343"></a>02343
+<a name="l02344"></a>02344 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t VR[] = {
+<a name="l02345"></a>02345 <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">PPC::V2</a>, PPC::V3, <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca72ebe5e08d40fbab96c046e017576a32">PPC::V4</a>, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
+<a name="l02346"></a>02346 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
+<a name="l02347"></a>02347 };
+<a name="l02348"></a>02348
+<a name="l02349"></a>02349 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> Num_GPR_Regs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(GPR_32);
+<a name="l02350"></a>02350 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> Num_FPR_Regs = 13;
+<a name="l02351"></a>02351 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> Num_VR_Regs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>( VR);
+<a name="l02352"></a>02352
+<a name="l02353"></a>02353 <span class="keywordtype">unsigned</span> GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
+<a name="l02354"></a>02354
+<a name="l02355"></a>02355 <span class="keyword">const</span> uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
+<a name="l02356"></a>02356
+<a name="l02357"></a>02357 <span class="comment">// In 32-bit non-varargs functions, the stack space for vectors is after the</span>
+<a name="l02358"></a>02358 <span class="comment">// stack space for non-vectors. We do not use this space unless we have</span>
+<a name="l02359"></a>02359 <span class="comment">// too many vectors to fit in registers, something that only occurs in</span>
+<a name="l02360"></a>02360 <span class="comment">// constructed examples:), but we have to walk the arglist to figure</span>
+<a name="l02361"></a>02361 <span class="comment">// that out...for the pathological case, compute VecArgOffset as the</span>
+<a name="l02362"></a>02362 <span class="comment">// start of the vector parameter area. Computing VecArgOffset is the</span>
+<a name="l02363"></a>02363 <span class="comment">// entire point of the following loop.</span>
+<a name="l02364"></a>02364 <span class="keywordtype">unsigned</span> VecArgOffset = ArgOffset;
+<a name="l02365"></a>02365 <span class="keywordflow">if</span> (!isVarArg && !isPPC64) {
+<a name="l02366"></a>02366 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> ArgNo = 0, e = Ins.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); ArgNo != e;
+<a name="l02367"></a>02367 ++ArgNo) {
+<a name="l02368"></a>02368 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ObjectVT = Ins[ArgNo].VT;
+<a name="l02369"></a>02369 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags = Ins[ArgNo].Flags;
+<a name="l02370"></a>02370
+<a name="l02371"></a>02371 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a34ee642bf0fb623f775e04e0e60d9b26">isByVal</a>()) {
+<a name="l02372"></a>02372 <span class="comment">// ObjSize is the true size, ArgSize rounded up to multiple of regs.</span>
+<a name="l02373"></a>02373 <span class="keywordtype">unsigned</span> ObjSize = Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a20485215f1c6f05a5c5209725c93de2f">getByValSize</a>();
+<a name="l02374"></a>02374 <span class="keywordtype">unsigned</span> ArgSize =
+<a name="l02375"></a>02375 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
+<a name="l02376"></a>02376 VecArgOffset += ArgSize;
+<a name="l02377"></a>02377 <span class="keywordflow">continue</span>;
+<a name="l02378"></a>02378 }
+<a name="l02379"></a>02379
+<a name="l02380"></a>02380 <span class="keywordflow">switch</span>(ObjectVT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l02381"></a>02381 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unhandled argument type!"</span>);
+<a name="l02382"></a>02382 <span class="keywordflow">case</span> MVT::i32:
+<a name="l02383"></a>02383 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>:
+<a name="l02384"></a>02384 VecArgOffset += 4;
+<a name="l02385"></a>02385 <span class="keywordflow">break</span>;
+<a name="l02386"></a>02386 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>: <span class="comment">// PPC64</span>
+<a name="l02387"></a>02387 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>:
+<a name="l02388"></a>02388 <span class="comment">// FIXME: We are guaranteed to be !isPPC64 at this point.</span>
+<a name="l02389"></a>02389 <span class="comment">// Does MVT::i64 apply?</span>
+<a name="l02390"></a>02390 VecArgOffset += 8;
+<a name="l02391"></a>02391 <span class="keywordflow">break</span>;
+<a name="l02392"></a>02392 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l02393"></a>02393 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>:
+<a name="l02394"></a>02394 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>:
+<a name="l02395"></a>02395 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>:
+<a name="l02396"></a>02396 <span class="comment">// Nothing to do, we're only looking at Nonvector args here.</span>
+<a name="l02397"></a>02397 <span class="keywordflow">break</span>;
+<a name="l02398"></a>02398 }
+<a name="l02399"></a>02399 }
+<a name="l02400"></a>02400 }
+<a name="l02401"></a>02401 <span class="comment">// We've found where the vector parameter area in memory is. Skip the</span>
+<a name="l02402"></a>02402 <span class="comment">// first 12 parameters; these don't use that memory.</span>
+<a name="l02403"></a>02403 VecArgOffset = ((VecArgOffset+15)/16)*16;
+<a name="l02404"></a>02404 VecArgOffset += 12*16;
+<a name="l02405"></a>02405
+<a name="l02406"></a>02406 <span class="comment">// Add DAG nodes to load the arguments or copy them out of registers. On</span>
+<a name="l02407"></a>02407 <span class="comment">// entry to a function on PPC, the arguments start after the linkage area,</span>
+<a name="l02408"></a>02408 <span class="comment">// although the first ones are often in registers.</span>
+<a name="l02409"></a>02409
+<a name="l02410"></a>02410 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> MemOps;
+<a name="l02411"></a>02411 <span class="keywordtype">unsigned</span> nAltivecParamsAtEnd = 0;
+<a name="l02412"></a>02412 <a class="code" href="classllvm_1_1ilist__iterator.html">Function::const_arg_iterator</a> FuncArg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ad784a6594990530bffb2018aeeed56f3">getFunction</a>()-><a class="code" href="classllvm_1_1Function.html#a8bf193a781a92cae52d7f9216d0824f8">arg_begin</a>();
+<a name="l02413"></a>02413 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> ArgNo = 0, e = Ins.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); ArgNo != e; ++ArgNo, ++FuncArg) {
+<a name="l02414"></a>02414 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ArgVal;
+<a name="l02415"></a>02415 <span class="keywordtype">bool</span> needsLoad = <span class="keyword">false</span>;
+<a name="l02416"></a>02416 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ObjectVT = Ins[ArgNo].VT;
+<a name="l02417"></a>02417 <span class="keywordtype">unsigned</span> ObjSize = ObjectVT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8;
+<a name="l02418"></a>02418 <span class="keywordtype">unsigned</span> ArgSize = ObjSize;
+<a name="l02419"></a>02419 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags = Ins[ArgNo].Flags;
+<a name="l02420"></a>02420
+<a name="l02421"></a>02421 <span class="keywordtype">unsigned</span> CurArgOffset = ArgOffset;
+<a name="l02422"></a>02422
+<a name="l02423"></a>02423 <span class="comment">// Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.</span>
+<a name="l02424"></a>02424 <span class="keywordflow">if</span> (ObjectVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a> || ObjectVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a> ||
+<a name="l02425"></a>02425 ObjectVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a> || ObjectVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>) {
+<a name="l02426"></a>02426 <span class="keywordflow">if</span> (isVarArg || isPPC64) {
+<a name="l02427"></a>02427 MinReservedArea = ((MinReservedArea+15)/16)*16;
+<a name="l02428"></a>02428 MinReservedArea += <a class="code" href="PPCISelLowering_8cpp.html#aacd7e508c9e6dd17afc738da27b87bc2">CalculateStackSlotSize</a>(ObjectVT,
+<a name="l02429"></a>02429 Flags,
+<a name="l02430"></a>02430 PtrByteSize);
+<a name="l02431"></a>02431 } <span class="keywordflow">else</span> nAltivecParamsAtEnd++;
+<a name="l02432"></a>02432 } <span class="keywordflow">else</span>
+<a name="l02433"></a>02433 <span class="comment">// Calculate min reserved area.</span>
+<a name="l02434"></a>02434 MinReservedArea += <a class="code" href="PPCISelLowering_8cpp.html#aacd7e508c9e6dd17afc738da27b87bc2">CalculateStackSlotSize</a>(Ins[ArgNo].VT,
+<a name="l02435"></a>02435 Flags,
+<a name="l02436"></a>02436 PtrByteSize);
+<a name="l02437"></a>02437
+<a name="l02438"></a>02438 <span class="comment">// FIXME the codegen can be much improved in some cases.</span>
+<a name="l02439"></a>02439 <span class="comment">// We do not have to keep everything in memory.</span>
+<a name="l02440"></a>02440 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a34ee642bf0fb623f775e04e0e60d9b26">isByVal</a>()) {
+<a name="l02441"></a>02441 <span class="comment">// ObjSize is the true size, ArgSize rounded up to multiple of registers.</span>
+<a name="l02442"></a>02442 ObjSize = Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a20485215f1c6f05a5c5209725c93de2f">getByValSize</a>();
+<a name="l02443"></a>02443 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
+<a name="l02444"></a>02444 <span class="comment">// Objects of size 1 and 2 are right justified, everything else is</span>
+<a name="l02445"></a>02445 <span class="comment">// left justified. This means the memory address is adjusted forwards.</span>
+<a name="l02446"></a>02446 <span class="keywordflow">if</span> (ObjSize==1 || ObjSize==2) {
+<a name="l02447"></a>02447 CurArgOffset = CurArgOffset + (4 - ObjSize);
+<a name="l02448"></a>02448 }
+<a name="l02449"></a>02449 <span class="comment">// The value of the object is its address.</span>
+<a name="l02450"></a>02450 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(ObjSize, CurArgOffset, <span class="keyword">true</span>);
+<a name="l02451"></a>02451 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l02452"></a>02452 InVals.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(FIN);
+<a name="l02453"></a>02453 <span class="keywordflow">if</span> (ObjSize==1 || ObjSize==2) {
+<a name="l02454"></a>02454 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02455"></a>02455 <span class="keywordtype">unsigned</span> VReg;
+<a name="l02456"></a>02456 <span class="keywordflow">if</span> (isPPC64)
+<a name="l02457"></a>02457 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::G8RCRegClass);
+<a name="l02458"></a>02458 <span class="keywordflow">else</span>
+<a name="l02459"></a>02459 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::GPRCRegClass);
+<a name="l02460"></a>02460 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, PtrVT);
+<a name="l02461"></a>02461 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ObjType = ObjSize == 1 ? MVT::i8 : <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>;
+<a name="l02462"></a>02462 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a4046a9f92b29865c08e6df8815e1402b">getTruncStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l02463"></a>02463 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(FuncArg,
+<a name="l02464"></a>02464 CurArgOffset),
+<a name="l02465"></a>02465 ObjType, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02466"></a>02466 MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l02467"></a>02467 ++GPR_idx;
+<a name="l02468"></a>02468 }
+<a name="l02469"></a>02469
+<a name="l02470"></a>02470 ArgOffset += PtrByteSize;
+<a name="l02471"></a>02471
+<a name="l02472"></a>02472 <span class="keywordflow">continue</span>;
+<a name="l02473"></a>02473 }
+<a name="l02474"></a>02474 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j = 0; j < ArgSize; j += PtrByteSize) {
+<a name="l02475"></a>02475 <span class="comment">// Store whatever pieces of the object are in registers</span>
+<a name="l02476"></a>02476 <span class="comment">// to memory. ArgOffset will be the address of the beginning</span>
+<a name="l02477"></a>02477 <span class="comment">// of the object.</span>
+<a name="l02478"></a>02478 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02479"></a>02479 <span class="keywordtype">unsigned</span> VReg;
+<a name="l02480"></a>02480 <span class="keywordflow">if</span> (isPPC64)
+<a name="l02481"></a>02481 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::G8RCRegClass);
+<a name="l02482"></a>02482 <span class="keywordflow">else</span>
+<a name="l02483"></a>02483 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::GPRCRegClass);
+<a name="l02484"></a>02484 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(PtrByteSize, ArgOffset, <span class="keyword">true</span>);
+<a name="l02485"></a>02485 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l02486"></a>02486 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, PtrVT);
+<a name="l02487"></a>02487 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l02488"></a>02488 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(FuncArg, ArgOffset),
+<a name="l02489"></a>02489 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02490"></a>02490 MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l02491"></a>02491 ++GPR_idx;
+<a name="l02492"></a>02492 ArgOffset += PtrByteSize;
+<a name="l02493"></a>02493 } <span class="keywordflow">else</span> {
+<a name="l02494"></a>02494 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
+<a name="l02495"></a>02495 <span class="keywordflow">break</span>;
+<a name="l02496"></a>02496 }
+<a name="l02497"></a>02497 }
+<a name="l02498"></a>02498 <span class="keywordflow">continue</span>;
+<a name="l02499"></a>02499 }
+<a name="l02500"></a>02500
+<a name="l02501"></a>02501 <span class="keywordflow">switch</span> (ObjectVT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l02502"></a>02502 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unhandled argument type!"</span>);
+<a name="l02503"></a>02503 <span class="keywordflow">case</span> MVT::i32:
+<a name="l02504"></a>02504 <span class="keywordflow">if</span> (!isPPC64) {
+<a name="l02505"></a>02505 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02506"></a>02506 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::GPRCRegClass);
+<a name="l02507"></a>02507 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, MVT::i32);
+<a name="l02508"></a>02508 ++GPR_idx;
+<a name="l02509"></a>02509 } <span class="keywordflow">else</span> {
+<a name="l02510"></a>02510 needsLoad = <span class="keyword">true</span>;
+<a name="l02511"></a>02511 ArgSize = PtrByteSize;
+<a name="l02512"></a>02512 }
+<a name="l02513"></a>02513 <span class="comment">// All int arguments reserve stack space in the Darwin ABI.</span>
+<a name="l02514"></a>02514 ArgOffset += PtrByteSize;
+<a name="l02515"></a>02515 <span class="keywordflow">break</span>;
+<a name="l02516"></a>02516 }
+<a name="l02517"></a>02517 <span class="comment">// FALLTHROUGH</span>
+<a name="l02518"></a>02518 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>: <span class="comment">// PPC64</span>
+<a name="l02519"></a>02519 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02520"></a>02520 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::G8RCRegClass);
+<a name="l02521"></a>02521 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l02522"></a>02522
+<a name="l02523"></a>02523 <span class="keywordflow">if</span> (ObjectVT == MVT::i32)
+<a name="l02524"></a>02524 <span class="comment">// PPC64 passes i8, i16, and i32 values in i64 registers. Promote</span>
+<a name="l02525"></a>02525 <span class="comment">// value to MVT::i64 and then truncate to the correct register size.</span>
+<a name="l02526"></a>02526 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
+<a name="l02527"></a>02527
+<a name="l02528"></a>02528 ++GPR_idx;
+<a name="l02529"></a>02529 } <span class="keywordflow">else</span> {
+<a name="l02530"></a>02530 needsLoad = <span class="keyword">true</span>;
+<a name="l02531"></a>02531 ArgSize = PtrByteSize;
+<a name="l02532"></a>02532 }
+<a name="l02533"></a>02533 <span class="comment">// All int arguments reserve stack space in the Darwin ABI.</span>
+<a name="l02534"></a>02534 ArgOffset += 8;
+<a name="l02535"></a>02535 <span class="keywordflow">break</span>;
+<a name="l02536"></a>02536
+<a name="l02537"></a>02537 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>:
+<a name="l02538"></a>02538 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>:
+<a name="l02539"></a>02539 <span class="comment">// Every 4 bytes of argument space consumes one of the GPRs available for</span>
+<a name="l02540"></a>02540 <span class="comment">// argument passing.</span>
+<a name="l02541"></a>02541 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs) {
+<a name="l02542"></a>02542 ++GPR_idx;
+<a name="l02543"></a>02543 <span class="keywordflow">if</span> (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
+<a name="l02544"></a>02544 ++GPR_idx;
+<a name="l02545"></a>02545 }
+<a name="l02546"></a>02546 <span class="keywordflow">if</span> (FPR_idx != Num_FPR_Regs) {
+<a name="l02547"></a>02547 <span class="keywordtype">unsigned</span> VReg;
+<a name="l02548"></a>02548
+<a name="l02549"></a>02549 <span class="keywordflow">if</span> (ObjectVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>)
+<a name="l02550"></a>02550 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(FPR[FPR_idx], &PPC::F4RCRegClass);
+<a name="l02551"></a>02551 <span class="keywordflow">else</span>
+<a name="l02552"></a>02552 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(FPR[FPR_idx], &PPC::F8RCRegClass);
+<a name="l02553"></a>02553
+<a name="l02554"></a>02554 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, ObjectVT);
+<a name="l02555"></a>02555 ++FPR_idx;
+<a name="l02556"></a>02556 } <span class="keywordflow">else</span> {
+<a name="l02557"></a>02557 needsLoad = <span class="keyword">true</span>;
+<a name="l02558"></a>02558 }
+<a name="l02559"></a>02559
+<a name="l02560"></a>02560 <span class="comment">// All FP arguments reserve stack space in the Darwin ABI.</span>
+<a name="l02561"></a>02561 ArgOffset += isPPC64 ? 8 : ObjSize;
+<a name="l02562"></a>02562 <span class="keywordflow">break</span>;
+<a name="l02563"></a>02563 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l02564"></a>02564 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>:
+<a name="l02565"></a>02565 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>:
+<a name="l02566"></a>02566 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>:
+<a name="l02567"></a>02567 <span class="comment">// Note that vector arguments in registers don't reserve stack space,</span>
+<a name="l02568"></a>02568 <span class="comment">// except in varargs functions.</span>
+<a name="l02569"></a>02569 <span class="keywordflow">if</span> (VR_idx != Num_VR_Regs) {
+<a name="l02570"></a>02570 <span class="keywordtype">unsigned</span> VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(VR[VR_idx], &PPC::VRRCRegClass);
+<a name="l02571"></a>02571 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, ObjectVT);
+<a name="l02572"></a>02572 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l02573"></a>02573 <span class="keywordflow">while</span> ((ArgOffset % 16) != 0) {
+<a name="l02574"></a>02574 ArgOffset += PtrByteSize;
+<a name="l02575"></a>02575 <span class="keywordflow">if</span> (GPR_idx != Num_GPR_Regs)
+<a name="l02576"></a>02576 GPR_idx++;
+<a name="l02577"></a>02577 }
+<a name="l02578"></a>02578 ArgOffset += 16;
+<a name="l02579"></a>02579 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); <span class="comment">// FIXME correct for ppc64?</span>
+<a name="l02580"></a>02580 }
+<a name="l02581"></a>02581 ++VR_idx;
+<a name="l02582"></a>02582 } <span class="keywordflow">else</span> {
+<a name="l02583"></a>02583 <span class="keywordflow">if</span> (!isVarArg && !isPPC64) {
+<a name="l02584"></a>02584 <span class="comment">// Vectors go after all the nonvectors.</span>
+<a name="l02585"></a>02585 CurArgOffset = VecArgOffset;
+<a name="l02586"></a>02586 VecArgOffset += 16;
+<a name="l02587"></a>02587 } <span class="keywordflow">else</span> {
+<a name="l02588"></a>02588 <span class="comment">// Vectors are aligned.</span>
+<a name="l02589"></a>02589 ArgOffset = ((ArgOffset+15)/16)*16;
+<a name="l02590"></a>02590 CurArgOffset = ArgOffset;
+<a name="l02591"></a>02591 ArgOffset += 16;
+<a name="l02592"></a>02592 }
+<a name="l02593"></a>02593 needsLoad = <span class="keyword">true</span>;
+<a name="l02594"></a>02594 }
+<a name="l02595"></a>02595 <span class="keywordflow">break</span>;
+<a name="l02596"></a>02596 }
+<a name="l02597"></a>02597
+<a name="l02598"></a>02598 <span class="comment">// We need to load the argument to a virtual register if we determined above</span>
+<a name="l02599"></a>02599 <span class="comment">// that we ran out of physical registers of the appropriate type.</span>
+<a name="l02600"></a>02600 <span class="keywordflow">if</span> (needsLoad) {
+<a name="l02601"></a>02601 <span class="keywordtype">int</span> FI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(ObjSize,
+<a name="l02602"></a>02602 CurArgOffset + (ArgSize - ObjSize),
+<a name="l02603"></a>02603 isImmutable);
+<a name="l02604"></a>02604 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, PtrVT);
+<a name="l02605"></a>02605 ArgVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(ObjectVT, dl, Chain, FIN, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l02606"></a>02606 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02607"></a>02607 }
+<a name="l02608"></a>02608
+<a name="l02609"></a>02609 InVals.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(ArgVal);
+<a name="l02610"></a>02610 }
+<a name="l02611"></a>02611
+<a name="l02612"></a>02612 <span class="comment">// Set the size that is at least reserved in caller of this function. Tail</span>
+<a name="l02613"></a>02613 <span class="comment">// call optimized functions' reserved stack space needs to be aligned so that</span>
+<a name="l02614"></a>02614 <span class="comment">// taking the difference between two stack areas will result in an aligned</span>
+<a name="l02615"></a>02615 <span class="comment">// stack.</span>
+<a name="l02616"></a>02616 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
+<a name="l02617"></a>02617
+<a name="l02618"></a>02618 <span class="comment">// If the function takes variable number of arguments, make a frame index for</span>
+<a name="l02619"></a>02619 <span class="comment">// the start of the first vararg value... for expansion of llvm.va_start.</span>
+<a name="l02620"></a>02620 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l02621"></a>02621 <span class="keywordtype">int</span> Depth = ArgOffset;
+<a name="l02622"></a>02622
+<a name="l02623"></a>02623 FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#ada6f0ce61d2e0bfaef869dffc2d643ed">setVarArgsFrameIndex</a>(
+<a name="l02624"></a>02624 MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(PtrVT.getSizeInBits()/8,
+<a name="l02625"></a>02625 Depth, <span class="keyword">true</span>));
+<a name="l02626"></a>02626 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FuncInfo-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a0a78984133f621514980f087442645b4">getVarArgsFrameIndex</a>(), PtrVT);
+<a name="l02627"></a>02627
+<a name="l02628"></a>02628 <span class="comment">// If this function is vararg, store any remaining integer argument regs</span>
+<a name="l02629"></a>02629 <span class="comment">// to their spots on the stack so that they may be loaded by deferencing the</span>
+<a name="l02630"></a>02630 <span class="comment">// result of va_next.</span>
+<a name="l02631"></a>02631 <span class="keywordflow">for</span> (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
+<a name="l02632"></a>02632 <span class="keywordtype">unsigned</span> VReg;
+<a name="l02633"></a>02633
+<a name="l02634"></a>02634 <span class="keywordflow">if</span> (isPPC64)
+<a name="l02635"></a>02635 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::G8RCRegClass);
+<a name="l02636"></a>02636 <span class="keywordflow">else</span>
+<a name="l02637"></a>02637 VReg = MF.<a class="code" href="classllvm_1_1MachineFunction.html#aef2c847a530f7f7f5aaaeac74ba7e385">addLiveIn</a>(GPR[GPR_idx], &PPC::GPRCRegClass);
+<a name="l02638"></a>02638
+<a name="l02639"></a>02639 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, VReg, PtrVT);
+<a name="l02640"></a>02640 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, FIN,
+<a name="l02641"></a>02641 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02642"></a>02642 MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l02643"></a>02643 <span class="comment">// Increment the address by four for the next argument to store</span>
+<a name="l02644"></a>02644 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(PtrVT.getSizeInBits()/8, PtrVT);
+<a name="l02645"></a>02645 FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), FIN, PtrOff);
+<a name="l02646"></a>02646 }
+<a name="l02647"></a>02647 }
+<a name="l02648"></a>02648
+<a name="l02649"></a>02649 <span class="keywordflow">if</span> (!MemOps.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l02650"></a>02650 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad469508535ce2082a1ab1f0e429187b8">ISD::TokenFactor</a>, dl,
+<a name="l02651"></a>02651 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, &MemOps[0], MemOps.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l02652"></a>02652
+<a name="l02653"></a>02653 <span class="keywordflow">return</span> Chain;
+<a name="l02654"></a>02654 }
+<a name="l02655"></a>02655 <span class="comment"></span>
+<a name="l02656"></a>02656 <span class="comment">/// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus</span>
+<a name="l02657"></a>02657 <span class="comment">/// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.</span>
+<a name="l02658"></a>02658 <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">unsigned</span>
+<a name="l02659"></a><a class="code" href="PPCISelLowering_8cpp.html#a3c31aec5751525d6fd2c9a3c7916b637">02659</a> <a class="code" href="PPCISelLowering_8cpp.html#a3c31aec5751525d6fd2c9a3c7916b637">CalculateParameterAndLinkageAreaSize</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l02660"></a>02660 <span class="keywordtype">bool</span> isPPC64,
+<a name="l02661"></a>02661 <span class="keywordtype">bool</span> isVarArg,
+<a name="l02662"></a>02662 <span class="keywordtype">unsigned</span> CC,
+<a name="l02663"></a>02663 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::OutputArg></a>
+<a name="l02664"></a>02664 &Outs,
+<a name="l02665"></a>02665 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &OutVals,
+<a name="l02666"></a>02666 <span class="keywordtype">unsigned</span> &nAltivecParamsAtEnd) {
+<a name="l02667"></a>02667 <span class="comment">// Count how many bytes are to be pushed on the stack, including the linkage</span>
+<a name="l02668"></a>02668 <span class="comment">// area, and parameter passing area. We start with 24/48 bytes, which is</span>
+<a name="l02669"></a>02669 <span class="comment">// prereserved space for [SP][CR][LR][3 x unused].</span>
+<a name="l02670"></a>02670 <span class="keywordtype">unsigned</span> NumBytes = <a class="code" href="classllvm_1_1PPCFrameLowering.html#ab90d8608756fd53ed946d0eab8ad6cb7">PPCFrameLowering::getLinkageSize</a>(isPPC64, <span class="keyword">true</span>);
+<a name="l02671"></a>02671 <span class="keywordtype">unsigned</span> NumOps = Outs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>();
+<a name="l02672"></a>02672 <span class="keywordtype">unsigned</span> PtrByteSize = isPPC64 ? 8 : 4;
+<a name="l02673"></a>02673
+<a name="l02674"></a>02674 <span class="comment">// Add up all the space actually used.</span>
+<a name="l02675"></a>02675 <span class="comment">// In 32-bit non-varargs calls, Altivec parameters all go at the end; usually</span>
+<a name="l02676"></a>02676 <span class="comment">// they all go in registers, but we must reserve stack space for them for</span>
+<a name="l02677"></a>02677 <span class="comment">// possible use by the caller. In varargs or 64-bit calls, parameters are</span>
+<a name="l02678"></a>02678 <span class="comment">// assigned stack space in order, with padding so Altivec parameters are</span>
+<a name="l02679"></a>02679 <span class="comment">// 16-byte aligned.</span>
+<a name="l02680"></a>02680 nAltivecParamsAtEnd = 0;
+<a name="l02681"></a>02681 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != NumOps; ++i) {
+<a name="l02682"></a>02682 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags = Outs[i].Flags;
+<a name="l02683"></a>02683 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ArgVT = Outs[i].VT;
+<a name="l02684"></a>02684 <span class="comment">// Varargs Altivec parameters are padded to a 16 byte boundary.</span>
+<a name="l02685"></a>02685 <span class="keywordflow">if</span> (ArgVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a> || ArgVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a> ||
+<a name="l02686"></a>02686 ArgVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a> || ArgVT==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>) {
+<a name="l02687"></a>02687 <span class="keywordflow">if</span> (!isVarArg && !isPPC64) {
+<a name="l02688"></a>02688 <span class="comment">// Non-varargs Altivec parameters go after all the non-Altivec</span>
+<a name="l02689"></a>02689 <span class="comment">// parameters; handle those later so we know how much padding we need.</span>
+<a name="l02690"></a>02690 nAltivecParamsAtEnd++;
+<a name="l02691"></a>02691 <span class="keywordflow">continue</span>;
+<a name="l02692"></a>02692 }
+<a name="l02693"></a>02693 <span class="comment">// Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.</span>
+<a name="l02694"></a>02694 NumBytes = ((NumBytes+15)/16)*16;
+<a name="l02695"></a>02695 }
+<a name="l02696"></a>02696 NumBytes += <a class="code" href="PPCISelLowering_8cpp.html#aacd7e508c9e6dd17afc738da27b87bc2">CalculateStackSlotSize</a>(ArgVT, Flags, PtrByteSize);
+<a name="l02697"></a>02697 }
+<a name="l02698"></a>02698
+<a name="l02699"></a>02699 <span class="comment">// Allow for Altivec parameters at the end, if needed.</span>
+<a name="l02700"></a>02700 <span class="keywordflow">if</span> (nAltivecParamsAtEnd) {
+<a name="l02701"></a>02701 NumBytes = ((NumBytes+15)/16)*16;
+<a name="l02702"></a>02702 NumBytes += 16*nAltivecParamsAtEnd;
+<a name="l02703"></a>02703 }
+<a name="l02704"></a>02704
+<a name="l02705"></a>02705 <span class="comment">// The prolog code of the callee may store up to 8 GPR argument registers to</span>
+<a name="l02706"></a>02706 <span class="comment">// the stack, allowing va_start to index over them in memory if its varargs.</span>
+<a name="l02707"></a>02707 <span class="comment">// Because we cannot tell if this is needed on the caller side, we have to</span>
+<a name="l02708"></a>02708 <span class="comment">// conservatively assume that it is needed. As such, make sure we have at</span>
+<a name="l02709"></a>02709 <span class="comment">// least enough stack space for the caller to store the 8 GPRs.</span>
+<a name="l02710"></a>02710 NumBytes = std::max(NumBytes,
+<a name="l02711"></a>02711 <a class="code" href="classllvm_1_1PPCFrameLowering.html#ad6cf9c804045cfe1b414dd12b18e86ca">PPCFrameLowering::getMinCallFrameSize</a>(isPPC64, <span class="keyword">true</span>));
+<a name="l02712"></a>02712
+<a name="l02713"></a>02713 <span class="comment">// Tail call needs the stack to be aligned.</span>
+<a name="l02714"></a>02714 <span class="keywordflow">if</span> (CC == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a> && DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ab1fb67187fc37e569cc5171cbebba873">Options</a>.<a class="code" href="classllvm_1_1TargetOptions.html#ad54fc81a4ef7ab96137a9b6e78fdf838">GuaranteedTailCallOpt</a>){
+<a name="l02715"></a>02715 <span class="keywordtype">unsigned</span> TargetAlign = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().
+<a name="l02716"></a>02716 getFrameLowering()->getStackAlignment();
+<a name="l02717"></a>02717 <span class="keywordtype">unsigned</span> AlignMask = TargetAlign-1;
+<a name="l02718"></a>02718 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
+<a name="l02719"></a>02719 }
+<a name="l02720"></a>02720
+<a name="l02721"></a>02721 <span class="keywordflow">return</span> NumBytes;
+<a name="l02722"></a>02722 }
+<a name="l02723"></a>02723 <span class="comment"></span>
+<a name="l02724"></a>02724 <span class="comment">/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be</span>
+<a name="l02725"></a>02725 <span class="comment">/// adjusted to accommodate the arguments for the tailcall.</span>
+<a name="l02726"></a><a class="code" href="PPCISelLowering_8cpp.html#aaf0bcfcb9ee7e078bec6074304e31cb0">02726</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">int</span> <a class="code" href="PPCISelLowering_8cpp.html#aaf0bcfcb9ee7e078bec6074304e31cb0">CalculateTailCallSPDiff</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a>& DAG, <span class="keywordtype">bool</span> isTailCall,
+<a name="l02727"></a>02727 <span class="keywordtype">unsigned</span> ParamSize) {
+<a name="l02728"></a>02728
+<a name="l02729"></a>02729 <span class="keywordflow">if</span> (!isTailCall) <span class="keywordflow">return</span> 0;
+<a name="l02730"></a>02730
+<a name="l02731"></a>02731 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FI = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l02732"></a>02732 <span class="keywordtype">unsigned</span> CallerMinReservedArea = FI-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#ac3642c7af6c2fd311f64b648c72057b5">getMinReservedArea</a>();
+<a name="l02733"></a>02733 <span class="keywordtype">int</span> SPDiff = (int)CallerMinReservedArea - (<span class="keywordtype">int</span>)ParamSize;
+<a name="l02734"></a>02734 <span class="comment">// Remember only if the new adjustement is bigger.</span>
+<a name="l02735"></a>02735 <span class="keywordflow">if</span> (SPDiff < FI->getTailCallSPDelta())
+<a name="l02736"></a>02736 FI-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a7780eaaa923683ff9eac5b49916136bc">setTailCallSPDelta</a>(SPDiff);
+<a name="l02737"></a>02737
+<a name="l02738"></a>02738 <span class="keywordflow">return</span> SPDiff;
+<a name="l02739"></a>02739 }
+<a name="l02740"></a>02740 <span class="comment"></span>
+<a name="l02741"></a>02741 <span class="comment">/// IsEligibleForTailCallOptimization - Check whether the call is eligible</span>
+<a name="l02742"></a>02742 <span class="comment">/// for tail call optimization. Targets which want to do tail call</span>
+<a name="l02743"></a>02743 <span class="comment">/// optimization should implement this function.</span>
+<a name="l02744"></a>02744 <span class="comment"></span><span class="keywordtype">bool</span>
+<a name="l02745"></a>02745 PPCTargetLowering::IsEligibleForTailCallOptimization(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Callee,
+<a name="l02746"></a>02746 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CalleeCC,
+<a name="l02747"></a>02747 <span class="keywordtype">bool</span> isVarArg,
+<a name="l02748"></a>02748 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a> &Ins,
+<a name="l02749"></a>02749 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a>& DAG)<span class="keyword"> const </span>{
+<a name="l02750"></a>02750 <span class="keywordflow">if</span> (!<a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().Options.GuaranteedTailCallOpt)
+<a name="l02751"></a>02751 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l02752"></a>02752
+<a name="l02753"></a>02753 <span class="comment">// Variable argument functions are not supported.</span>
+<a name="l02754"></a>02754 <span class="keywordflow">if</span> (isVarArg)
+<a name="l02755"></a>02755 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l02756"></a>02756
+<a name="l02757"></a>02757 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l02758"></a>02758 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallerCC = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ad784a6594990530bffb2018aeeed56f3">getFunction</a>()-><a class="code" href="classllvm_1_1Function.html#af4d5ada526cdf057f5f29047e058187d">getCallingConv</a>();
+<a name="l02759"></a>02759 <span class="keywordflow">if</span> (CalleeCC == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a> && CallerCC == CalleeCC) {
+<a name="l02760"></a>02760 <span class="comment">// Functions containing by val parameters are not supported.</span>
+<a name="l02761"></a>02761 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != Ins.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i++) {
+<a name="l02762"></a>02762 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags = Ins[i].Flags;
+<a name="l02763"></a>02763 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a34ee642bf0fb623f775e04e0e60d9b26">isByVal</a>()) <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l02764"></a>02764 }
+<a name="l02765"></a>02765
+<a name="l02766"></a>02766 <span class="comment">// Non PIC/GOT tail calls are supported.</span>
+<a name="l02767"></a>02767 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a87f1815c4b56735aaadbbcdfdf32cf4f">getRelocationModel</a>() != <a class="code" href="namespacellvm_1_1Reloc.html#af59f6dc86e80aaf56f1afd155eebf568adc2075e13a68142b26e05ac08bbfc320">Reloc::PIC_</a>)
+<a name="l02768"></a>02768 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l02769"></a>02769
+<a name="l02770"></a>02770 <span class="comment">// At the moment we can only do local tail calls (in same module, hidden</span>
+<a name="l02771"></a>02771 <span class="comment">// or protected) if we are generating PIC.</span>
+<a name="l02772"></a>02772 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1GlobalAddressSDNode.html">GlobalAddressSDNode</a> *G = dyn_cast<GlobalAddressSDNode>(Callee))
+<a name="l02773"></a>02773 <span class="keywordflow">return</span> G->getGlobal()->hasHiddenVisibility()
+<a name="l02774"></a>02774 || G->getGlobal()->hasProtectedVisibility();
+<a name="l02775"></a>02775 }
+<a name="l02776"></a>02776
+<a name="l02777"></a>02777 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l02778"></a>02778 }
+<a name="l02779"></a>02779 <span class="comment"></span>
+<a name="l02780"></a>02780 <span class="comment">/// isCallCompatibleAddress - Return the immediate to use if the specified</span>
+<a name="l02781"></a>02781 <span class="comment">/// 32-bit value is representable in the immediate field of a BxA instruction.</span>
+<a name="l02782"></a><a class="code" href="PPCISelLowering_8cpp.html#aca2e60fc82a1bde79b2afe10ef5c520d">02782</a> <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="PPCISelLowering_8cpp.html#aca2e60fc82a1bde79b2afe10ef5c520d">isBLACompatibleAddress</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG) {
+<a name="l02783"></a>02783 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *C = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(Op);
+<a name="l02784"></a>02784 <span class="keywordflow">if</span> (!C) <span class="keywordflow">return</span> 0;
+<a name="l02785"></a>02785
+<a name="l02786"></a>02786 <span class="keywordtype">int</span> Addr = C-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l02787"></a>02787 <span class="keywordflow">if</span> ((Addr & 3) != 0 || <span class="comment">// Low 2 bits are implicitly zero.</span>
+<a name="l02788"></a>02788 SignExtend32<26>(Addr) != Addr)
+<a name="l02789"></a>02789 <span class="keywordflow">return</span> 0; <span class="comment">// Top 6 bits have to be sext of immediate.</span>
+<a name="l02790"></a>02790
+<a name="l02791"></a>02791 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>((<span class="keywordtype">int</span>)C-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>() >> 2,
+<a name="l02792"></a>02792 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>()).getNode();
+<a name="l02793"></a>02793 }
+<a name="l02794"></a>02794
+<a name="l02795"></a>02795 <span class="keyword">namespace </span>{
+<a name="l02796"></a>02796
+<a name="l02797"></a>02797 <span class="keyword">struct </span>TailCallArgumentInfo {
+<a name="l02798"></a>02798 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg;
+<a name="l02799"></a>02799 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FrameIdxOp;
+<a name="l02800"></a>02800 <span class="keywordtype">int</span> FrameIdx;
+<a name="l02801"></a>02801
+<a name="l02802"></a>02802 TailCallArgumentInfo() : FrameIdx(0) {}
+<a name="l02803"></a>02803 };
+<a name="l02804"></a>02804
+<a name="l02805"></a>02805 }
+<a name="l02806"></a>02806 <span class="comment"></span>
+<a name="l02807"></a>02807 <span class="comment">/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.</span>
+<a name="l02808"></a>02808 <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l02809"></a><a class="code" href="PPCISelLowering_8cpp.html#ac377a43ca6d83ebb604beff3d8a3f55d">02809</a> <a class="code" href="PPCISelLowering_8cpp.html#ac377a43ca6d83ebb604beff3d8a3f55d" title="StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.">StoreTailCallArgumentsToStackSlot</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l02810"></a>02810 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l02811"></a>02811 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<TailCallArgumentInfo, 8></a> &TailCallArgs,
+<a name="l02812"></a>02812 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> &MemOpChains,
+<a name="l02813"></a>02813 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl) {
+<a name="l02814"></a>02814 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = TailCallArgs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i != e; ++i) {
+<a name="l02815"></a>02815 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg = TailCallArgs[i].Arg;
+<a name="l02816"></a>02816 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = TailCallArgs[i].FrameIdxOp;
+<a name="l02817"></a>02817 <span class="keywordtype">int</span> FI = TailCallArgs[i].FrameIdx;
+<a name="l02818"></a>02818 <span class="comment">// Store relative to framepointer.</span>
+<a name="l02819"></a>02819 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, Arg, FIN,
+<a name="l02820"></a>02820 <a class="code" href="structllvm_1_1MachinePointerInfo.html#acb492206d94d8f8179f797d4c7966ba9">MachinePointerInfo::getFixedStack</a>(FI),
+<a name="l02821"></a>02821 <span class="keyword">false</span>, <span class="keyword">false</span>, 0));
+<a name="l02822"></a>02822 }
+<a name="l02823"></a>02823 }
+<a name="l02824"></a>02824 <span class="comment"></span>
+<a name="l02825"></a>02825 <span class="comment">/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to</span>
+<a name="l02826"></a>02826 <span class="comment">/// the appropriate stack slot for the tail call optimized function call.</span>
+<a name="l02827"></a><a class="code" href="PPCISelLowering_8cpp.html#af6c5edb170ddab3de8d53f1168a6f6c0">02827</a> <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="PPCISelLowering_8cpp.html#af6c5edb170ddab3de8d53f1168a6f6c0">EmitTailCallStoreFPAndRetAddr</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l02828"></a>02828 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF,
+<a name="l02829"></a>02829 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l02830"></a>02830 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OldRetAddr,
+<a name="l02831"></a>02831 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OldFP,
+<a name="l02832"></a>02832 <span class="keywordtype">int</span> SPDiff,
+<a name="l02833"></a>02833 <span class="keywordtype">bool</span> isPPC64,
+<a name="l02834"></a>02834 <span class="keywordtype">bool</span> isDarwinABI,
+<a name="l02835"></a>02835 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl) {
+<a name="l02836"></a>02836 <span class="keywordflow">if</span> (SPDiff) {
+<a name="l02837"></a>02837 <span class="comment">// Calculate the new stack slot for the return address.</span>
+<a name="l02838"></a>02838 <span class="keywordtype">int</span> SlotSize = isPPC64 ? 8 : 4;
+<a name="l02839"></a>02839 <span class="keywordtype">int</span> NewRetAddrLoc = SPDiff + <a class="code" href="classllvm_1_1PPCFrameLowering.html#a4d69526bf0c3ba246820af1cbc25effe">PPCFrameLowering::getReturnSaveOffset</a>(isPPC64,
+<a name="l02840"></a>02840 isDarwinABI);
+<a name="l02841"></a>02841 <span class="keywordtype">int</span> NewRetAddr = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(SlotSize,
+<a name="l02842"></a>02842 NewRetAddrLoc, <span class="keyword">true</span>);
+<a name="l02843"></a>02843 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = isPPC64 ? <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> : <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>;
+<a name="l02844"></a>02844 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> NewRetAddrFrIdx = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(NewRetAddr, VT);
+<a name="l02845"></a>02845 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
+<a name="l02846"></a>02846 <a class="code" href="structllvm_1_1MachinePointerInfo.html#acb492206d94d8f8179f797d4c7966ba9">MachinePointerInfo::getFixedStack</a>(NewRetAddr),
+<a name="l02847"></a>02847 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02848"></a>02848
+<a name="l02849"></a>02849 <span class="comment">// When using the 32/64-bit SVR4 ABI there is no need to move the FP stack</span>
+<a name="l02850"></a>02850 <span class="comment">// slot as the FP is never overwritten.</span>
+<a name="l02851"></a>02851 <span class="keywordflow">if</span> (isDarwinABI) {
+<a name="l02852"></a>02852 <span class="keywordtype">int</span> NewFPLoc =
+<a name="l02853"></a>02853 SPDiff + <a class="code" href="classllvm_1_1PPCFrameLowering.html#a97db50b03c1daa960e8d2e0fcb9e9f8b">PPCFrameLowering::getFramePointerSaveOffset</a>(isPPC64, isDarwinABI);
+<a name="l02854"></a>02854 <span class="keywordtype">int</span> NewFPIdx = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(SlotSize, NewFPLoc,
+<a name="l02855"></a>02855 <span class="keyword">true</span>);
+<a name="l02856"></a>02856 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> NewFramePtrIdx = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(NewFPIdx, VT);
+<a name="l02857"></a>02857 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, OldFP, NewFramePtrIdx,
+<a name="l02858"></a>02858 <a class="code" href="structllvm_1_1MachinePointerInfo.html#acb492206d94d8f8179f797d4c7966ba9">MachinePointerInfo::getFixedStack</a>(NewFPIdx),
+<a name="l02859"></a>02859 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02860"></a>02860 }
+<a name="l02861"></a>02861 }
+<a name="l02862"></a>02862 <span class="keywordflow">return</span> Chain;
+<a name="l02863"></a>02863 }
+<a name="l02864"></a>02864 <span class="comment"></span>
+<a name="l02865"></a>02865 <span class="comment">/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate</span>
+<a name="l02866"></a>02866 <span class="comment">/// the position of the argument.</span>
+<a name="l02867"></a>02867 <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l02868"></a><a class="code" href="PPCISelLowering_8cpp.html#acbd75cbe0914841fc7e59e69bb8d1654">02868</a> <a class="code" href="PPCISelLowering_8cpp.html#acbd75cbe0914841fc7e59e69bb8d1654">CalculateTailCallArgDest</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG, <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF, <span class="keywordtype">bool</span> isPPC64,
+<a name="l02869"></a>02869 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg, <span class="keywordtype">int</span> SPDiff, <span class="keywordtype">unsigned</span> ArgOffset,
+<a name="l02870"></a>02870 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<TailCallArgumentInfo, 8></a>& TailCallArguments) {
+<a name="l02871"></a>02871 <span class="keywordtype">int</span> Offset = ArgOffset + SPDiff;
+<a name="l02872"></a>02872 uint32_t <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933ad11797b0ad89e5eb13f16d7a2ba9741e">OpSize</a> = (Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()+7)/8;
+<a name="l02873"></a>02873 <span class="keywordtype">int</span> FI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(OpSize, Offset, <span class="keyword">true</span>);
+<a name="l02874"></a>02874 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = isPPC64 ? <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> : <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>;
+<a name="l02875"></a>02875 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIN = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FI, VT);
+<a name="l02876"></a>02876 TailCallArgumentInfo Info;
+<a name="l02877"></a>02877 Info.Arg = Arg;
+<a name="l02878"></a>02878 Info.FrameIdxOp = FIN;
+<a name="l02879"></a>02879 Info.FrameIdx = FI;
+<a name="l02880"></a>02880 TailCallArguments.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Info);
+<a name="l02881"></a>02881 }
+<a name="l02882"></a>02882 <span class="comment"></span>
+<a name="l02883"></a>02883 <span class="comment">/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address</span>
+<a name="l02884"></a>02884 <span class="comment">/// stack slot. Returns the chain as result and the loaded frame pointers in</span>
+<a name="l02885"></a>02885 <span class="comment">/// LROpOut/FPOpout. Used when tail calling.</span>
+<a name="l02886"></a>02886 <span class="comment"></span><a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> & DAG,
+<a name="l02887"></a>02887 <span class="keywordtype">int</span> SPDiff,
+<a name="l02888"></a>02888 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l02889"></a>02889 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &LROpOut,
+<a name="l02890"></a>02890 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &FPOpOut,
+<a name="l02891"></a>02891 <span class="keywordtype">bool</span> isDarwinABI,
+<a name="l02892"></a>02892 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl)<span class="keyword"> const </span>{
+<a name="l02893"></a>02893 <span class="keywordflow">if</span> (SPDiff) {
+<a name="l02894"></a>02894 <span class="comment">// Load the LR and FP stack slot for later adjusting.</span>
+<a name="l02895"></a>02895 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>() ? <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> : MVT::i32;
+<a name="l02896"></a>02896 LROpOut = getReturnAddrFrameIndex(DAG);
+<a name="l02897"></a>02897 LROpOut = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(VT, dl, Chain, LROpOut, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l02898"></a>02898 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02899"></a>02899 Chain = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(LROpOut.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), 1);
+<a name="l02900"></a>02900
+<a name="l02901"></a>02901 <span class="comment">// When using the 32/64-bit SVR4 ABI there is no need to load the FP stack</span>
+<a name="l02902"></a>02902 <span class="comment">// slot as the FP is never overwritten.</span>
+<a name="l02903"></a>02903 <span class="keywordflow">if</span> (isDarwinABI) {
+<a name="l02904"></a>02904 FPOpOut = getFramePointerFrameIndex(DAG);
+<a name="l02905"></a>02905 FPOpOut = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(VT, dl, Chain, FPOpOut, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l02906"></a>02906 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l02907"></a>02907 Chain = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(FPOpOut.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), 1);
+<a name="l02908"></a>02908 }
+<a name="l02909"></a>02909 }
+<a name="l02910"></a>02910 <span class="keywordflow">return</span> Chain;
+<a name="l02911"></a>02911 }
+<a name="l02912"></a>02912 <span class="comment"></span>
+<a name="l02913"></a>02913 <span class="comment">/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified</span>
+<a name="l02914"></a>02914 <span class="comment">/// by "Src" to address "Dst" of size "Size". Alignment information is</span>
+<a name="l02915"></a>02915 <span class="comment">/// specified by the specific parameter attribute. The copy will be passed as</span>
+<a name="l02916"></a>02916 <span class="comment">/// a byval function parameter.</span>
+<a name="l02917"></a>02917 <span class="comment">/// Sometimes what we are copying is the end of a larger object, the part that</span>
+<a name="l02918"></a>02918 <span class="comment">/// does not fit in registers.</span>
+<a name="l02919"></a>02919 <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l02920"></a><a class="code" href="PPCISelLowering_8cpp.html#a9af2525638d1b14080afae2d307a0dce">02920</a> <a class="code" href="PPCISelLowering_8cpp.html#a9af2525638d1b14080afae2d307a0dce">CreateCopyOfByValArgument</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Src, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Dst, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l02921"></a>02921 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l02922"></a>02922 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl) {
+<a name="l02923"></a>02923 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SizeNode = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a20485215f1c6f05a5c5209725c93de2f">getByValSize</a>(), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02924"></a>02924 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ae9fd1d41eb20949f16b3ec4fdd273d01">getMemcpy</a>(Chain, dl, Dst, Src, SizeNode, Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a24db357868a02447db2862c8b5cef52f">getByValAlign</a>(),
+<a name="l02925"></a>02925 <span class="keyword">false</span>, <span class="keyword">false</span>, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(0),
+<a name="l02926"></a>02926 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(0));
+<a name="l02927"></a>02927 }
+<a name="l02928"></a>02928 <span class="comment"></span>
+<a name="l02929"></a>02929 <span class="comment">/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of</span>
+<a name="l02930"></a>02930 <span class="comment">/// tail calls.</span>
+<a name="l02931"></a>02931 <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l02932"></a><a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">02932</a> <a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">LowerMemOpCallTo</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG, <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l02933"></a>02933 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff, <span class="keywordtype">int</span> SPDiff,
+<a name="l02934"></a>02934 <span class="keywordtype">unsigned</span> ArgOffset, <span class="keywordtype">bool</span> isPPC64, <span class="keywordtype">bool</span> isTailCall,
+<a name="l02935"></a>02935 <span class="keywordtype">bool</span> isVector, <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> &MemOpChains,
+<a name="l02936"></a>02936 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<TailCallArgumentInfo, 8></a> &TailCallArguments,
+<a name="l02937"></a>02937 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl) {
+<a name="l02938"></a>02938 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l02939"></a>02939 <span class="keywordflow">if</span> (!isTailCall) {
+<a name="l02940"></a>02940 <span class="keywordflow">if</span> (isVector) {
+<a name="l02941"></a>02941 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> StackPtr;
+<a name="l02942"></a>02942 <span class="keywordflow">if</span> (isPPC64)
+<a name="l02943"></a>02943 StackPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::X1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l02944"></a>02944 <span class="keywordflow">else</span>
+<a name="l02945"></a>02945 StackPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::R1, MVT::i32);
+<a name="l02946"></a>02946 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, StackPtr,
+<a name="l02947"></a>02947 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(ArgOffset, PtrVT));
+<a name="l02948"></a>02948 }
+<a name="l02949"></a>02949 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, Arg, PtrOff,
+<a name="l02950"></a>02950 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0));
+<a name="l02951"></a>02951 <span class="comment">// Calculate and remember argument location.</span>
+<a name="l02952"></a>02952 } <span class="keywordflow">else</span> <a class="code" href="PPCISelLowering_8cpp.html#acbd75cbe0914841fc7e59e69bb8d1654">CalculateTailCallArgDest</a>(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
+<a name="l02953"></a>02953 TailCallArguments);
+<a name="l02954"></a>02954 }
+<a name="l02955"></a>02955
+<a name="l02956"></a>02956 <span class="keyword">static</span>
+<a name="l02957"></a><a class="code" href="PPCISelLowering_8cpp.html#a6e0cf06aedc5ad75745f3834560a71a6">02957</a> <span class="keywordtype">void</span> <a class="code" href="PPCISelLowering_8cpp.html#a6e0cf06aedc5ad75745f3834560a71a6">PrepareTailCall</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &InFlag, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Chain,
+<a name="l02958"></a>02958 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <span class="keywordtype">bool</span> isPPC64, <span class="keywordtype">int</span> SPDiff, <span class="keywordtype">unsigned</span> NumBytes,
+<a name="l02959"></a>02959 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LROp, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FPOp, <span class="keywordtype">bool</span> isDarwinABI,
+<a name="l02960"></a>02960 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<TailCallArgumentInfo, 8></a> &TailCallArguments) {
+<a name="l02961"></a>02961 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l02962"></a>02962
+<a name="l02963"></a>02963 <span class="comment">// Emit a sequence of copyto/copyfrom virtual registers for arguments that</span>
+<a name="l02964"></a>02964 <span class="comment">// might overwrite each other in case of tail call optimization.</span>
+<a name="l02965"></a>02965 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> MemOpChains2;
+<a name="l02966"></a>02966 <span class="comment">// Do not flag preceding copytoreg stuff together with the following stuff.</span>
+<a name="l02967"></a>02967 InFlag = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l02968"></a>02968 <a class="code" href="PPCISelLowering_8cpp.html#ac377a43ca6d83ebb604beff3d8a3f55d" title="StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.">StoreTailCallArgumentsToStackSlot</a>(DAG, Chain, TailCallArguments,
+<a name="l02969"></a>02969 MemOpChains2, dl);
+<a name="l02970"></a>02970 <span class="keywordflow">if</span> (!MemOpChains2.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l02971"></a>02971 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad469508535ce2082a1ab1f0e429187b8">ISD::TokenFactor</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>,
+<a name="l02972"></a>02972 &MemOpChains2[0], MemOpChains2.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l02973"></a>02973
+<a name="l02974"></a>02974 <span class="comment">// Store the return address to the appropriate stack slot.</span>
+<a name="l02975"></a>02975 Chain = <a class="code" href="PPCISelLowering_8cpp.html#af6c5edb170ddab3de8d53f1168a6f6c0">EmitTailCallStoreFPAndRetAddr</a>(DAG, MF, Chain, LROp, FPOp, SPDiff,
+<a name="l02976"></a>02976 isPPC64, isDarwinABI, dl);
+<a name="l02977"></a>02977
+<a name="l02978"></a>02978 <span class="comment">// Emit callseq_end just before tailcall node.</span>
+<a name="l02979"></a>02979 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a68ec943fbadc65f413d9cf63a501f70c">getCALLSEQ_END</a>(Chain, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(NumBytes, <span class="keyword">true</span>),
+<a name="l02980"></a>02980 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(0, <span class="keyword">true</span>), InFlag);
+<a name="l02981"></a>02981 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l02982"></a>02982 }
+<a name="l02983"></a>02983
+<a name="l02984"></a>02984 <span class="keyword">static</span>
+<a name="l02985"></a><a class="code" href="PPCISelLowering_8cpp.html#af8870998d9445390ad3472c180860a89">02985</a> <span class="keywordtype">unsigned</span> <a class="code" href="PPCISelLowering_8cpp.html#af8870998d9445390ad3472c180860a89">PrepareCall</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Callee, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &InFlag,
+<a name="l02986"></a>02986 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Chain, <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <span class="keywordtype">int</span> SPDiff, <span class="keywordtype">bool</span> isTailCall,
+<a name="l02987"></a>02987 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector</a><std::pair<unsigned, SDValue>, 8> &RegsToPass,
+<a name="l02988"></a>02988 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> &Ops, std::vector<EVT> &NodeTys,
+<a name="l02989"></a>02989 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a> &PPCSubTarget) {
+<a name="l02990"></a>02990
+<a name="l02991"></a>02991 <span class="keywordtype">bool</span> isPPC64 = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>();
+<a name="l02992"></a>02992 <span class="keywordtype">bool</span> isSVR4ABI = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>();
+<a name="l02993"></a>02993
+<a name="l02994"></a>02994 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l02995"></a>02995 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>); <span class="comment">// Returns a chain</span>
+<a name="l02996"></a>02996 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>); <span class="comment">// Returns a flag for retval copy to use.</span>
+<a name="l02997"></a>02997
+<a name="l02998"></a>02998 <span class="keywordtype">unsigned</span> CallOpc = isSVR4ABI ? <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66acf9dfc83dc60a6e978bde88a5f43c10c">PPCISD::CALL_SVR4</a> : <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abedf5397c58d51756c7a87898df6065c">PPCISD::CALL_Darwin</a>;
+<a name="l02999"></a>02999
+<a name="l03000"></a>03000 <span class="keywordtype">bool</span> needIndirectCall = <span class="keyword">true</span>;
+<a name="l03001"></a>03001 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Dest = <a class="code" href="PPCISelLowering_8cpp.html#aca2e60fc82a1bde79b2afe10ef5c520d">isBLACompatibleAddress</a>(Callee, DAG)) {
+<a name="l03002"></a>03002 <span class="comment">// If this is an absolute destination address, use the munged value.</span>
+<a name="l03003"></a>03003 Callee = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Dest, 0);
+<a name="l03004"></a>03004 needIndirectCall = <span class="keyword">false</span>;
+<a name="l03005"></a>03005 }
+<a name="l03006"></a>03006
+<a name="l03007"></a>03007 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1GlobalAddressSDNode.html">GlobalAddressSDNode</a> *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
+<a name="l03008"></a>03008 <span class="comment">// XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201</span>
+<a name="l03009"></a>03009 <span class="comment">// Use indirect calls for ALL functions calls in JIT mode, since the</span>
+<a name="l03010"></a>03010 <span class="comment">// far-call stubs may be outside relocation limits for a BL instruction.</span>
+<a name="l03011"></a>03011 <span class="keywordflow">if</span> (!DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a5af2fed99951774b6a14d30ec6e73792">getSubtarget</a><<a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a>>().isJITCodeModel()) {
+<a name="l03012"></a>03012 <span class="keywordtype">unsigned</span> OpFlags = 0;
+<a name="l03013"></a>03013 <span class="keywordflow">if</span> (DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a87f1815c4b56735aaadbbcdfdf32cf4f">getRelocationModel</a>() != <a class="code" href="namespacellvm_1_1Reloc.html#af59f6dc86e80aaf56f1afd155eebf568a2102fa713297236bf4339c5f0bf0f39d">Reloc::Static</a> &&
+<a name="l03014"></a>03014 (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#a3934c03d7d0973a65fa524182810ec34">getTargetTriple</a>().<a class="code" href="classllvm_1_1Triple.html#a046b1c05ec2d492f6572840cf8bac653">isMacOSX</a>() &&
+<a name="l03015"></a>03015 PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#a3934c03d7d0973a65fa524182810ec34">getTargetTriple</a>().<a class="code" href="classllvm_1_1Triple.html#af2ee35261532b22de8929f4d7c86e6ac">isMacOSXVersionLT</a>(10, 5)) &&
+<a name="l03016"></a>03016 (G->getGlobal()->isDeclaration() ||
+<a name="l03017"></a>03017 G->getGlobal()->isWeakForLinker())) {
+<a name="l03018"></a>03018 <span class="comment">// PC-relative references to external symbols should go through $stub,</span>
+<a name="l03019"></a>03019 <span class="comment">// unless we're building with the leopard linker or later, which</span>
+<a name="l03020"></a>03020 <span class="comment">// automatically synthesizes these stubs.</span>
+<a name="l03021"></a>03021 OpFlags = <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffae388379ce6a1637e40bc3e1320a414cd">PPCII::MO_DARWIN_STUB</a>;
+<a name="l03022"></a>03022 }
+<a name="l03023"></a>03023
+<a name="l03024"></a>03024 <span class="comment">// If the callee is a GlobalAddress/ExternalSymbol node (quite common,</span>
+<a name="l03025"></a>03025 <span class="comment">// every direct call is) turn it into a TargetGlobalAddress /</span>
+<a name="l03026"></a>03026 <span class="comment">// TargetExternalSymbol node so that legalize doesn't hack it.</span>
+<a name="l03027"></a>03027 Callee = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac42a2722cefd536e5c88535fd4c95288">getTargetGlobalAddress</a>(G->getGlobal(), dl,
+<a name="l03028"></a>03028 Callee.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(),
+<a name="l03029"></a>03029 0, OpFlags);
+<a name="l03030"></a>03030 needIndirectCall = <span class="keyword">false</span>;
+<a name="l03031"></a>03031 }
+<a name="l03032"></a>03032 }
+<a name="l03033"></a>03033
+<a name="l03034"></a>03034 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ExternalSymbolSDNode.html">ExternalSymbolSDNode</a> *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
+<a name="l03035"></a>03035 <span class="keywordtype">unsigned</span> <span class="keywordtype">char</span> OpFlags = 0;
+<a name="l03036"></a>03036
+<a name="l03037"></a>03037 <span class="keywordflow">if</span> (DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a87f1815c4b56735aaadbbcdfdf32cf4f">getRelocationModel</a>() != <a class="code" href="namespacellvm_1_1Reloc.html#af59f6dc86e80aaf56f1afd155eebf568a2102fa713297236bf4339c5f0bf0f39d">Reloc::Static</a> &&
+<a name="l03038"></a>03038 (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#a3934c03d7d0973a65fa524182810ec34">getTargetTriple</a>().<a class="code" href="classllvm_1_1Triple.html#a046b1c05ec2d492f6572840cf8bac653">isMacOSX</a>() &&
+<a name="l03039"></a>03039 PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#a3934c03d7d0973a65fa524182810ec34">getTargetTriple</a>().<a class="code" href="classllvm_1_1Triple.html#af2ee35261532b22de8929f4d7c86e6ac">isMacOSXVersionLT</a>(10, 5))) {
+<a name="l03040"></a>03040 <span class="comment">// PC-relative references to external symbols should go through $stub,</span>
+<a name="l03041"></a>03041 <span class="comment">// unless we're building with the leopard linker or later, which</span>
+<a name="l03042"></a>03042 <span class="comment">// automatically synthesizes these stubs.</span>
+<a name="l03043"></a>03043 OpFlags = <a class="code" href="namespacellvm_1_1PPCII.html#ae73836094d8b0399ba10a6e540a363ffae388379ce6a1637e40bc3e1320a414cd">PPCII::MO_DARWIN_STUB</a>;
+<a name="l03044"></a>03044 }
+<a name="l03045"></a>03045
+<a name="l03046"></a>03046 Callee = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ab5254dc94639bcdd77bf933ad2fe9ac3">getTargetExternalSymbol</a>(S->getSymbol(), Callee.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(),
+<a name="l03047"></a>03047 OpFlags);
+<a name="l03048"></a>03048 needIndirectCall = <span class="keyword">false</span>;
+<a name="l03049"></a>03049 }
+<a name="l03050"></a>03050
+<a name="l03051"></a>03051 <span class="keywordflow">if</span> (needIndirectCall) {
+<a name="l03052"></a>03052 <span class="comment">// Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair</span>
+<a name="l03053"></a>03053 <span class="comment">// to do the call, we can't use PPCISD::CALL.</span>
+<a name="l03054"></a>03054 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MTCTROps[] = {Chain, Callee, InFlag};
+<a name="l03055"></a>03055
+<a name="l03056"></a>03056 <span class="keywordflow">if</span> (isSVR4ABI && isPPC64) {
+<a name="l03057"></a>03057 <span class="comment">// Function pointers in the 64-bit SVR4 ABI do not point to the function</span>
+<a name="l03058"></a>03058 <span class="comment">// entry point, but to the function descriptor (the function entry point</span>
+<a name="l03059"></a>03059 <span class="comment">// address is part of the function descriptor though).</span>
+<a name="l03060"></a>03060 <span class="comment">// The function descriptor is a three doubleword structure with the</span>
+<a name="l03061"></a>03061 <span class="comment">// following fields: function entry point, TOC base address and</span>
+<a name="l03062"></a>03062 <span class="comment">// environment pointer.</span>
+<a name="l03063"></a>03063 <span class="comment">// Thus for a call through a function pointer, the following actions need</span>
+<a name="l03064"></a>03064 <span class="comment">// to be performed:</span>
+<a name="l03065"></a>03065 <span class="comment">// 1. Save the TOC of the caller in the TOC save area of its stack</span>
+<a name="l03066"></a>03066 <span class="comment">// frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).</span>
+<a name="l03067"></a>03067 <span class="comment">// 2. Load the address of the function entry point from the function</span>
+<a name="l03068"></a>03068 <span class="comment">// descriptor.</span>
+<a name="l03069"></a>03069 <span class="comment">// 3. Load the TOC of the callee from the function descriptor into r2.</span>
+<a name="l03070"></a>03070 <span class="comment">// 4. Load the environment pointer from the function descriptor into</span>
+<a name="l03071"></a>03071 <span class="comment">// r11.</span>
+<a name="l03072"></a>03072 <span class="comment">// 5. Branch to the function entry point address.</span>
+<a name="l03073"></a>03073 <span class="comment">// 6. On return of the callee, the TOC of the caller needs to be</span>
+<a name="l03074"></a>03074 <span class="comment">// restored (this is done in FinishCall()).</span>
+<a name="l03075"></a>03075 <span class="comment">//</span>
+<a name="l03076"></a>03076 <span class="comment">// All those operations are flagged together to ensure that no other</span>
+<a name="l03077"></a>03077 <span class="comment">// operations can be scheduled in between. E.g. without flagging the</span>
+<a name="l03078"></a>03078 <span class="comment">// operations together, a TOC access in the caller could be scheduled</span>
+<a name="l03079"></a>03079 <span class="comment">// between the load of the callee TOC and the branch to the callee, which</span>
+<a name="l03080"></a>03080 <span class="comment">// results in the TOC access going through the TOC of the callee instead</span>
+<a name="l03081"></a>03081 <span class="comment">// of going through the TOC of the caller, which leads to incorrect code.</span>
+<a name="l03082"></a>03082
+<a name="l03083"></a>03083 <span class="comment">// Load the address of the function entry point from the function</span>
+<a name="l03084"></a>03084 <span class="comment">// descriptor.</span>
+<a name="l03085"></a>03085 <a class="code" href="structllvm_1_1SDVTList.html">SDVTList</a> VTs = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a196c23d6cb4d768d037970f1f35bbf66">getVTList</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>);
+<a name="l03086"></a>03086 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LoadFuncPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a35d9b393639fbc9a4e639ce81c704d17" title="Like a regular LOAD but additionally taking/producing a flag.">PPCISD::LOAD</a>, dl, VTs, MTCTROps,
+<a name="l03087"></a>03087 InFlag.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>() ? 3 : 2);
+<a name="l03088"></a>03088 Chain = LoadFuncPtr.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03089"></a>03089 InFlag = LoadFuncPtr.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(2);
+<a name="l03090"></a>03090
+<a name="l03091"></a>03091 <span class="comment">// Load environment pointer into r11.</span>
+<a name="l03092"></a>03092 <span class="comment">// Offset of the environment pointer within the function descriptor.</span>
+<a name="l03093"></a>03093 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(16);
+<a name="l03094"></a>03094
+<a name="l03095"></a>03095 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AddPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, Callee, PtrOff);
+<a name="l03096"></a>03096 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LoadEnvPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a35d9b393639fbc9a4e639ce81c704d17" title="Like a regular LOAD but additionally taking/producing a flag.">PPCISD::LOAD</a>, dl, VTs, Chain, AddPtr,
+<a name="l03097"></a>03097 InFlag);
+<a name="l03098"></a>03098 Chain = LoadEnvPtr.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03099"></a>03099 InFlag = LoadEnvPtr.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(2);
+<a name="l03100"></a>03100
+<a name="l03101"></a>03101 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> EnvVal = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a64720b4e2b3deb1f80177f31d1843691">getCopyToReg</a>(Chain, dl, PPC::X11, LoadEnvPtr,
+<a name="l03102"></a>03102 InFlag);
+<a name="l03103"></a>03103 Chain = EnvVal.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(0);
+<a name="l03104"></a>03104 InFlag = EnvVal.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03105"></a>03105
+<a name="l03106"></a>03106 <span class="comment">// Load TOC of the callee into r2. We are using a target-specific load</span>
+<a name="l03107"></a>03107 <span class="comment">// with r2 hard coded, because the result of a target-independent load</span>
+<a name="l03108"></a>03108 <span class="comment">// would never go directly into r2, since r2 is a reserved register (which</span>
+<a name="l03109"></a>03109 <span class="comment">// prevents the register allocator from allocating it), resulting in an</span>
+<a name="l03110"></a>03110 <span class="comment">// additional register being allocated and an unnecessary move instruction</span>
+<a name="l03111"></a>03111 <span class="comment">// being generated.</span>
+<a name="l03112"></a>03112 VTs = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a196c23d6cb4d768d037970f1f35bbf66">getVTList</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>);
+<a name="l03113"></a>03113 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LoadTOCPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a4a73d0b02b92ec58d7f38d00ad50f289">PPCISD::LOAD_TOC</a>, dl, VTs, Chain,
+<a name="l03114"></a>03114 Callee, InFlag);
+<a name="l03115"></a>03115 Chain = LoadTOCPtr.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(0);
+<a name="l03116"></a>03116 InFlag = LoadTOCPtr.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03117"></a>03117
+<a name="l03118"></a>03118 MTCTROps[0] = Chain;
+<a name="l03119"></a>03119 MTCTROps[1] = LoadFuncPtr;
+<a name="l03120"></a>03120 MTCTROps[2] = InFlag;
+<a name="l03121"></a>03121 }
+<a name="l03122"></a>03122
+<a name="l03123"></a>03123 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aa48a0d892596a0da3cf4a82c6ff5a91f">PPCISD::MTCTR</a>, dl, NodeTys, MTCTROps,
+<a name="l03124"></a>03124 2 + (InFlag.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>() != 0));
+<a name="l03125"></a>03125 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03126"></a>03126
+<a name="l03127"></a>03127 NodeTys.clear();
+<a name="l03128"></a>03128 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>);
+<a name="l03129"></a>03129 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>);
+<a name="l03130"></a>03130 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l03131"></a>03131 CallOpc = isSVR4ABI ? <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66ac9e5a043bcec002240b677d88e122f10">PPCISD::BCTRL_SVR4</a> : <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aaf00be05177a18c604cdafebde41d4ce">PPCISD::BCTRL_Darwin</a>;
+<a name="l03132"></a>03132 Callee.<a class="code" href="classllvm_1_1SDValue.html#ad575e4867727668f7d50952bc9e1a1cd" title="set the SDNode">setNode</a>(0);
+<a name="l03133"></a>03133 <span class="comment">// Add CTR register as callee so a bctr can be emitted later.</span>
+<a name="l03134"></a>03134 <span class="keywordflow">if</span> (isTailCall)
+<a name="l03135"></a>03135 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
+<a name="l03136"></a>03136 }
+<a name="l03137"></a>03137
+<a name="l03138"></a>03138 <span class="comment">// If this is a direct call, pass the chain and the callee.</span>
+<a name="l03139"></a>03139 <span class="keywordflow">if</span> (Callee.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()) {
+<a name="l03140"></a>03140 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l03141"></a>03141 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Callee);
+<a name="l03142"></a>03142 }
+<a name="l03143"></a>03143 <span class="comment">// If this is a tail call add stack pointer delta.</span>
+<a name="l03144"></a>03144 <span class="keywordflow">if</span> (isTailCall)
+<a name="l03145"></a>03145 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(SPDiff, MVT::i32));
+<a name="l03146"></a>03146
+<a name="l03147"></a>03147 <span class="comment">// Add argument registers to the end of the list so that they are known live</span>
+<a name="l03148"></a>03148 <span class="comment">// into the call.</span>
+<a name="l03149"></a>03149 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = RegsToPass.size(); i != e; ++i)
+<a name="l03150"></a>03150 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(RegsToPass[i].first,
+<a name="l03151"></a>03151 RegsToPass[i].second.getValueType()));
+<a name="l03152"></a>03152
+<a name="l03153"></a>03153 <span class="keywordflow">return</span> CallOpc;
+<a name="l03154"></a>03154 }
+<a name="l03155"></a>03155
+<a name="l03156"></a>03156 <span class="keyword">static</span>
+<a name="l03157"></a><a class="code" href="PPCISelLowering_8cpp.html#af8f1aa9eaa10954ed0f91b56e372edd9">03157</a> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#af8f1aa9eaa10954ed0f91b56e372edd9">isLocalCall</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Callee)
+<a name="l03158"></a>03158 {
+<a name="l03159"></a>03159 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1GlobalAddressSDNode.html">GlobalAddressSDNode</a> *G = dyn_cast<GlobalAddressSDNode>(Callee))
+<a name="l03160"></a>03160 <span class="keywordflow">return</span> !G->getGlobal()->isDeclaration() &&
+<a name="l03161"></a>03161 !G->getGlobal()->isWeakForLinker();
+<a name="l03162"></a>03162 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l03163"></a>03163 }
+<a name="l03164"></a>03164
+<a name="l03165"></a>03165 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l03166"></a>03166 PPCTargetLowering::LowerCallResult(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag,
+<a name="l03167"></a>03167 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l03168"></a>03168 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a> &Ins,
+<a name="l03169"></a>03169 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l03170"></a>03170 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l03171"></a>03171
+<a name="l03172"></a>03172 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<CCValAssign, 16></a> RVLocs;
+<a name="l03173"></a>03173 <a class="code" href="classllvm_1_1CCState.html">CCState</a> CCRetInfo(CallConv, isVarArg, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>(),
+<a name="l03174"></a>03174 <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>(), RVLocs, *DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>());
+<a name="l03175"></a>03175 CCRetInfo.<a class="code" href="classllvm_1_1CCState.html#a34218a663a02de9dc2d26a5639f58ebe">AnalyzeCallResult</a>(Ins, RetCC_PPC);
+<a name="l03176"></a>03176
+<a name="l03177"></a>03177 <span class="comment">// Copy all of the result registers out of their specified physreg.</span>
+<a name="l03178"></a>03178 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = RVLocs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i != e; ++i) {
+<a name="l03179"></a>03179 <a class="code" href="classllvm_1_1CCValAssign.html" title="CCValAssign - Represent assignment of one arg/retval to a location.">CCValAssign</a> &VA = RVLocs[i];
+<a name="l03180"></a>03180 assert(VA.<a class="code" href="classllvm_1_1CCValAssign.html#afcfd7d2322b397d0d55a4595dea52e3c">isRegLoc</a>() && <span class="stringliteral">"Can only return in registers!"</span>);
+<a name="l03181"></a>03181
+<a name="l03182"></a>03182 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl,
+<a name="l03183"></a>03183 VA.<a class="code" href="classllvm_1_1CCValAssign.html#a5cb182c203efa2f1fc4797fb76b15daf">getLocReg</a>(), VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae59804b87136d0ddf452a25b025b768c">getLocVT</a>(), InFlag);
+<a name="l03184"></a>03184 Chain = Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03185"></a>03185 InFlag = Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(2);
+<a name="l03186"></a>03186
+<a name="l03187"></a>03187 <span class="keywordflow">switch</span> (VA.<a class="code" href="classllvm_1_1CCValAssign.html#a8c820cdb37337e8b0bd55e0fcd39dd18">getLocInfo</a>()) {
+<a name="l03188"></a>03188 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unknown loc info!"</span>);
+<a name="l03189"></a>03189 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45a8b73d77b9e54663c2e80a48d0917dce1">CCValAssign::Full</a>: <span class="keywordflow">break</span>;
+<a name="l03190"></a>03190 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45acc07b91f72979f3e9b12c2e0c355db46">CCValAssign::AExt</a>:
+<a name="l03191"></a>03191 Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae690127648393001a7d5b93dc23da7b3" title="TRUNCATE - Completely drop the high bits.">ISD::TRUNCATE</a>, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae603fba6e8709cb50d43f38c4305e46b">getValVT</a>(), Val);
+<a name="l03192"></a>03192 <span class="keywordflow">break</span>;
+<a name="l03193"></a>03193 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45a807a4e133d7f743724d809a3f3875aa2">CCValAssign::ZExt</a>:
+<a name="l03194"></a>03194 Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110af23301e60475124fd80a2cb51f6ba863">ISD::AssertZext</a>, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae59804b87136d0ddf452a25b025b768c">getLocVT</a>(), Val,
+<a name="l03195"></a>03195 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ab8ba6b05ad4fa7517f2e23b26f84ae1b">getValueType</a>(VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae603fba6e8709cb50d43f38c4305e46b">getValVT</a>()));
+<a name="l03196"></a>03196 Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae690127648393001a7d5b93dc23da7b3" title="TRUNCATE - Completely drop the high bits.">ISD::TRUNCATE</a>, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae603fba6e8709cb50d43f38c4305e46b">getValVT</a>(), Val);
+<a name="l03197"></a>03197 <span class="keywordflow">break</span>;
+<a name="l03198"></a>03198 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45a7fd25972cdb14499949c7726499e0cb6">CCValAssign::SExt</a>:
+<a name="l03199"></a>03199 Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aee4f13218bdbb5c5697f7e786618ecb2">ISD::AssertSext</a>, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae59804b87136d0ddf452a25b025b768c">getLocVT</a>(), Val,
+<a name="l03200"></a>03200 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ab8ba6b05ad4fa7517f2e23b26f84ae1b">getValueType</a>(VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae603fba6e8709cb50d43f38c4305e46b">getValVT</a>()));
+<a name="l03201"></a>03201 Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae690127648393001a7d5b93dc23da7b3" title="TRUNCATE - Completely drop the high bits.">ISD::TRUNCATE</a>, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae603fba6e8709cb50d43f38c4305e46b">getValVT</a>(), Val);
+<a name="l03202"></a>03202 <span class="keywordflow">break</span>;
+<a name="l03203"></a>03203 }
+<a name="l03204"></a>03204
+<a name="l03205"></a>03205 InVals.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Val);
+<a name="l03206"></a>03206 }
+<a name="l03207"></a>03207
+<a name="l03208"></a>03208 <span class="keywordflow">return</span> Chain;
+<a name="l03209"></a>03209 }
+<a name="l03210"></a>03210
+<a name="l03211"></a>03211 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l03212"></a>03212 PPCTargetLowering::FinishCall(<a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl,
+<a name="l03213"></a>03213 <span class="keywordtype">bool</span> isTailCall, <span class="keywordtype">bool</span> isVarArg,
+<a name="l03214"></a>03214 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l03215"></a>03215 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector</a><std::pair<unsigned, SDValue>, 8>
+<a name="l03216"></a>03216 &RegsToPass,
+<a name="l03217"></a>03217 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l03218"></a>03218 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Callee,
+<a name="l03219"></a>03219 <span class="keywordtype">int</span> SPDiff, <span class="keywordtype">unsigned</span> NumBytes,
+<a name="l03220"></a>03220 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a> &Ins,
+<a name="l03221"></a>03221 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l03222"></a>03222 std::vector<EVT> NodeTys;
+<a name="l03223"></a>03223 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> Ops;
+<a name="l03224"></a>03224 <span class="keywordtype">unsigned</span> CallOpc = <a class="code" href="PPCISelLowering_8cpp.html#af8870998d9445390ad3472c180860a89">PrepareCall</a>(DAG, Callee, InFlag, Chain, dl, SPDiff,
+<a name="l03225"></a>03225 isTailCall, RegsToPass, Ops, NodeTys,
+<a name="l03226"></a>03226 PPCSubTarget);
+<a name="l03227"></a>03227
+<a name="l03228"></a>03228 <span class="comment">// Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls</span>
+<a name="l03229"></a>03229 <span class="keywordflow">if</span> (isVarArg && PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>() && !PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>())
+<a name="l03230"></a>03230 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::CR1EQ, MVT::i32));
+<a name="l03231"></a>03231
+<a name="l03232"></a>03232 <span class="comment">// When performing tail call optimization the callee pops its arguments off</span>
+<a name="l03233"></a>03233 <span class="comment">// the stack. Account for this here so these bytes can be pushed back on in</span>
+<a name="l03234"></a>03234 <span class="comment">// PPCRegisterInfo::eliminateCallFramePseudoInstr.</span>
+<a name="l03235"></a>03235 <span class="keywordtype">int</span> BytesCalleePops =
+<a name="l03236"></a>03236 (CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a> &&
+<a name="l03237"></a>03237 <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ab1fb67187fc37e569cc5171cbebba873">Options</a>.<a class="code" href="classllvm_1_1TargetOptions.html#ad54fc81a4ef7ab96137a9b6e78fdf838">GuaranteedTailCallOpt</a>) ? NumBytes : 0;
+<a name="l03238"></a>03238
+<a name="l03239"></a>03239 <span class="comment">// Add a register mask operand representing the call-preserved registers.</span>
+<a name="l03240"></a>03240 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI = <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a70b47eca6a99c87b81f4c1b1455dc090">getRegisterInfo</a>();
+<a name="l03241"></a>03241 <span class="keyword">const</span> uint32_t *Mask = TRI-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#abbdc1cffc65c3d42ac4c8f5003679071">getCallPreservedMask</a>(CallConv);
+<a name="l03242"></a>03242 assert(Mask && <span class="stringliteral">"Missing call preserved mask for calling convention"</span>);
+<a name="l03243"></a>03243 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acfe1250a2214797a59c6457dd2180df9">getRegisterMask</a>(Mask));
+<a name="l03244"></a>03244
+<a name="l03245"></a>03245 <span class="keywordflow">if</span> (InFlag.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>())
+<a name="l03246"></a>03246 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(InFlag);
+<a name="l03247"></a>03247
+<a name="l03248"></a>03248 <span class="comment">// Emit tail call.</span>
+<a name="l03249"></a>03249 <span class="keywordflow">if</span> (isTailCall) {
+<a name="l03250"></a>03250 <span class="comment">// If this is the first return lowered for this function, add the regs</span>
+<a name="l03251"></a>03251 <span class="comment">// to the liveout set for the function.</span>
+<a name="l03252"></a>03252 <span class="keywordflow">if</span> (DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a60f6bf9d77fabdbf75998d1ecd9ee4ac">liveout_empty</a>()) {
+<a name="l03253"></a>03253 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<CCValAssign, 16></a> RVLocs;
+<a name="l03254"></a>03254 <a class="code" href="classllvm_1_1CCState.html">CCState</a> CCInfo(CallConv, isVarArg, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>(),
+<a name="l03255"></a>03255 <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>(), RVLocs, *DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>());
+<a name="l03256"></a>03256 CCInfo.<a class="code" href="classllvm_1_1CCState.html#a34218a663a02de9dc2d26a5639f58ebe">AnalyzeCallResult</a>(Ins, RetCC_PPC);
+<a name="l03257"></a>03257 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != RVLocs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); ++i)
+<a name="l03258"></a>03258 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#ad01a8efb5445cb8b6cdd1a4196b54b67">addLiveOut</a>(RVLocs[i].getLocReg());
+<a name="l03259"></a>03259 }
+<a name="l03260"></a>03260
+<a name="l03261"></a>03261 assert(((Callee.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a419e8283a58d2b1b86591fa7f18ccfd9">ISD::Register</a> &&
+<a name="l03262"></a>03262 cast<RegisterSDNode>(Callee)-><a class="code" href="MipsDisassembler_8cpp.html#a30bccd0ebacd9892c243f7bd520e4aa0">getReg</a>() == PPC::CTR) ||
+<a name="l03263"></a>03263 Callee.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a59b314018a929255951f01f8daaae72f">ISD::TargetExternalSymbol</a> ||
+<a name="l03264"></a>03264 Callee.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a> ||
+<a name="l03265"></a>03265 isa<ConstantSDNode>(Callee)) &&
+<a name="l03266"></a>03266 <span class="stringliteral">"Expecting an global address, external symbol, absolute value or register"</span>);
+<a name="l03267"></a>03267
+<a name="l03268"></a>03268 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aa4dc9f480c199614ca9475c7969ead06">PPCISD::TC_RETURN</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, &Ops[0], Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l03269"></a>03269 }
+<a name="l03270"></a>03270
+<a name="l03271"></a>03271 <span class="comment">// Add a NOP immediately after the branch instruction when using the 64-bit</span>
+<a name="l03272"></a>03272 <span class="comment">// SVR4 ABI. At link time, if caller and callee are in a different module and</span>
+<a name="l03273"></a>03273 <span class="comment">// thus have a different TOC, the call will be replaced with a call to a stub</span>
+<a name="l03274"></a>03274 <span class="comment">// function which saves the current TOC, loads the TOC of the callee and</span>
+<a name="l03275"></a>03275 <span class="comment">// branches to the callee. The NOP will be replaced with a load instruction</span>
+<a name="l03276"></a>03276 <span class="comment">// which restores the TOC of the caller from the TOC save slot of the current</span>
+<a name="l03277"></a>03277 <span class="comment">// stack frame. If caller and callee belong to the same module (and have the</span>
+<a name="l03278"></a>03278 <span class="comment">// same TOC), the NOP will remain unchanged.</span>
+<a name="l03279"></a>03279
+<a name="l03280"></a>03280 <span class="keywordtype">bool</span> needsTOCRestore = <span class="keyword">false</span>;
+<a name="l03281"></a>03281 <span class="keywordflow">if</span> (!isTailCall && PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>()&& PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>()) {
+<a name="l03282"></a>03282 <span class="keywordflow">if</span> (CallOpc == <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66ac9e5a043bcec002240b677d88e122f10">PPCISD::BCTRL_SVR4</a>) {
+<a name="l03283"></a>03283 <span class="comment">// This is a call through a function pointer.</span>
+<a name="l03284"></a>03284 <span class="comment">// Restore the caller TOC from the save area into R2.</span>
+<a name="l03285"></a>03285 <span class="comment">// See PrepareCall() for more information about calls through function</span>
+<a name="l03286"></a>03286 <span class="comment">// pointers in the 64-bit SVR4 ABI.</span>
+<a name="l03287"></a>03287 <span class="comment">// We are using a target-specific load with r2 hard coded, because the</span>
+<a name="l03288"></a>03288 <span class="comment">// result of a target-independent load would never go directly into r2,</span>
+<a name="l03289"></a>03289 <span class="comment">// since r2 is a reserved register (which prevents the register allocator</span>
+<a name="l03290"></a>03290 <span class="comment">// from allocating it), resulting in an additional register being</span>
+<a name="l03291"></a>03291 <span class="comment">// allocated and an unnecessary move instruction being generated.</span>
+<a name="l03292"></a>03292 needsTOCRestore = <span class="keyword">true</span>;
+<a name="l03293"></a>03293 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> ((CallOpc == <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66acf9dfc83dc60a6e978bde88a5f43c10c">PPCISD::CALL_SVR4</a>) && !<a class="code" href="PPCISelLowering_8cpp.html#af8f1aa9eaa10954ed0f91b56e372edd9">isLocalCall</a>(Callee)) {
+<a name="l03294"></a>03294 <span class="comment">// Otherwise insert NOP for non-local calls.</span>
+<a name="l03295"></a>03295 CallOpc = <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2835b483522c86e3f126ca118152d55d">PPCISD::CALL_NOP_SVR4</a>;
+<a name="l03296"></a>03296 }
+<a name="l03297"></a>03297 }
+<a name="l03298"></a>03298
+<a name="l03299"></a>03299 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(CallOpc, dl, NodeTys, &Ops[0], Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l03300"></a>03300 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03301"></a>03301
+<a name="l03302"></a>03302 <span class="keywordflow">if</span> (needsTOCRestore) {
+<a name="l03303"></a>03303 <a class="code" href="structllvm_1_1SDVTList.html">SDVTList</a> VTs = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a196c23d6cb4d768d037970f1f35bbf66">getVTList</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>);
+<a name="l03304"></a>03304 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66ab791c435016d75f72e1e95c54f3d42d9">PPCISD::TOC_RESTORE</a>, dl, VTs, Chain, InFlag);
+<a name="l03305"></a>03305 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03306"></a>03306 }
+<a name="l03307"></a>03307
+<a name="l03308"></a>03308 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a68ec943fbadc65f413d9cf63a501f70c">getCALLSEQ_END</a>(Chain, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(NumBytes, <span class="keyword">true</span>),
+<a name="l03309"></a>03309 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(BytesCalleePops, <span class="keyword">true</span>),
+<a name="l03310"></a>03310 InFlag);
+<a name="l03311"></a>03311 <span class="keywordflow">if</span> (!Ins.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l03312"></a>03312 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03313"></a>03313
+<a name="l03314"></a>03314 <span class="keywordflow">return</span> LowerCallResult(Chain, InFlag, CallConv, isVarArg,
+<a name="l03315"></a>03315 Ins, dl, DAG, InVals);
+<a name="l03316"></a>03316 }
+<a name="l03317"></a>03317
+<a name="l03318"></a>03318 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l03319"></a>03319 PPCTargetLowering::LowerCall(<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html">TargetLowering::CallLoweringInfo</a> &CLI,
+<a name="l03320"></a>03320 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l03321"></a>03321 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#ae76ac9826f02f95aae34e845ac110244">DAG</a>;
+<a name="l03322"></a>03322 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> &dl = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#a1a282f7af8d0e0a3f8ae1444c5071f94">DL</a>;
+<a name="l03323"></a>03323 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<ISD::OutputArg, 32></a> &Outs = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#ad07ce660c9cb208ae98a53ad8b3ce1de">Outs</a>;
+<a name="l03324"></a>03324 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 32></a> &OutVals = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#adba9c4dde08bb0a9de1c99e7e039d8a0">OutVals</a>;
+<a name="l03325"></a>03325 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<ISD::InputArg, 32></a> &Ins = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#a423dda4ff918d4145ccc1861f059f940">Ins</a>;
+<a name="l03326"></a>03326 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#aa4872f31b8be67e8a1998454db0766bd">Chain</a>;
+<a name="l03327"></a>03327 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Callee = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#a31faa4803c937d756c28947a070c6c2e">Callee</a>;
+<a name="l03328"></a>03328 <span class="keywordtype">bool</span> &isTailCall = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#a283b7df55a414e3185b56aeea1ec7ee7">IsTailCall</a>;
+<a name="l03329"></a>03329 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#ae47a430364102f6e179d49cb3411b955">CallConv</a>;
+<a name="l03330"></a>03330 <span class="keywordtype">bool</span> isVarArg = CLI.<a class="code" href="structllvm_1_1TargetLowering_1_1CallLoweringInfo.html#a3eb6e80dc80f35553ccc33a89d691df8">IsVarArg</a>;
+<a name="l03331"></a>03331
+<a name="l03332"></a>03332 <span class="keywordflow">if</span> (isTailCall)
+<a name="l03333"></a>03333 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
+<a name="l03334"></a>03334 Ins, DAG);
+<a name="l03335"></a>03335
+<a name="l03336"></a>03336 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>()) {
+<a name="l03337"></a>03337 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>())
+<a name="l03338"></a>03338 <span class="keywordflow">return</span> LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
+<a name="l03339"></a>03339 isTailCall, Outs, OutVals, Ins,
+<a name="l03340"></a>03340 dl, DAG, InVals);
+<a name="l03341"></a>03341 <span class="keywordflow">else</span>
+<a name="l03342"></a>03342 <span class="keywordflow">return</span> LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
+<a name="l03343"></a>03343 isTailCall, Outs, OutVals, Ins,
+<a name="l03344"></a>03344 dl, DAG, InVals);
+<a name="l03345"></a>03345 }
+<a name="l03346"></a>03346
+<a name="l03347"></a>03347 <span class="keywordflow">return</span> LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
+<a name="l03348"></a>03348 isTailCall, Outs, OutVals, Ins,
+<a name="l03349"></a>03349 dl, DAG, InVals);
+<a name="l03350"></a>03350 }
+<a name="l03351"></a>03351
+<a name="l03352"></a>03352 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l03353"></a>03353 PPCTargetLowering::LowerCall_32SVR4(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Callee,
+<a name="l03354"></a>03354 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l03355"></a>03355 <span class="keywordtype">bool</span> isTailCall,
+<a name="l03356"></a>03356 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::OutputArg></a> &Outs,
+<a name="l03357"></a>03357 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &OutVals,
+<a name="l03358"></a>03358 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a> &Ins,
+<a name="l03359"></a>03359 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l03360"></a>03360 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l03361"></a>03361 <span class="comment">// See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description</span>
+<a name="l03362"></a>03362 <span class="comment">// of the 32-bit SVR4 ABI stack frame layout.</span>
+<a name="l03363"></a>03363
+<a name="l03364"></a>03364 assert((CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">CallingConv::C</a> ||
+<a name="l03365"></a>03365 CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a>) && <span class="stringliteral">"Unknown calling convention!"</span>);
+<a name="l03366"></a>03366
+<a name="l03367"></a>03367 <span class="keywordtype">unsigned</span> PtrByteSize = 4;
+<a name="l03368"></a>03368
+<a name="l03369"></a>03369 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l03370"></a>03370
+<a name="l03371"></a>03371 <span class="comment">// Mark this function as potentially containing a function that contains a</span>
+<a name="l03372"></a>03372 <span class="comment">// tail call. As a consequence the frame pointer will be used for dynamicalloc</span>
+<a name="l03373"></a>03373 <span class="comment">// and restoring the callers stack pointer in this functions epilog. This is</span>
+<a name="l03374"></a>03374 <span class="comment">// done because by tail calling the called function might overwrite the value</span>
+<a name="l03375"></a>03375 <span class="comment">// in this function's (MF) stack pointer stack slot 0(SP).</span>
+<a name="l03376"></a>03376 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().Options.GuaranteedTailCallOpt &&
+<a name="l03377"></a>03377 CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a>)
+<a name="l03378"></a>03378 MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>()->setHasFastCall();
+<a name="l03379"></a>03379
+<a name="l03380"></a>03380 <span class="comment">// Count how many bytes are to be pushed on the stack, including the linkage</span>
+<a name="l03381"></a>03381 <span class="comment">// area, parameter list area and the part of the local variable space which</span>
+<a name="l03382"></a>03382 <span class="comment">// contains copies of aggregates which are passed by value.</span>
+<a name="l03383"></a>03383
+<a name="l03384"></a>03384 <span class="comment">// Assign locations to all of the outgoing arguments.</span>
+<a name="l03385"></a>03385 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<CCValAssign, 16></a> ArgLocs;
+<a name="l03386"></a>03386 <a class="code" href="classllvm_1_1CCState.html">CCState</a> CCInfo(CallConv, isVarArg, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>(),
+<a name="l03387"></a>03387 <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>(), ArgLocs, *DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>());
+<a name="l03388"></a>03388
+<a name="l03389"></a>03389 <span class="comment">// Reserve space for the linkage area on the stack.</span>
+<a name="l03390"></a>03390 CCInfo.<a class="code" href="classllvm_1_1CCState.html#accd683afb417ec1f0f44c62c8b5a8fc4">AllocateStack</a>(<a class="code" href="classllvm_1_1PPCFrameLowering.html#ab90d8608756fd53ed946d0eab8ad6cb7">PPCFrameLowering::getLinkageSize</a>(<span class="keyword">false</span>, <span class="keyword">false</span>), PtrByteSize);
+<a name="l03391"></a>03391
+<a name="l03392"></a>03392 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l03393"></a>03393 <span class="comment">// Handle fixed and variable vector arguments differently.</span>
+<a name="l03394"></a>03394 <span class="comment">// Fixed vector arguments go into registers as long as registers are</span>
+<a name="l03395"></a>03395 <span class="comment">// available. Variable vector arguments always go into memory.</span>
+<a name="l03396"></a>03396 <span class="keywordtype">unsigned</span> NumArgs = Outs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>();
+<a name="l03397"></a>03397
+<a name="l03398"></a>03398 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != NumArgs; ++i) {
+<a name="l03399"></a>03399 <a class="code" href="classllvm_1_1MVT.html">MVT</a> ArgVT = Outs[i].VT;
+<a name="l03400"></a>03400 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> ArgFlags = Outs[i].Flags;
+<a name="l03401"></a>03401 <span class="keywordtype">bool</span> Result;
+<a name="l03402"></a>03402
+<a name="l03403"></a>03403 <span class="keywordflow">if</span> (Outs[i].IsFixed) {
+<a name="l03404"></a>03404 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45a8b73d77b9e54663c2e80a48d0917dce1">CCValAssign::Full</a>, ArgFlags,
+<a name="l03405"></a>03405 CCInfo);
+<a name="l03406"></a>03406 } <span class="keywordflow">else</span> {
+<a name="l03407"></a>03407 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45a8b73d77b9e54663c2e80a48d0917dce1">CCValAssign::Full</a>,
+<a name="l03408"></a>03408 ArgFlags, CCInfo);
+<a name="l03409"></a>03409 }
+<a name="l03410"></a>03410
+<a name="l03411"></a>03411 <span class="keywordflow">if</span> (Result) {
+<a name="l03412"></a>03412 <span class="preprocessor">#ifndef NDEBUG</span>
+<a name="l03413"></a>03413 <span class="preprocessor"></span> <a class="code" href="namespacellvm.html#ab8e34eca3b0817ef7a127913fbf6d9e4">errs</a>() << <span class="stringliteral">"Call operand #"</span> << i << <span class="stringliteral">" has unhandled type "</span>
+<a name="l03414"></a>03414 << <a class="code" href="structllvm_1_1EVT.html">EVT</a>(ArgVT).<a class="code" href="structllvm_1_1EVT.html#a840a2d72e6d1e7ec1c938ffd9f023c68">getEVTString</a>() << <span class="stringliteral">"\n"</span>;
+<a name="l03415"></a>03415 <span class="preprocessor">#endif</span>
+<a name="l03416"></a>03416 <span class="preprocessor"></span> <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(0);
+<a name="l03417"></a>03417 }
+<a name="l03418"></a>03418 }
+<a name="l03419"></a>03419 } <span class="keywordflow">else</span> {
+<a name="l03420"></a>03420 <span class="comment">// All arguments are treated the same.</span>
+<a name="l03421"></a>03421 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
+<a name="l03422"></a>03422 }
+<a name="l03423"></a>03423
+<a name="l03424"></a>03424 <span class="comment">// Assign locations to all of the outgoing aggregate by value arguments.</span>
+<a name="l03425"></a>03425 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<CCValAssign, 16></a> ByValArgLocs;
+<a name="l03426"></a>03426 <a class="code" href="classllvm_1_1CCState.html">CCState</a> CCByValInfo(CallConv, isVarArg, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>(),
+<a name="l03427"></a>03427 <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>(), ByValArgLocs, *DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>());
+<a name="l03428"></a>03428
+<a name="l03429"></a>03429 <span class="comment">// Reserve stack space for the allocations in CCInfo.</span>
+<a name="l03430"></a>03430 CCByValInfo.<a class="code" href="classllvm_1_1CCState.html#accd683afb417ec1f0f44c62c8b5a8fc4">AllocateStack</a>(CCInfo.getNextStackOffset(), PtrByteSize);
+<a name="l03431"></a>03431
+<a name="l03432"></a>03432 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
+<a name="l03433"></a>03433
+<a name="l03434"></a>03434 <span class="comment">// Size of the linkage area, parameter list area and the part of the local</span>
+<a name="l03435"></a>03435 <span class="comment">// space variable where copies of aggregates which are passed by value are</span>
+<a name="l03436"></a>03436 <span class="comment">// stored.</span>
+<a name="l03437"></a>03437 <span class="keywordtype">unsigned</span> NumBytes = CCByValInfo.getNextStackOffset();
+<a name="l03438"></a>03438
+<a name="l03439"></a>03439 <span class="comment">// Calculate by how many bytes the stack has to be adjusted in case of tail</span>
+<a name="l03440"></a>03440 <span class="comment">// call optimization.</span>
+<a name="l03441"></a>03441 <span class="keywordtype">int</span> SPDiff = <a class="code" href="PPCISelLowering_8cpp.html#aaf0bcfcb9ee7e078bec6074304e31cb0">CalculateTailCallSPDiff</a>(DAG, isTailCall, NumBytes);
+<a name="l03442"></a>03442
+<a name="l03443"></a>03443 <span class="comment">// Adjust the stack pointer for the new arguments...</span>
+<a name="l03444"></a>03444 <span class="comment">// These operations are automatically eliminated by the prolog/epilog pass</span>
+<a name="l03445"></a>03445 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#aa3b147eb51c574c8d7149855e4a9dfc2">getCALLSEQ_START</a>(Chain, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(NumBytes, <span class="keyword">true</span>));
+<a name="l03446"></a>03446 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CallSeqStart = Chain;
+<a name="l03447"></a>03447
+<a name="l03448"></a>03448 <span class="comment">// Load the return address and frame pointer so it can be moved somewhere else</span>
+<a name="l03449"></a>03449 <span class="comment">// later.</span>
+<a name="l03450"></a>03450 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LROp, FPOp;
+<a name="l03451"></a>03451 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, <span class="keyword">false</span>,
+<a name="l03452"></a>03452 dl);
+<a name="l03453"></a>03453
+<a name="l03454"></a>03454 <span class="comment">// Set up a copy of the stack pointer for use loading and storing any</span>
+<a name="l03455"></a>03455 <span class="comment">// arguments that may not fit in the registers available for argument</span>
+<a name="l03456"></a>03456 <span class="comment">// passing.</span>
+<a name="l03457"></a>03457 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> StackPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::R1, MVT::i32);
+<a name="l03458"></a>03458
+<a name="l03459"></a>03459 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<std::pair<unsigned, SDValue></a>, 8> RegsToPass;
+<a name="l03460"></a>03460 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<TailCallArgumentInfo, 8></a> TailCallArguments;
+<a name="l03461"></a>03461 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> MemOpChains;
+<a name="l03462"></a>03462
+<a name="l03463"></a>03463 <span class="keywordtype">bool</span> seenFloatArg = <span class="keyword">false</span>;
+<a name="l03464"></a>03464 <span class="comment">// Walk the register/memloc assignments, inserting copies/loads.</span>
+<a name="l03465"></a>03465 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, j = 0, e = ArgLocs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>();
+<a name="l03466"></a>03466 i != e;
+<a name="l03467"></a>03467 ++i) {
+<a name="l03468"></a>03468 <a class="code" href="classllvm_1_1CCValAssign.html" title="CCValAssign - Represent assignment of one arg/retval to a location.">CCValAssign</a> &VA = ArgLocs[i];
+<a name="l03469"></a>03469 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg = OutVals[i];
+<a name="l03470"></a>03470 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags = Outs[i].Flags;
+<a name="l03471"></a>03471
+<a name="l03472"></a>03472 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a34ee642bf0fb623f775e04e0e60d9b26">isByVal</a>()) {
+<a name="l03473"></a>03473 <span class="comment">// Argument is an aggregate which is passed by value, thus we need to</span>
+<a name="l03474"></a>03474 <span class="comment">// create a copy of it in the local variable space of the current stack</span>
+<a name="l03475"></a>03475 <span class="comment">// frame (which is the stack frame of the caller) and pass the address of</span>
+<a name="l03476"></a>03476 <span class="comment">// this copy to the callee.</span>
+<a name="l03477"></a>03477 assert((j < ByValArgLocs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>()) && <span class="stringliteral">"Index out of bounds!"</span>);
+<a name="l03478"></a>03478 <a class="code" href="classllvm_1_1CCValAssign.html" title="CCValAssign - Represent assignment of one arg/retval to a location.">CCValAssign</a> &ByValVA = ByValArgLocs[j++];
+<a name="l03479"></a>03479 assert((VA.<a class="code" href="classllvm_1_1CCValAssign.html#a96511fb80d3f05f6f95530002bd4b6a8">getValNo</a>() == ByValVA.<a class="code" href="classllvm_1_1CCValAssign.html#a96511fb80d3f05f6f95530002bd4b6a8">getValNo</a>()) && <span class="stringliteral">"ValNo mismatch!"</span>);
+<a name="l03480"></a>03480
+<a name="l03481"></a>03481 <span class="comment">// Memory reserved in the local variable space of the callers stack frame.</span>
+<a name="l03482"></a>03482 <span class="keywordtype">unsigned</span> LocMemOffset = ByValVA.<a class="code" href="classllvm_1_1CCValAssign.html#a7b19fa41486ca39142442dd962c8d3b6">getLocMemOffset</a>();
+<a name="l03483"></a>03483
+<a name="l03484"></a>03484 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(LocMemOffset);
+<a name="l03485"></a>03485 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, <a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>(), StackPtr, PtrOff);
+<a name="l03486"></a>03486
+<a name="l03487"></a>03487 <span class="comment">// Create a copy of the argument in the local area of the current</span>
+<a name="l03488"></a>03488 <span class="comment">// stack frame.</span>
+<a name="l03489"></a>03489 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MemcpyCall =
+<a name="l03490"></a>03490 <a class="code" href="PPCISelLowering_8cpp.html#a9af2525638d1b14080afae2d307a0dce">CreateCopyOfByValArgument</a>(Arg, PtrOff,
+<a name="l03491"></a>03491 CallSeqStart.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0),
+<a name="l03492"></a>03492 Flags, DAG, dl);
+<a name="l03493"></a>03493
+<a name="l03494"></a>03494 <span class="comment">// This must go outside the CALLSEQ_START..END.</span>
+<a name="l03495"></a>03495 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
+<a name="l03496"></a>03496 CallSeqStart.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1));
+<a name="l03497"></a>03497 DAG.ReplaceAllUsesWith(CallSeqStart.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(),
+<a name="l03498"></a>03498 NewCallSeqStart.getNode());
+<a name="l03499"></a>03499 Chain = CallSeqStart = NewCallSeqStart;
+<a name="l03500"></a>03500
+<a name="l03501"></a>03501 <span class="comment">// Pass the address of the aggregate copy on the stack either in a</span>
+<a name="l03502"></a>03502 <span class="comment">// physical register or in the parameter list area of the current stack</span>
+<a name="l03503"></a>03503 <span class="comment">// frame to the callee.</span>
+<a name="l03504"></a>03504 Arg = PtrOff;
+<a name="l03505"></a>03505 }
+<a name="l03506"></a>03506
+<a name="l03507"></a>03507 <span class="keywordflow">if</span> (VA.<a class="code" href="classllvm_1_1CCValAssign.html#afcfd7d2322b397d0d55a4595dea52e3c">isRegLoc</a>()) {
+<a name="l03508"></a>03508 seenFloatArg |= VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae59804b87136d0ddf452a25b025b768c">getLocVT</a>().<a class="code" href="classllvm_1_1MVT.html#ab1311d6d51755d404adc348ad4aeaaad" title="isFloatingPoint - Return true if this is a FP, or a vector FP type.">isFloatingPoint</a>();
+<a name="l03509"></a>03509 <span class="comment">// Put argument in a physical register.</span>
+<a name="l03510"></a>03510 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(VA.<a class="code" href="classllvm_1_1CCValAssign.html#a5cb182c203efa2f1fc4797fb76b15daf">getLocReg</a>(), Arg));
+<a name="l03511"></a>03511 } <span class="keywordflow">else</span> {
+<a name="l03512"></a>03512 <span class="comment">// Put argument in the parameter list area of the current stack frame.</span>
+<a name="l03513"></a>03513 assert(VA.<a class="code" href="classllvm_1_1CCValAssign.html#a5b5b7a20dd6b367935d4f44744ab6e08">isMemLoc</a>());
+<a name="l03514"></a>03514 <span class="keywordtype">unsigned</span> LocMemOffset = VA.<a class="code" href="classllvm_1_1CCValAssign.html#a7b19fa41486ca39142442dd962c8d3b6">getLocMemOffset</a>();
+<a name="l03515"></a>03515
+<a name="l03516"></a>03516 <span class="keywordflow">if</span> (!isTailCall) {
+<a name="l03517"></a>03517 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff = DAG.getIntPtrConstant(LocMemOffset);
+<a name="l03518"></a>03518 PtrOff = DAG.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, <a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>(), StackPtr, PtrOff);
+<a name="l03519"></a>03519
+<a name="l03520"></a>03520 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.getStore(Chain, dl, Arg, PtrOff,
+<a name="l03521"></a>03521 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l03522"></a>03522 <span class="keyword">false</span>, <span class="keyword">false</span>, 0));
+<a name="l03523"></a>03523 } <span class="keywordflow">else</span> {
+<a name="l03524"></a>03524 <span class="comment">// Calculate and remember argument location.</span>
+<a name="l03525"></a>03525 <a class="code" href="PPCISelLowering_8cpp.html#acbd75cbe0914841fc7e59e69bb8d1654">CalculateTailCallArgDest</a>(DAG, MF, <span class="keyword">false</span>, Arg, SPDiff, LocMemOffset,
+<a name="l03526"></a>03526 TailCallArguments);
+<a name="l03527"></a>03527 }
+<a name="l03528"></a>03528 }
+<a name="l03529"></a>03529 }
+<a name="l03530"></a>03530
+<a name="l03531"></a>03531 <span class="keywordflow">if</span> (!MemOpChains.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l03532"></a>03532 Chain = DAG.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad469508535ce2082a1ab1f0e429187b8">ISD::TokenFactor</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>,
+<a name="l03533"></a>03533 &MemOpChains[0], MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l03534"></a>03534
+<a name="l03535"></a>03535 <span class="comment">// Build a sequence of copy-to-reg nodes chained together with token chain</span>
+<a name="l03536"></a>03536 <span class="comment">// and flag operands which copy the outgoing args into the appropriate regs.</span>
+<a name="l03537"></a>03537 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag;
+<a name="l03538"></a>03538 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i != e; ++i) {
+<a name="l03539"></a>03539 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
+<a name="l03540"></a>03540 RegsToPass[i].second, InFlag);
+<a name="l03541"></a>03541 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03542"></a>03542 }
+<a name="l03543"></a>03543
+<a name="l03544"></a>03544 <span class="comment">// Set CR bit 6 to true if this is a vararg call with floating args passed in</span>
+<a name="l03545"></a>03545 <span class="comment">// registers.</span>
+<a name="l03546"></a>03546 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l03547"></a>03547 <a class="code" href="structllvm_1_1SDVTList.html">SDVTList</a> VTs = DAG.getVTList(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>);
+<a name="l03548"></a>03548 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Chain, InFlag };
+<a name="l03549"></a>03549
+<a name="l03550"></a>03550 Chain = DAG.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(seenFloatArg ? <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a7fa84f3807a868c9e48e0928e3ac7f81" title="ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls">PPCISD::CR6SET</a> : <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a0a616f27a6f2de704ab3ed849b50b181">PPCISD::CR6UNSET</a>,
+<a name="l03551"></a>03551 dl, VTs, Ops, InFlag.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>() ? 2 : 1);
+<a name="l03552"></a>03552
+<a name="l03553"></a>03553 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03554"></a>03554 }
+<a name="l03555"></a>03555
+<a name="l03556"></a>03556 <span class="keywordflow">if</span> (isTailCall)
+<a name="l03557"></a>03557 <a class="code" href="PPCISelLowering_8cpp.html#a6e0cf06aedc5ad75745f3834560a71a6">PrepareTailCall</a>(DAG, InFlag, Chain, dl, <span class="keyword">false</span>, SPDiff, NumBytes, LROp, FPOp,
+<a name="l03558"></a>03558 <span class="keyword">false</span>, TailCallArguments);
+<a name="l03559"></a>03559
+<a name="l03560"></a>03560 <span class="keywordflow">return</span> FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
+<a name="l03561"></a>03561 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
+<a name="l03562"></a>03562 Ins, InVals);
+<a name="l03563"></a>03563 }
+<a name="l03564"></a>03564
+<a name="l03565"></a>03565 <span class="comment">// Copy an argument into memory, being careful to do this outside the</span>
+<a name="l03566"></a>03566 <span class="comment">// call sequence for the call to which the argument belongs.</span>
+<a name="l03567"></a>03567 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l03568"></a>03568 PPCTargetLowering::createMemcpyOutsideCallSeq(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff,
+<a name="l03569"></a>03569 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CallSeqStart,
+<a name="l03570"></a>03570 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags,
+<a name="l03571"></a>03571 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l03572"></a>03572 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl)<span class="keyword"> const </span>{
+<a name="l03573"></a>03573 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MemcpyCall = <a class="code" href="PPCISelLowering_8cpp.html#a9af2525638d1b14080afae2d307a0dce">CreateCopyOfByValArgument</a>(Arg, PtrOff,
+<a name="l03574"></a>03574 CallSeqStart.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0),
+<a name="l03575"></a>03575 Flags, DAG, dl);
+<a name="l03576"></a>03576 <span class="comment">// The MEMCPY must go outside the CALLSEQ_START..END.</span>
+<a name="l03577"></a>03577 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
+<a name="l03578"></a>03578 CallSeqStart.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1));
+<a name="l03579"></a>03579 DAG.ReplaceAllUsesWith(CallSeqStart.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(),
+<a name="l03580"></a>03580 NewCallSeqStart.getNode());
+<a name="l03581"></a>03581 <span class="keywordflow">return</span> NewCallSeqStart;
+<a name="l03582"></a>03582 }
+<a name="l03583"></a>03583
+<a name="l03584"></a>03584 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l03585"></a>03585 PPCTargetLowering::LowerCall_64SVR4(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Callee,
+<a name="l03586"></a>03586 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l03587"></a>03587 <span class="keywordtype">bool</span> isTailCall,
+<a name="l03588"></a>03588 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::OutputArg></a> &Outs,
+<a name="l03589"></a>03589 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &OutVals,
+<a name="l03590"></a>03590 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a> &Ins,
+<a name="l03591"></a>03591 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l03592"></a>03592 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l03593"></a>03593
+<a name="l03594"></a>03594 <span class="keywordtype">unsigned</span> NumOps = Outs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>();
+<a name="l03595"></a>03595
+<a name="l03596"></a>03596 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l03597"></a>03597 <span class="keywordtype">unsigned</span> PtrByteSize = 8;
+<a name="l03598"></a>03598
+<a name="l03599"></a>03599 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l03600"></a>03600
+<a name="l03601"></a>03601 <span class="comment">// Mark this function as potentially containing a function that contains a</span>
+<a name="l03602"></a>03602 <span class="comment">// tail call. As a consequence the frame pointer will be used for dynamicalloc</span>
+<a name="l03603"></a>03603 <span class="comment">// and restoring the callers stack pointer in this functions epilog. This is</span>
+<a name="l03604"></a>03604 <span class="comment">// done because by tail calling the called function might overwrite the value</span>
+<a name="l03605"></a>03605 <span class="comment">// in this function's (MF) stack pointer stack slot 0(SP).</span>
+<a name="l03606"></a>03606 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().Options.GuaranteedTailCallOpt &&
+<a name="l03607"></a>03607 CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a>)
+<a name="l03608"></a>03608 MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>()->setHasFastCall();
+<a name="l03609"></a>03609
+<a name="l03610"></a>03610 <span class="keywordtype">unsigned</span> nAltivecParamsAtEnd = 0;
+<a name="l03611"></a>03611
+<a name="l03612"></a>03612 <span class="comment">// Count how many bytes are to be pushed on the stack, including the linkage</span>
+<a name="l03613"></a>03613 <span class="comment">// area, and parameter passing area. We start with at least 48 bytes, which</span>
+<a name="l03614"></a>03614 <span class="comment">// is reserved space for [SP][CR][LR][3 x unused].</span>
+<a name="l03615"></a>03615 <span class="comment">// NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result</span>
+<a name="l03616"></a>03616 <span class="comment">// of this call.</span>
+<a name="l03617"></a>03617 <span class="keywordtype">unsigned</span> NumBytes =
+<a name="l03618"></a>03618 <a class="code" href="PPCISelLowering_8cpp.html#a3c31aec5751525d6fd2c9a3c7916b637">CalculateParameterAndLinkageAreaSize</a>(DAG, <span class="keyword">true</span>, isVarArg, CallConv,
+<a name="l03619"></a>03619 Outs, OutVals, nAltivecParamsAtEnd);
+<a name="l03620"></a>03620
+<a name="l03621"></a>03621 <span class="comment">// Calculate by how many bytes the stack has to be adjusted in case of tail</span>
+<a name="l03622"></a>03622 <span class="comment">// call optimization.</span>
+<a name="l03623"></a>03623 <span class="keywordtype">int</span> SPDiff = <a class="code" href="PPCISelLowering_8cpp.html#aaf0bcfcb9ee7e078bec6074304e31cb0">CalculateTailCallSPDiff</a>(DAG, isTailCall, NumBytes);
+<a name="l03624"></a>03624
+<a name="l03625"></a>03625 <span class="comment">// To protect arguments on the stack from being clobbered in a tail call,</span>
+<a name="l03626"></a>03626 <span class="comment">// force all the loads to happen before doing any other lowering.</span>
+<a name="l03627"></a>03627 <span class="keywordflow">if</span> (isTailCall)
+<a name="l03628"></a>03628 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a1487d4dfd14eebe24447f52b04bb8f6f">getStackArgumentTokenFactor</a>(Chain);
+<a name="l03629"></a>03629
+<a name="l03630"></a>03630 <span class="comment">// Adjust the stack pointer for the new arguments...</span>
+<a name="l03631"></a>03631 <span class="comment">// These operations are automatically eliminated by the prolog/epilog pass</span>
+<a name="l03632"></a>03632 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#aa3b147eb51c574c8d7149855e4a9dfc2">getCALLSEQ_START</a>(Chain, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(NumBytes, <span class="keyword">true</span>));
+<a name="l03633"></a>03633 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CallSeqStart = Chain;
+<a name="l03634"></a>03634
+<a name="l03635"></a>03635 <span class="comment">// Load the return address and frame pointer so it can be move somewhere else</span>
+<a name="l03636"></a>03636 <span class="comment">// later.</span>
+<a name="l03637"></a>03637 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LROp, FPOp;
+<a name="l03638"></a>03638 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, <span class="keyword">true</span>,
+<a name="l03639"></a>03639 dl);
+<a name="l03640"></a>03640
+<a name="l03641"></a>03641 <span class="comment">// Set up a copy of the stack pointer for use loading and storing any</span>
+<a name="l03642"></a>03642 <span class="comment">// arguments that may not fit in the registers available for argument</span>
+<a name="l03643"></a>03643 <span class="comment">// passing.</span>
+<a name="l03644"></a>03644 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> StackPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::X1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l03645"></a>03645
+<a name="l03646"></a>03646 <span class="comment">// Figure out which arguments are going to go in registers, and which in</span>
+<a name="l03647"></a>03647 <span class="comment">// memory. Also, if this is a vararg function, floating point operations</span>
+<a name="l03648"></a>03648 <span class="comment">// must be stored to our stack, and loaded into integer regs as well, if</span>
+<a name="l03649"></a>03649 <span class="comment">// any integer regs are available for argument passing.</span>
+<a name="l03650"></a>03650 <span class="keywordtype">unsigned</span> ArgOffset = <a class="code" href="classllvm_1_1PPCFrameLowering.html#ab90d8608756fd53ed946d0eab8ad6cb7">PPCFrameLowering::getLinkageSize</a>(<span class="keyword">true</span>, <span class="keyword">true</span>);
+<a name="l03651"></a>03651 <span class="keywordtype">unsigned</span> GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
+<a name="l03652"></a>03652
+<a name="l03653"></a>03653 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t GPR[] = {
+<a name="l03654"></a>03654 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+<a name="l03655"></a>03655 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
+<a name="l03656"></a>03656 };
+<a name="l03657"></a>03657 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t *FPR = <a class="code" href="PPCISelLowering_8cpp.html#a1cbd108eaf5aca7619ff85c02489c3a1">GetFPR</a>();
+<a name="l03658"></a>03658
+<a name="l03659"></a>03659 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t VR[] = {
+<a name="l03660"></a>03660 <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">PPC::V2</a>, PPC::V3, <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca72ebe5e08d40fbab96c046e017576a32">PPC::V4</a>, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
+<a name="l03661"></a>03661 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
+<a name="l03662"></a>03662 };
+<a name="l03663"></a>03663 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumGPRs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(GPR);
+<a name="l03664"></a>03664 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumFPRs = 13;
+<a name="l03665"></a>03665 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumVRs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(VR);
+<a name="l03666"></a>03666
+<a name="l03667"></a>03667 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<std::pair<unsigned, SDValue></a>, 8> RegsToPass;
+<a name="l03668"></a>03668 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<TailCallArgumentInfo, 8></a> TailCallArguments;
+<a name="l03669"></a>03669
+<a name="l03670"></a>03670 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> MemOpChains;
+<a name="l03671"></a>03671 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != NumOps; ++i) {
+<a name="l03672"></a>03672 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg = OutVals[i];
+<a name="l03673"></a>03673 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags = Outs[i].Flags;
+<a name="l03674"></a>03674
+<a name="l03675"></a>03675 <span class="comment">// PtrOff will be used to store the current argument to the stack if a</span>
+<a name="l03676"></a>03676 <span class="comment">// register cannot be found for it.</span>
+<a name="l03677"></a>03677 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff;
+<a name="l03678"></a>03678
+<a name="l03679"></a>03679 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(ArgOffset, StackPtr.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l03680"></a>03680
+<a name="l03681"></a>03681 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, StackPtr, PtrOff);
+<a name="l03682"></a>03682
+<a name="l03683"></a>03683 <span class="comment">// Promote integers to 64-bit values.</span>
+<a name="l03684"></a>03684 <span class="keywordflow">if</span> (Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == MVT::i32) {
+<a name="l03685"></a>03685 <span class="comment">// FIXME: Should this use ANY_EXTEND if neither sext nor zext?</span>
+<a name="l03686"></a>03686 <span class="keywordtype">unsigned</span> ExtOp = Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#ae3d1eab6cbe1d4d2bd95ac0844bdee8f">isSExt</a>() ? <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a5183f3d72924bc7c77ba8d3f5de9f602">ISD::SIGN_EXTEND</a> : <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a93fdf85eff945f1a668b4915a051453e" title="ZERO_EXTEND - Used for integer types, zeroing the new bits.">ISD::ZERO_EXTEND</a>;
+<a name="l03687"></a>03687 Arg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(ExtOp, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, Arg);
+<a name="l03688"></a>03688 }
+<a name="l03689"></a>03689
+<a name="l03690"></a>03690 <span class="comment">// FIXME memcpy is used way more than necessary. Correctness first.</span>
+<a name="l03691"></a>03691 <span class="comment">// Note: "by value" is code for passing a structure by value, not</span>
+<a name="l03692"></a>03692 <span class="comment">// basic types.</span>
+<a name="l03693"></a>03693 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a34ee642bf0fb623f775e04e0e60d9b26">isByVal</a>()) {
+<a name="l03694"></a>03694 <span class="comment">// Note: Size includes alignment padding, so</span>
+<a name="l03695"></a>03695 <span class="comment">// struct x { short a; char b; }</span>
+<a name="l03696"></a>03696 <span class="comment">// will have Size = 4. With #pragma pack(1), it will have Size = 3.</span>
+<a name="l03697"></a>03697 <span class="comment">// These are the proper values we need for right-justifying the</span>
+<a name="l03698"></a>03698 <span class="comment">// aggregate in a parameter register.</span>
+<a name="l03699"></a>03699 <span class="keywordtype">unsigned</span> Size = Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a20485215f1c6f05a5c5209725c93de2f">getByValSize</a>();
+<a name="l03700"></a>03700
+<a name="l03701"></a>03701 <span class="comment">// An empty aggregate parameter takes up no storage and no</span>
+<a name="l03702"></a>03702 <span class="comment">// registers.</span>
+<a name="l03703"></a>03703 <span class="keywordflow">if</span> (Size == 0)
+<a name="l03704"></a>03704 <span class="keywordflow">continue</span>;
+<a name="l03705"></a>03705
+<a name="l03706"></a>03706 <span class="comment">// All aggregates smaller than 8 bytes must be passed right-justified.</span>
+<a name="l03707"></a>03707 <span class="keywordflow">if</span> (Size==1 || Size==2 || Size==4) {
+<a name="l03708"></a>03708 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = (Size==1) ? MVT::i8 : ((Size==2) ? <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a> : MVT::i32);
+<a name="l03709"></a>03709 <span class="keywordflow">if</span> (GPR_idx != NumGPRs) {
+<a name="l03710"></a>03710 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1SPII.html#add994c36633ba2d8f6a1366b775e88a6a5069619ca8fdce305534f3fe85091a0f">Load</a> = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a0f9818b48624fb3fda605d6b9e854e60">getExtLoad</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7afab3fffd153f7d7770fed81272e4b78f">ISD::EXTLOAD</a>, dl, PtrVT, Chain, Arg,
+<a name="l03711"></a>03711 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), VT,
+<a name="l03712"></a>03712 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l03713"></a>03713 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l03714"></a>03714 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l03715"></a>03715
+<a name="l03716"></a>03716 ArgOffset += PtrByteSize;
+<a name="l03717"></a>03717 <span class="keywordflow">continue</span>;
+<a name="l03718"></a>03718 }
+<a name="l03719"></a>03719 }
+<a name="l03720"></a>03720
+<a name="l03721"></a>03721 <span class="keywordflow">if</span> (GPR_idx == NumGPRs && Size < 8) {
+<a name="l03722"></a>03722 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Const = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(PtrByteSize - Size,
+<a name="l03723"></a>03723 PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l03724"></a>03724 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AddPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, PtrOff, Const);
+<a name="l03725"></a>03725 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
+<a name="l03726"></a>03726 CallSeqStart,
+<a name="l03727"></a>03727 Flags, DAG, dl);
+<a name="l03728"></a>03728 ArgOffset += PtrByteSize;
+<a name="l03729"></a>03729 <span class="keywordflow">continue</span>;
+<a name="l03730"></a>03730 }
+<a name="l03731"></a>03731 <span class="comment">// Copy entire object into memory. There are cases where gcc-generated</span>
+<a name="l03732"></a>03732 <span class="comment">// code assumes it is there, even if it could be put entirely into</span>
+<a name="l03733"></a>03733 <span class="comment">// registers. (This is not what the doc says.)</span>
+<a name="l03734"></a>03734
+<a name="l03735"></a>03735 <span class="comment">// FIXME: The above statement is likely due to a misunderstanding of the</span>
+<a name="l03736"></a>03736 <span class="comment">// documents. All arguments must be copied into the parameter area BY</span>
+<a name="l03737"></a>03737 <span class="comment">// THE CALLEE in the event that the callee takes the address of any</span>
+<a name="l03738"></a>03738 <span class="comment">// formal argument. That has not yet been implemented. However, it is</span>
+<a name="l03739"></a>03739 <span class="comment">// reasonable to use the stack area as a staging area for the register</span>
+<a name="l03740"></a>03740 <span class="comment">// load.</span>
+<a name="l03741"></a>03741
+<a name="l03742"></a>03742 <span class="comment">// Skip this for small aggregates, as we will use the same slot for a</span>
+<a name="l03743"></a>03743 <span class="comment">// right-justified copy, below.</span>
+<a name="l03744"></a>03744 <span class="keywordflow">if</span> (Size >= 8)
+<a name="l03745"></a>03745 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
+<a name="l03746"></a>03746 CallSeqStart,
+<a name="l03747"></a>03747 Flags, DAG, dl);
+<a name="l03748"></a>03748
+<a name="l03749"></a>03749 <span class="comment">// When a register is available, pass a small aggregate right-justified.</span>
+<a name="l03750"></a>03750 <span class="keywordflow">if</span> (Size < 8 && GPR_idx != NumGPRs) {
+<a name="l03751"></a>03751 <span class="comment">// The easiest way to get this right-justified in a register</span>
+<a name="l03752"></a>03752 <span class="comment">// is to copy the structure into the rightmost portion of a</span>
+<a name="l03753"></a>03753 <span class="comment">// local variable slot, then load the whole slot into the</span>
+<a name="l03754"></a>03754 <span class="comment">// register.</span>
+<a name="l03755"></a>03755 <span class="comment">// FIXME: The memcpy seems to produce pretty awful code for</span>
+<a name="l03756"></a>03756 <span class="comment">// small aggregates, particularly for packed ones.</span>
+<a name="l03757"></a>03757 <span class="comment">// FIXME: It would be preferable to use the slot in the </span>
+<a name="l03758"></a>03758 <span class="comment">// parameter save area instead of a new local variable.</span>
+<a name="l03759"></a>03759 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Const = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(8 - Size, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l03760"></a>03760 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AddPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, PtrOff, Const);
+<a name="l03761"></a>03761 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
+<a name="l03762"></a>03762 CallSeqStart,
+<a name="l03763"></a>03763 Flags, DAG, dl);
+<a name="l03764"></a>03764
+<a name="l03765"></a>03765 <span class="comment">// Load the slot into the register.</span>
+<a name="l03766"></a>03766 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Chain, PtrOff,
+<a name="l03767"></a>03767 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l03768"></a>03768 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l03769"></a>03769 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l03770"></a>03770 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l03771"></a>03771
+<a name="l03772"></a>03772 <span class="comment">// Done with this argument.</span>
+<a name="l03773"></a>03773 ArgOffset += PtrByteSize;
+<a name="l03774"></a>03774 <span class="keywordflow">continue</span>;
+<a name="l03775"></a>03775 }
+<a name="l03776"></a>03776
+<a name="l03777"></a>03777 <span class="comment">// For aggregates larger than PtrByteSize, copy the pieces of the</span>
+<a name="l03778"></a>03778 <span class="comment">// object that fit into registers from the parameter save area.</span>
+<a name="l03779"></a>03779 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j=0; j<Size; j+=PtrByteSize) {
+<a name="l03780"></a>03780 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Const = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(j, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l03781"></a>03781 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AddArg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, Arg, Const);
+<a name="l03782"></a>03782 <span class="keywordflow">if</span> (GPR_idx != NumGPRs) {
+<a name="l03783"></a>03783 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Chain, AddArg,
+<a name="l03784"></a>03784 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l03785"></a>03785 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l03786"></a>03786 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l03787"></a>03787 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l03788"></a>03788 ArgOffset += PtrByteSize;
+<a name="l03789"></a>03789 } <span class="keywordflow">else</span> {
+<a name="l03790"></a>03790 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
+<a name="l03791"></a>03791 <span class="keywordflow">break</span>;
+<a name="l03792"></a>03792 }
+<a name="l03793"></a>03793 }
+<a name="l03794"></a>03794 <span class="keywordflow">continue</span>;
+<a name="l03795"></a>03795 }
+<a name="l03796"></a>03796
+<a name="l03797"></a>03797 <span class="keywordflow">switch</span> (Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l03798"></a>03798 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unexpected ValueType for argument!"</span>);
+<a name="l03799"></a>03799 <span class="keywordflow">case</span> MVT::i32:
+<a name="l03800"></a>03800 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>:
+<a name="l03801"></a>03801 <span class="keywordflow">if</span> (GPR_idx != NumGPRs) {
+<a name="l03802"></a>03802 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Arg));
+<a name="l03803"></a>03803 } <span class="keywordflow">else</span> {
+<a name="l03804"></a>03804 <a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">LowerMemOpCallTo</a>(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
+<a name="l03805"></a>03805 <span class="keyword">true</span>, isTailCall, <span class="keyword">false</span>, MemOpChains,
+<a name="l03806"></a>03806 TailCallArguments, dl);
+<a name="l03807"></a>03807 }
+<a name="l03808"></a>03808 ArgOffset += PtrByteSize;
+<a name="l03809"></a>03809 <span class="keywordflow">break</span>;
+<a name="l03810"></a>03810 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>:
+<a name="l03811"></a>03811 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>:
+<a name="l03812"></a>03812 <span class="keywordflow">if</span> (FPR_idx != NumFPRs) {
+<a name="l03813"></a>03813 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(FPR[FPR_idx++], Arg));
+<a name="l03814"></a>03814
+<a name="l03815"></a>03815 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l03816"></a>03816 <span class="comment">// A single float or an aggregate containing only a single float</span>
+<a name="l03817"></a>03817 <span class="comment">// must be passed right-justified in the stack doubleword, and</span>
+<a name="l03818"></a>03818 <span class="comment">// in the GPR, if one is available.</span>
+<a name="l03819"></a>03819 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> StoreOff;
+<a name="l03820"></a>03820 <span class="keywordflow">if</span> (Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a> == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) {
+<a name="l03821"></a>03821 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ConstFour = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(4, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l03822"></a>03822 StoreOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, PtrOff, ConstFour);
+<a name="l03823"></a>03823 } <span class="keywordflow">else</span>
+<a name="l03824"></a>03824 StoreOff = PtrOff;
+<a name="l03825"></a>03825
+<a name="l03826"></a>03826 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, Arg, StoreOff,
+<a name="l03827"></a>03827 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l03828"></a>03828 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l03829"></a>03829
+<a name="l03830"></a>03830 <span class="comment">// Float varargs are always shadowed in available integer registers</span>
+<a name="l03831"></a>03831 <span class="keywordflow">if</span> (GPR_idx != NumGPRs) {
+<a name="l03832"></a>03832 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Store, PtrOff,
+<a name="l03833"></a>03833 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>,
+<a name="l03834"></a>03834 <span class="keyword">false</span>, 0);
+<a name="l03835"></a>03835 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l03836"></a>03836 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l03837"></a>03837 }
+<a name="l03838"></a>03838 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (GPR_idx != NumGPRs)
+<a name="l03839"></a>03839 <span class="comment">// If we have any FPRs remaining, we may also have GPRs remaining.</span>
+<a name="l03840"></a>03840 ++GPR_idx;
+<a name="l03841"></a>03841 } <span class="keywordflow">else</span> {
+<a name="l03842"></a>03842 <span class="comment">// Single-precision floating-point values are mapped to the</span>
+<a name="l03843"></a>03843 <span class="comment">// second (rightmost) word of the stack doubleword.</span>
+<a name="l03844"></a>03844 <span class="keywordflow">if</span> (Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) {
+<a name="l03845"></a>03845 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ConstFour = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(4, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l03846"></a>03846 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, PtrOff, ConstFour);
+<a name="l03847"></a>03847 }
+<a name="l03848"></a>03848
+<a name="l03849"></a>03849 <a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">LowerMemOpCallTo</a>(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
+<a name="l03850"></a>03850 <span class="keyword">true</span>, isTailCall, <span class="keyword">false</span>, MemOpChains,
+<a name="l03851"></a>03851 TailCallArguments, dl);
+<a name="l03852"></a>03852 }
+<a name="l03853"></a>03853 ArgOffset += 8;
+<a name="l03854"></a>03854 <span class="keywordflow">break</span>;
+<a name="l03855"></a>03855 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l03856"></a>03856 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>:
+<a name="l03857"></a>03857 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>:
+<a name="l03858"></a>03858 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>:
+<a name="l03859"></a>03859 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l03860"></a>03860 <span class="comment">// These go aligned on the stack, or in the corresponding R registers</span>
+<a name="l03861"></a>03861 <span class="comment">// when within range. The Darwin PPC ABI doc claims they also go in</span>
+<a name="l03862"></a>03862 <span class="comment">// V registers; in fact gcc does this only for arguments that are</span>
+<a name="l03863"></a>03863 <span class="comment">// prototyped, not for those that match the ... We do it for all</span>
+<a name="l03864"></a>03864 <span class="comment">// arguments, seems to work.</span>
+<a name="l03865"></a>03865 <span class="keywordflow">while</span> (ArgOffset % 16 !=0) {
+<a name="l03866"></a>03866 ArgOffset += PtrByteSize;
+<a name="l03867"></a>03867 <span class="keywordflow">if</span> (GPR_idx != NumGPRs)
+<a name="l03868"></a>03868 GPR_idx++;
+<a name="l03869"></a>03869 }
+<a name="l03870"></a>03870 <span class="comment">// We could elide this store in the case where the object fits</span>
+<a name="l03871"></a>03871 <span class="comment">// entirely in R registers. Maybe later.</span>
+<a name="l03872"></a>03872 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, StackPtr,
+<a name="l03873"></a>03873 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(ArgOffset, PtrVT));
+<a name="l03874"></a>03874 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, Arg, PtrOff,
+<a name="l03875"></a>03875 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l03876"></a>03876 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l03877"></a>03877 <span class="keywordflow">if</span> (VR_idx != NumVRs) {
+<a name="l03878"></a>03878 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, dl, Store, PtrOff,
+<a name="l03879"></a>03879 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l03880"></a>03880 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l03881"></a>03881 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l03882"></a>03882 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(VR[VR_idx++], Load));
+<a name="l03883"></a>03883 }
+<a name="l03884"></a>03884 ArgOffset += 16;
+<a name="l03885"></a>03885 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i=0; i<16; i+=PtrByteSize) {
+<a name="l03886"></a>03886 <span class="keywordflow">if</span> (GPR_idx == NumGPRs)
+<a name="l03887"></a>03887 <span class="keywordflow">break</span>;
+<a name="l03888"></a>03888 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ix = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, PtrOff,
+<a name="l03889"></a>03889 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(i, PtrVT));
+<a name="l03890"></a>03890 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Store, Ix, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l03891"></a>03891 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l03892"></a>03892 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l03893"></a>03893 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l03894"></a>03894 }
+<a name="l03895"></a>03895 <span class="keywordflow">break</span>;
+<a name="l03896"></a>03896 }
+<a name="l03897"></a>03897
+<a name="l03898"></a>03898 <span class="comment">// Non-varargs Altivec params generally go in registers, but have</span>
+<a name="l03899"></a>03899 <span class="comment">// stack space allocated at the end.</span>
+<a name="l03900"></a>03900 <span class="keywordflow">if</span> (VR_idx != NumVRs) {
+<a name="l03901"></a>03901 <span class="comment">// Doesn't have GPR space allocated.</span>
+<a name="l03902"></a>03902 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(VR[VR_idx++], Arg));
+<a name="l03903"></a>03903 } <span class="keywordflow">else</span> {
+<a name="l03904"></a>03904 <a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">LowerMemOpCallTo</a>(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
+<a name="l03905"></a>03905 <span class="keyword">true</span>, isTailCall, <span class="keyword">true</span>, MemOpChains,
+<a name="l03906"></a>03906 TailCallArguments, dl);
+<a name="l03907"></a>03907 ArgOffset += 16;
+<a name="l03908"></a>03908 }
+<a name="l03909"></a>03909 <span class="keywordflow">break</span>;
+<a name="l03910"></a>03910 }
+<a name="l03911"></a>03911 }
+<a name="l03912"></a>03912
+<a name="l03913"></a>03913 <span class="keywordflow">if</span> (!MemOpChains.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l03914"></a>03914 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad469508535ce2082a1ab1f0e429187b8">ISD::TokenFactor</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>,
+<a name="l03915"></a>03915 &MemOpChains[0], MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l03916"></a>03916
+<a name="l03917"></a>03917 <span class="comment">// Check if this is an indirect call (MTCTR/BCTRL).</span>
+<a name="l03918"></a>03918 <span class="comment">// See PrepareCall() for more information about calls through function</span>
+<a name="l03919"></a>03919 <span class="comment">// pointers in the 64-bit SVR4 ABI.</span>
+<a name="l03920"></a>03920 <span class="keywordflow">if</span> (!isTailCall &&
+<a name="l03921"></a>03921 !dyn_cast<GlobalAddressSDNode>(Callee) &&
+<a name="l03922"></a>03922 !<a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ExternalSymbolSDNode.html">ExternalSymbolSDNode</a>>(Callee) &&
+<a name="l03923"></a>03923 !<a class="code" href="PPCISelLowering_8cpp.html#aca2e60fc82a1bde79b2afe10ef5c520d">isBLACompatibleAddress</a>(Callee, DAG)) {
+<a name="l03924"></a>03924 <span class="comment">// Load r2 into a virtual register and store it to the TOC save area.</span>
+<a name="l03925"></a>03925 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a73bac1ad181451211a9680323c87011c">getCopyFromReg</a>(Chain, dl, PPC::X2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l03926"></a>03926 <span class="comment">// TOC save area offset.</span>
+<a name="l03927"></a>03927 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(40);
+<a name="l03928"></a>03928 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AddPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, StackPtr, PtrOff);
+<a name="l03929"></a>03929 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Val.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, Val, AddPtr, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l03930"></a>03930 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l03931"></a>03931 <span class="comment">// R12 must contain the address of an indirect callee. This does not</span>
+<a name="l03932"></a>03932 <span class="comment">// mean the MTCTR instruction must use R12; it's easier to model this</span>
+<a name="l03933"></a>03933 <span class="comment">// as an extra parameter, so do that.</span>
+<a name="l03934"></a>03934 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair((<span class="keywordtype">unsigned</span>)PPC::X12, Callee));
+<a name="l03935"></a>03935 }
+<a name="l03936"></a>03936
+<a name="l03937"></a>03937 <span class="comment">// Build a sequence of copy-to-reg nodes chained together with token chain</span>
+<a name="l03938"></a>03938 <span class="comment">// and flag operands which copy the outgoing args into the appropriate regs.</span>
+<a name="l03939"></a>03939 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag;
+<a name="l03940"></a>03940 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i != e; ++i) {
+<a name="l03941"></a>03941 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a64720b4e2b3deb1f80177f31d1843691">getCopyToReg</a>(Chain, dl, RegsToPass[i].first,
+<a name="l03942"></a>03942 RegsToPass[i].second, InFlag);
+<a name="l03943"></a>03943 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03944"></a>03944 }
+<a name="l03945"></a>03945
+<a name="l03946"></a>03946 <span class="keywordflow">if</span> (isTailCall)
+<a name="l03947"></a>03947 <a class="code" href="PPCISelLowering_8cpp.html#a6e0cf06aedc5ad75745f3834560a71a6">PrepareTailCall</a>(DAG, InFlag, Chain, dl, <span class="keyword">true</span>, SPDiff, NumBytes, LROp,
+<a name="l03948"></a>03948 FPOp, <span class="keyword">true</span>, TailCallArguments);
+<a name="l03949"></a>03949
+<a name="l03950"></a>03950 <span class="keywordflow">return</span> FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
+<a name="l03951"></a>03951 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
+<a name="l03952"></a>03952 Ins, InVals);
+<a name="l03953"></a>03953 }
+<a name="l03954"></a>03954
+<a name="l03955"></a>03955 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l03956"></a>03956 PPCTargetLowering::LowerCall_Darwin(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Callee,
+<a name="l03957"></a>03957 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l03958"></a>03958 <span class="keywordtype">bool</span> isTailCall,
+<a name="l03959"></a>03959 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::OutputArg></a> &Outs,
+<a name="l03960"></a>03960 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &OutVals,
+<a name="l03961"></a>03961 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::InputArg></a> &Ins,
+<a name="l03962"></a>03962 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l03963"></a>03963 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &InVals)<span class="keyword"> const </span>{
+<a name="l03964"></a>03964
+<a name="l03965"></a>03965 <span class="keywordtype">unsigned</span> NumOps = Outs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>();
+<a name="l03966"></a>03966
+<a name="l03967"></a>03967 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l03968"></a>03968 <span class="keywordtype">bool</span> isPPC64 = PtrVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>;
+<a name="l03969"></a>03969 <span class="keywordtype">unsigned</span> PtrByteSize = isPPC64 ? 8 : 4;
+<a name="l03970"></a>03970
+<a name="l03971"></a>03971 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l03972"></a>03972
+<a name="l03973"></a>03973 <span class="comment">// Mark this function as potentially containing a function that contains a</span>
+<a name="l03974"></a>03974 <span class="comment">// tail call. As a consequence the frame pointer will be used for dynamicalloc</span>
+<a name="l03975"></a>03975 <span class="comment">// and restoring the callers stack pointer in this functions epilog. This is</span>
+<a name="l03976"></a>03976 <span class="comment">// done because by tail calling the called function might overwrite the value</span>
+<a name="l03977"></a>03977 <span class="comment">// in this function's (MF) stack pointer stack slot 0(SP).</span>
+<a name="l03978"></a>03978 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().Options.GuaranteedTailCallOpt &&
+<a name="l03979"></a>03979 CallConv == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974abc8e2ee40a84687a9e12fd08784b87ba">CallingConv::Fast</a>)
+<a name="l03980"></a>03980 MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>()->setHasFastCall();
+<a name="l03981"></a>03981
+<a name="l03982"></a>03982 <span class="keywordtype">unsigned</span> nAltivecParamsAtEnd = 0;
+<a name="l03983"></a>03983
+<a name="l03984"></a>03984 <span class="comment">// Count how many bytes are to be pushed on the stack, including the linkage</span>
+<a name="l03985"></a>03985 <span class="comment">// area, and parameter passing area. We start with 24/48 bytes, which is</span>
+<a name="l03986"></a>03986 <span class="comment">// prereserved space for [SP][CR][LR][3 x unused].</span>
+<a name="l03987"></a>03987 <span class="keywordtype">unsigned</span> NumBytes =
+<a name="l03988"></a>03988 <a class="code" href="PPCISelLowering_8cpp.html#a3c31aec5751525d6fd2c9a3c7916b637">CalculateParameterAndLinkageAreaSize</a>(DAG, isPPC64, isVarArg, CallConv,
+<a name="l03989"></a>03989 Outs, OutVals,
+<a name="l03990"></a>03990 nAltivecParamsAtEnd);
+<a name="l03991"></a>03991
+<a name="l03992"></a>03992 <span class="comment">// Calculate by how many bytes the stack has to be adjusted in case of tail</span>
+<a name="l03993"></a>03993 <span class="comment">// call optimization.</span>
+<a name="l03994"></a>03994 <span class="keywordtype">int</span> SPDiff = <a class="code" href="PPCISelLowering_8cpp.html#aaf0bcfcb9ee7e078bec6074304e31cb0">CalculateTailCallSPDiff</a>(DAG, isTailCall, NumBytes);
+<a name="l03995"></a>03995
+<a name="l03996"></a>03996 <span class="comment">// To protect arguments on the stack from being clobbered in a tail call,</span>
+<a name="l03997"></a>03997 <span class="comment">// force all the loads to happen before doing any other lowering.</span>
+<a name="l03998"></a>03998 <span class="keywordflow">if</span> (isTailCall)
+<a name="l03999"></a>03999 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a1487d4dfd14eebe24447f52b04bb8f6f">getStackArgumentTokenFactor</a>(Chain);
+<a name="l04000"></a>04000
+<a name="l04001"></a>04001 <span class="comment">// Adjust the stack pointer for the new arguments...</span>
+<a name="l04002"></a>04002 <span class="comment">// These operations are automatically eliminated by the prolog/epilog pass</span>
+<a name="l04003"></a>04003 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#aa3b147eb51c574c8d7149855e4a9dfc2">getCALLSEQ_START</a>(Chain, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(NumBytes, <span class="keyword">true</span>));
+<a name="l04004"></a>04004 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CallSeqStart = Chain;
+<a name="l04005"></a>04005
+<a name="l04006"></a>04006 <span class="comment">// Load the return address and frame pointer so it can be move somewhere else</span>
+<a name="l04007"></a>04007 <span class="comment">// later.</span>
+<a name="l04008"></a>04008 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LROp, FPOp;
+<a name="l04009"></a>04009 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, <span class="keyword">true</span>,
+<a name="l04010"></a>04010 dl);
+<a name="l04011"></a>04011
+<a name="l04012"></a>04012 <span class="comment">// Set up a copy of the stack pointer for use loading and storing any</span>
+<a name="l04013"></a>04013 <span class="comment">// arguments that may not fit in the registers available for argument</span>
+<a name="l04014"></a>04014 <span class="comment">// passing.</span>
+<a name="l04015"></a>04015 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> StackPtr;
+<a name="l04016"></a>04016 <span class="keywordflow">if</span> (isPPC64)
+<a name="l04017"></a>04017 StackPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::X1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l04018"></a>04018 <span class="keywordflow">else</span>
+<a name="l04019"></a>04019 StackPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::R1, MVT::i32);
+<a name="l04020"></a>04020
+<a name="l04021"></a>04021 <span class="comment">// Figure out which arguments are going to go in registers, and which in</span>
+<a name="l04022"></a>04022 <span class="comment">// memory. Also, if this is a vararg function, floating point operations</span>
+<a name="l04023"></a>04023 <span class="comment">// must be stored to our stack, and loaded into integer regs as well, if</span>
+<a name="l04024"></a>04024 <span class="comment">// any integer regs are available for argument passing.</span>
+<a name="l04025"></a>04025 <span class="keywordtype">unsigned</span> ArgOffset = <a class="code" href="classllvm_1_1PPCFrameLowering.html#ab90d8608756fd53ed946d0eab8ad6cb7">PPCFrameLowering::getLinkageSize</a>(isPPC64, <span class="keyword">true</span>);
+<a name="l04026"></a>04026 <span class="keywordtype">unsigned</span> GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
+<a name="l04027"></a>04027
+<a name="l04028"></a>04028 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t GPR_32[] = { <span class="comment">// 32-bit registers.</span>
+<a name="l04029"></a>04029 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
+<a name="l04030"></a>04030 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
+<a name="l04031"></a>04031 };
+<a name="l04032"></a>04032 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t GPR_64[] = { <span class="comment">// 64-bit registers.</span>
+<a name="l04033"></a>04033 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
+<a name="l04034"></a>04034 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
+<a name="l04035"></a>04035 };
+<a name="l04036"></a>04036 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t *FPR = <a class="code" href="PPCISelLowering_8cpp.html#a1cbd108eaf5aca7619ff85c02489c3a1">GetFPR</a>();
+<a name="l04037"></a>04037
+<a name="l04038"></a>04038 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t VR[] = {
+<a name="l04039"></a>04039 <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">PPC::V2</a>, PPC::V3, <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca72ebe5e08d40fbab96c046e017576a32">PPC::V4</a>, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
+<a name="l04040"></a>04040 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
+<a name="l04041"></a>04041 };
+<a name="l04042"></a>04042 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumGPRs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(GPR_32);
+<a name="l04043"></a>04043 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumFPRs = 13;
+<a name="l04044"></a>04044 <span class="keyword">const</span> <span class="keywordtype">unsigned</span> NumVRs = <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(VR);
+<a name="l04045"></a>04045
+<a name="l04046"></a>04046 <span class="keyword">const</span> uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
+<a name="l04047"></a>04047
+<a name="l04048"></a>04048 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<std::pair<unsigned, SDValue></a>, 8> RegsToPass;
+<a name="l04049"></a>04049 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<TailCallArgumentInfo, 8></a> TailCallArguments;
+<a name="l04050"></a>04050
+<a name="l04051"></a>04051 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> MemOpChains;
+<a name="l04052"></a>04052 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != NumOps; ++i) {
+<a name="l04053"></a>04053 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg = OutVals[i];
+<a name="l04054"></a>04054 <a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html">ISD::ArgFlagsTy</a> Flags = Outs[i].Flags;
+<a name="l04055"></a>04055
+<a name="l04056"></a>04056 <span class="comment">// PtrOff will be used to store the current argument to the stack if a</span>
+<a name="l04057"></a>04057 <span class="comment">// register cannot be found for it.</span>
+<a name="l04058"></a>04058 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff;
+<a name="l04059"></a>04059
+<a name="l04060"></a>04060 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(ArgOffset, StackPtr.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l04061"></a>04061
+<a name="l04062"></a>04062 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, StackPtr, PtrOff);
+<a name="l04063"></a>04063
+<a name="l04064"></a>04064 <span class="comment">// On PPC64, promote integers to 64-bit values.</span>
+<a name="l04065"></a>04065 <span class="keywordflow">if</span> (isPPC64 && Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == MVT::i32) {
+<a name="l04066"></a>04066 <span class="comment">// FIXME: Should this use ANY_EXTEND if neither sext nor zext?</span>
+<a name="l04067"></a>04067 <span class="keywordtype">unsigned</span> ExtOp = Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#ae3d1eab6cbe1d4d2bd95ac0844bdee8f">isSExt</a>() ? <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a5183f3d72924bc7c77ba8d3f5de9f602">ISD::SIGN_EXTEND</a> : <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a93fdf85eff945f1a668b4915a051453e" title="ZERO_EXTEND - Used for integer types, zeroing the new bits.">ISD::ZERO_EXTEND</a>;
+<a name="l04068"></a>04068 Arg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(ExtOp, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, Arg);
+<a name="l04069"></a>04069 }
+<a name="l04070"></a>04070
+<a name="l04071"></a>04071 <span class="comment">// FIXME memcpy is used way more than necessary. Correctness first.</span>
+<a name="l04072"></a>04072 <span class="comment">// Note: "by value" is code for passing a structure by value, not</span>
+<a name="l04073"></a>04073 <span class="comment">// basic types.</span>
+<a name="l04074"></a>04074 <span class="keywordflow">if</span> (Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a34ee642bf0fb623f775e04e0e60d9b26">isByVal</a>()) {
+<a name="l04075"></a>04075 <span class="keywordtype">unsigned</span> Size = Flags.<a class="code" href="structllvm_1_1ISD_1_1ArgFlagsTy.html#a20485215f1c6f05a5c5209725c93de2f">getByValSize</a>();
+<a name="l04076"></a>04076 <span class="comment">// Very small objects are passed right-justified. Everything else is</span>
+<a name="l04077"></a>04077 <span class="comment">// passed left-justified.</span>
+<a name="l04078"></a>04078 <span class="keywordflow">if</span> (Size==1 || Size==2) {
+<a name="l04079"></a>04079 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = (Size==1) ? MVT::i8 : <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>;
+<a name="l04080"></a>04080 <span class="keywordflow">if</span> (GPR_idx != NumGPRs) {
+<a name="l04081"></a>04081 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a0f9818b48624fb3fda605d6b9e854e60">getExtLoad</a>(<a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7afab3fffd153f7d7770fed81272e4b78f">ISD::EXTLOAD</a>, dl, PtrVT, Chain, Arg,
+<a name="l04082"></a>04082 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), VT,
+<a name="l04083"></a>04083 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04084"></a>04084 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l04085"></a>04085 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l04086"></a>04086
+<a name="l04087"></a>04087 ArgOffset += PtrByteSize;
+<a name="l04088"></a>04088 } <span class="keywordflow">else</span> {
+<a name="l04089"></a>04089 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Const = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(PtrByteSize - Size,
+<a name="l04090"></a>04090 PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l04091"></a>04091 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AddPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, PtrOff, Const);
+<a name="l04092"></a>04092 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
+<a name="l04093"></a>04093 CallSeqStart,
+<a name="l04094"></a>04094 Flags, DAG, dl);
+<a name="l04095"></a>04095 ArgOffset += PtrByteSize;
+<a name="l04096"></a>04096 }
+<a name="l04097"></a>04097 <span class="keywordflow">continue</span>;
+<a name="l04098"></a>04098 }
+<a name="l04099"></a>04099 <span class="comment">// Copy entire object into memory. There are cases where gcc-generated</span>
+<a name="l04100"></a>04100 <span class="comment">// code assumes it is there, even if it could be put entirely into</span>
+<a name="l04101"></a>04101 <span class="comment">// registers. (This is not what the doc says.)</span>
+<a name="l04102"></a>04102 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
+<a name="l04103"></a>04103 CallSeqStart,
+<a name="l04104"></a>04104 Flags, DAG, dl);
+<a name="l04105"></a>04105
+<a name="l04106"></a>04106 <span class="comment">// For small aggregates (Darwin only) and aggregates >= PtrByteSize,</span>
+<a name="l04107"></a>04107 <span class="comment">// copy the pieces of the object that fit into registers from the</span>
+<a name="l04108"></a>04108 <span class="comment">// parameter save area.</span>
+<a name="l04109"></a>04109 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j=0; j<Size; j+=PtrByteSize) {
+<a name="l04110"></a>04110 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Const = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(j, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l04111"></a>04111 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AddArg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, Arg, Const);
+<a name="l04112"></a>04112 <span class="keywordflow">if</span> (GPR_idx != NumGPRs) {
+<a name="l04113"></a>04113 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Chain, AddArg,
+<a name="l04114"></a>04114 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04115"></a>04115 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04116"></a>04116 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l04117"></a>04117 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l04118"></a>04118 ArgOffset += PtrByteSize;
+<a name="l04119"></a>04119 } <span class="keywordflow">else</span> {
+<a name="l04120"></a>04120 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
+<a name="l04121"></a>04121 <span class="keywordflow">break</span>;
+<a name="l04122"></a>04122 }
+<a name="l04123"></a>04123 }
+<a name="l04124"></a>04124 <span class="keywordflow">continue</span>;
+<a name="l04125"></a>04125 }
+<a name="l04126"></a>04126
+<a name="l04127"></a>04127 <span class="keywordflow">switch</span> (Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l04128"></a>04128 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unexpected ValueType for argument!"</span>);
+<a name="l04129"></a>04129 <span class="keywordflow">case</span> MVT::i32:
+<a name="l04130"></a>04130 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>:
+<a name="l04131"></a>04131 <span class="keywordflow">if</span> (GPR_idx != NumGPRs) {
+<a name="l04132"></a>04132 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Arg));
+<a name="l04133"></a>04133 } <span class="keywordflow">else</span> {
+<a name="l04134"></a>04134 <a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">LowerMemOpCallTo</a>(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
+<a name="l04135"></a>04135 isPPC64, isTailCall, <span class="keyword">false</span>, MemOpChains,
+<a name="l04136"></a>04136 TailCallArguments, dl);
+<a name="l04137"></a>04137 }
+<a name="l04138"></a>04138 ArgOffset += PtrByteSize;
+<a name="l04139"></a>04139 <span class="keywordflow">break</span>;
+<a name="l04140"></a>04140 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>:
+<a name="l04141"></a>04141 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>:
+<a name="l04142"></a>04142 <span class="keywordflow">if</span> (FPR_idx != NumFPRs) {
+<a name="l04143"></a>04143 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(FPR[FPR_idx++], Arg));
+<a name="l04144"></a>04144
+<a name="l04145"></a>04145 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l04146"></a>04146 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, Arg, PtrOff,
+<a name="l04147"></a>04147 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04148"></a>04148 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l04149"></a>04149
+<a name="l04150"></a>04150 <span class="comment">// Float varargs are always shadowed in available integer registers</span>
+<a name="l04151"></a>04151 <span class="keywordflow">if</span> (GPR_idx != NumGPRs) {
+<a name="l04152"></a>04152 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Store, PtrOff,
+<a name="l04153"></a>04153 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>,
+<a name="l04154"></a>04154 <span class="keyword">false</span>, 0);
+<a name="l04155"></a>04155 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l04156"></a>04156 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l04157"></a>04157 }
+<a name="l04158"></a>04158 <span class="keywordflow">if</span> (GPR_idx != NumGPRs && Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a> && !isPPC64){
+<a name="l04159"></a>04159 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ConstFour = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(4, PtrOff.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l04160"></a>04160 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, PtrOff, ConstFour);
+<a name="l04161"></a>04161 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Store, PtrOff,
+<a name="l04162"></a>04162 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04163"></a>04163 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04164"></a>04164 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l04165"></a>04165 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l04166"></a>04166 }
+<a name="l04167"></a>04167 } <span class="keywordflow">else</span> {
+<a name="l04168"></a>04168 <span class="comment">// If we have any FPRs remaining, we may also have GPRs remaining.</span>
+<a name="l04169"></a>04169 <span class="comment">// Args passed in FPRs consume either 1 (f32) or 2 (f64) available</span>
+<a name="l04170"></a>04170 <span class="comment">// GPRs.</span>
+<a name="l04171"></a>04171 <span class="keywordflow">if</span> (GPR_idx != NumGPRs)
+<a name="l04172"></a>04172 ++GPR_idx;
+<a name="l04173"></a>04173 <span class="keywordflow">if</span> (GPR_idx != NumGPRs && Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a> &&
+<a name="l04174"></a>04174 !isPPC64) <span class="comment">// PPC64 has 64-bit GPR's obviously :)</span>
+<a name="l04175"></a>04175 ++GPR_idx;
+<a name="l04176"></a>04176 }
+<a name="l04177"></a>04177 } <span class="keywordflow">else</span>
+<a name="l04178"></a>04178 <a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">LowerMemOpCallTo</a>(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
+<a name="l04179"></a>04179 isPPC64, isTailCall, <span class="keyword">false</span>, MemOpChains,
+<a name="l04180"></a>04180 TailCallArguments, dl);
+<a name="l04181"></a>04181 <span class="keywordflow">if</span> (isPPC64)
+<a name="l04182"></a>04182 ArgOffset += 8;
+<a name="l04183"></a>04183 <span class="keywordflow">else</span>
+<a name="l04184"></a>04184 ArgOffset += Arg.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a> ? 4 : 8;
+<a name="l04185"></a>04185 <span class="keywordflow">break</span>;
+<a name="l04186"></a>04186 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l04187"></a>04187 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>:
+<a name="l04188"></a>04188 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>:
+<a name="l04189"></a>04189 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>:
+<a name="l04190"></a>04190 <span class="keywordflow">if</span> (isVarArg) {
+<a name="l04191"></a>04191 <span class="comment">// These go aligned on the stack, or in the corresponding R registers</span>
+<a name="l04192"></a>04192 <span class="comment">// when within range. The Darwin PPC ABI doc claims they also go in</span>
+<a name="l04193"></a>04193 <span class="comment">// V registers; in fact gcc does this only for arguments that are</span>
+<a name="l04194"></a>04194 <span class="comment">// prototyped, not for those that match the ... We do it for all</span>
+<a name="l04195"></a>04195 <span class="comment">// arguments, seems to work.</span>
+<a name="l04196"></a>04196 <span class="keywordflow">while</span> (ArgOffset % 16 !=0) {
+<a name="l04197"></a>04197 ArgOffset += PtrByteSize;
+<a name="l04198"></a>04198 <span class="keywordflow">if</span> (GPR_idx != NumGPRs)
+<a name="l04199"></a>04199 GPR_idx++;
+<a name="l04200"></a>04200 }
+<a name="l04201"></a>04201 <span class="comment">// We could elide this store in the case where the object fits</span>
+<a name="l04202"></a>04202 <span class="comment">// entirely in R registers. Maybe later.</span>
+<a name="l04203"></a>04203 PtrOff = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, StackPtr,
+<a name="l04204"></a>04204 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(ArgOffset, PtrVT));
+<a name="l04205"></a>04205 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, Arg, PtrOff,
+<a name="l04206"></a>04206 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04207"></a>04207 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Store);
+<a name="l04208"></a>04208 <span class="keywordflow">if</span> (VR_idx != NumVRs) {
+<a name="l04209"></a>04209 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>, dl, Store, PtrOff,
+<a name="l04210"></a>04210 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04211"></a>04211 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04212"></a>04212 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l04213"></a>04213 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(VR[VR_idx++], Load));
+<a name="l04214"></a>04214 }
+<a name="l04215"></a>04215 ArgOffset += 16;
+<a name="l04216"></a>04216 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i=0; i<16; i+=PtrByteSize) {
+<a name="l04217"></a>04217 <span class="keywordflow">if</span> (GPR_idx == NumGPRs)
+<a name="l04218"></a>04218 <span class="keywordflow">break</span>;
+<a name="l04219"></a>04219 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ix = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, PtrOff,
+<a name="l04220"></a>04220 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(i, PtrVT));
+<a name="l04221"></a>04221 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Load = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Store, Ix, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04222"></a>04222 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04223"></a>04223 MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Load.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l04224"></a>04224 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(GPR[GPR_idx++], Load));
+<a name="l04225"></a>04225 }
+<a name="l04226"></a>04226 <span class="keywordflow">break</span>;
+<a name="l04227"></a>04227 }
+<a name="l04228"></a>04228
+<a name="l04229"></a>04229 <span class="comment">// Non-varargs Altivec params generally go in registers, but have</span>
+<a name="l04230"></a>04230 <span class="comment">// stack space allocated at the end.</span>
+<a name="l04231"></a>04231 <span class="keywordflow">if</span> (VR_idx != NumVRs) {
+<a name="l04232"></a>04232 <span class="comment">// Doesn't have GPR space allocated.</span>
+<a name="l04233"></a>04233 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(VR[VR_idx++], Arg));
+<a name="l04234"></a>04234 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (nAltivecParamsAtEnd==0) {
+<a name="l04235"></a>04235 <span class="comment">// We are emitting Altivec params in order.</span>
+<a name="l04236"></a>04236 <a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">LowerMemOpCallTo</a>(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
+<a name="l04237"></a>04237 isPPC64, isTailCall, <span class="keyword">true</span>, MemOpChains,
+<a name="l04238"></a>04238 TailCallArguments, dl);
+<a name="l04239"></a>04239 ArgOffset += 16;
+<a name="l04240"></a>04240 }
+<a name="l04241"></a>04241 <span class="keywordflow">break</span>;
+<a name="l04242"></a>04242 }
+<a name="l04243"></a>04243 }
+<a name="l04244"></a>04244 <span class="comment">// If all Altivec parameters fit in registers, as they usually do,</span>
+<a name="l04245"></a>04245 <span class="comment">// they get stack space following the non-Altivec parameters. We</span>
+<a name="l04246"></a>04246 <span class="comment">// don't track this here because nobody below needs it.</span>
+<a name="l04247"></a>04247 <span class="comment">// If there are more Altivec parameters than fit in registers emit</span>
+<a name="l04248"></a>04248 <span class="comment">// the stores here.</span>
+<a name="l04249"></a>04249 <span class="keywordflow">if</span> (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
+<a name="l04250"></a>04250 <span class="keywordtype">unsigned</span> j = 0;
+<a name="l04251"></a>04251 <span class="comment">// Offset is aligned; skip 1st 12 params which go in V registers.</span>
+<a name="l04252"></a>04252 ArgOffset = ((ArgOffset+15)/16)*16;
+<a name="l04253"></a>04253 ArgOffset += 12*16;
+<a name="l04254"></a>04254 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != NumOps; ++i) {
+<a name="l04255"></a>04255 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg = OutVals[i];
+<a name="l04256"></a>04256 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ArgType = Outs[i].VT;
+<a name="l04257"></a>04257 <span class="keywordflow">if</span> (ArgType==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a> || ArgType==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a> ||
+<a name="l04258"></a>04258 ArgType==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a> || ArgType==<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>) {
+<a name="l04259"></a>04259 <span class="keywordflow">if</span> (++j > NumVRs) {
+<a name="l04260"></a>04260 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PtrOff;
+<a name="l04261"></a>04261 <span class="comment">// We are emitting Altivec params in order.</span>
+<a name="l04262"></a>04262 <a class="code" href="PPCISelLowering_8cpp.html#a3c33721c113cdbc1ea2f1c8f4da8b99d">LowerMemOpCallTo</a>(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
+<a name="l04263"></a>04263 isPPC64, isTailCall, <span class="keyword">true</span>, MemOpChains,
+<a name="l04264"></a>04264 TailCallArguments, dl);
+<a name="l04265"></a>04265 ArgOffset += 16;
+<a name="l04266"></a>04266 }
+<a name="l04267"></a>04267 }
+<a name="l04268"></a>04268 }
+<a name="l04269"></a>04269 }
+<a name="l04270"></a>04270
+<a name="l04271"></a>04271 <span class="keywordflow">if</span> (!MemOpChains.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l04272"></a>04272 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad469508535ce2082a1ab1f0e429187b8">ISD::TokenFactor</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>,
+<a name="l04273"></a>04273 &MemOpChains[0], MemOpChains.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l04274"></a>04274
+<a name="l04275"></a>04275 <span class="comment">// On Darwin, R12 must contain the address of an indirect callee. This does</span>
+<a name="l04276"></a>04276 <span class="comment">// not mean the MTCTR instruction must use R12; it's easier to model this as</span>
+<a name="l04277"></a>04277 <span class="comment">// an extra parameter, so do that.</span>
+<a name="l04278"></a>04278 <span class="keywordflow">if</span> (!isTailCall &&
+<a name="l04279"></a>04279 !dyn_cast<GlobalAddressSDNode>(Callee) &&
+<a name="l04280"></a>04280 !<a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ExternalSymbolSDNode.html">ExternalSymbolSDNode</a>>(Callee) &&
+<a name="l04281"></a>04281 !<a class="code" href="PPCISelLowering_8cpp.html#aca2e60fc82a1bde79b2afe10ef5c520d">isBLACompatibleAddress</a>(Callee, DAG))
+<a name="l04282"></a>04282 RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair((<span class="keywordtype">unsigned</span>)(isPPC64 ? PPC::X12 :
+<a name="l04283"></a>04283 PPC::R12), Callee));
+<a name="l04284"></a>04284
+<a name="l04285"></a>04285 <span class="comment">// Build a sequence of copy-to-reg nodes chained together with token chain</span>
+<a name="l04286"></a>04286 <span class="comment">// and flag operands which copy the outgoing args into the appropriate regs.</span>
+<a name="l04287"></a>04287 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag;
+<a name="l04288"></a>04288 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = RegsToPass.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i != e; ++i) {
+<a name="l04289"></a>04289 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a64720b4e2b3deb1f80177f31d1843691">getCopyToReg</a>(Chain, dl, RegsToPass[i].first,
+<a name="l04290"></a>04290 RegsToPass[i].second, InFlag);
+<a name="l04291"></a>04291 InFlag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l04292"></a>04292 }
+<a name="l04293"></a>04293
+<a name="l04294"></a>04294 <span class="keywordflow">if</span> (isTailCall)
+<a name="l04295"></a>04295 <a class="code" href="PPCISelLowering_8cpp.html#a6e0cf06aedc5ad75745f3834560a71a6">PrepareTailCall</a>(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
+<a name="l04296"></a>04296 FPOp, <span class="keyword">true</span>, TailCallArguments);
+<a name="l04297"></a>04297
+<a name="l04298"></a>04298 <span class="keywordflow">return</span> FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
+<a name="l04299"></a>04299 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
+<a name="l04300"></a>04300 Ins, InVals);
+<a name="l04301"></a>04301 }
+<a name="l04302"></a>04302
+<a name="l04303"></a>04303 <span class="keywordtype">bool</span>
+<a name="l04304"></a>04304 PPCTargetLowering::CanLowerReturn(<a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv,
+<a name="l04305"></a>04305 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF, <span class="keywordtype">bool</span> isVarArg,
+<a name="l04306"></a>04306 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::OutputArg></a> &Outs,
+<a name="l04307"></a>04307 <a class="code" href="classllvm_1_1LLVMContext.html">LLVMContext</a> &Context)<span class="keyword"> const </span>{
+<a name="l04308"></a>04308 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<CCValAssign, 16></a> RVLocs;
+<a name="l04309"></a>04309 <a class="code" href="classllvm_1_1CCState.html">CCState</a> CCInfo(CallConv, isVarArg, MF, <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>(),
+<a name="l04310"></a>04310 RVLocs, Context);
+<a name="l04311"></a>04311 <span class="keywordflow">return</span> CCInfo.CheckReturn(Outs, RetCC_PPC);
+<a name="l04312"></a>04312 }
+<a name="l04313"></a>04313
+<a name="l04314"></a>04314 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l04315"></a>04315 PPCTargetLowering::LowerReturn(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain,
+<a name="l04316"></a>04316 <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974" title="LLVM Calling Convention Representation.">CallingConv::ID</a> CallConv, <span class="keywordtype">bool</span> isVarArg,
+<a name="l04317"></a>04317 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<ISD::OutputArg></a> &Outs,
+<a name="l04318"></a>04318 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a> &OutVals,
+<a name="l04319"></a>04319 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l04320"></a>04320
+<a name="l04321"></a>04321 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<CCValAssign, 16></a> RVLocs;
+<a name="l04322"></a>04322 <a class="code" href="classllvm_1_1CCState.html">CCState</a> CCInfo(CallConv, isVarArg, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>(),
+<a name="l04323"></a>04323 <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>(), RVLocs, *DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a39c6dff47b8dbd25cfaf6336c7056077">getContext</a>());
+<a name="l04324"></a>04324 CCInfo.<a class="code" href="classllvm_1_1CCState.html#a73b07a938dd8182363ba52719d38bf53">AnalyzeReturn</a>(Outs, RetCC_PPC);
+<a name="l04325"></a>04325
+<a name="l04326"></a>04326 <span class="comment">// If this is the first return lowered for this function, add the regs to the</span>
+<a name="l04327"></a>04327 <span class="comment">// liveout set for the function.</span>
+<a name="l04328"></a>04328 <span class="keywordflow">if</span> (DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a60f6bf9d77fabdbf75998d1ecd9ee4ac">liveout_empty</a>()) {
+<a name="l04329"></a>04329 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != RVLocs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); ++i)
+<a name="l04330"></a>04330 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#ad01a8efb5445cb8b6cdd1a4196b54b67">addLiveOut</a>(RVLocs[i].getLocReg());
+<a name="l04331"></a>04331 }
+<a name="l04332"></a>04332
+<a name="l04333"></a>04333 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Flag;
+<a name="l04334"></a>04334
+<a name="l04335"></a>04335 <span class="comment">// Copy the result values into the output registers.</span>
+<a name="l04336"></a>04336 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != RVLocs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); ++i) {
+<a name="l04337"></a>04337 <a class="code" href="classllvm_1_1CCValAssign.html" title="CCValAssign - Represent assignment of one arg/retval to a location.">CCValAssign</a> &VA = RVLocs[i];
+<a name="l04338"></a>04338 assert(VA.<a class="code" href="classllvm_1_1CCValAssign.html#afcfd7d2322b397d0d55a4595dea52e3c">isRegLoc</a>() && <span class="stringliteral">"Can only return in registers!"</span>);
+<a name="l04339"></a>04339
+<a name="l04340"></a>04340 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Arg = OutVals[i];
+<a name="l04341"></a>04341
+<a name="l04342"></a>04342 <span class="keywordflow">switch</span> (VA.<a class="code" href="classllvm_1_1CCValAssign.html#a8c820cdb37337e8b0bd55e0fcd39dd18">getLocInfo</a>()) {
+<a name="l04343"></a>04343 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unknown loc info!"</span>);
+<a name="l04344"></a>04344 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45a8b73d77b9e54663c2e80a48d0917dce1">CCValAssign::Full</a>: <span class="keywordflow">break</span>;
+<a name="l04345"></a>04345 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45acc07b91f72979f3e9b12c2e0c355db46">CCValAssign::AExt</a>:
+<a name="l04346"></a>04346 Arg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a27d5d8ef82302b739ba3ca8be1a5513d" title="ANY_EXTEND - Used for integer types. The high bits are undefined.">ISD::ANY_EXTEND</a>, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae59804b87136d0ddf452a25b025b768c">getLocVT</a>(), Arg);
+<a name="l04347"></a>04347 <span class="keywordflow">break</span>;
+<a name="l04348"></a>04348 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45a807a4e133d7f743724d809a3f3875aa2">CCValAssign::ZExt</a>:
+<a name="l04349"></a>04349 Arg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a93fdf85eff945f1a668b4915a051453e" title="ZERO_EXTEND - Used for integer types, zeroing the new bits.">ISD::ZERO_EXTEND</a>, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae59804b87136d0ddf452a25b025b768c">getLocVT</a>(), Arg);
+<a name="l04350"></a>04350 <span class="keywordflow">break</span>;
+<a name="l04351"></a>04351 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1CCValAssign.html#a2b78fd53da0b5df7bc4eacf7df556a45a7fd25972cdb14499949c7726499e0cb6">CCValAssign::SExt</a>:
+<a name="l04352"></a>04352 Arg = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a5183f3d72924bc7c77ba8d3f5de9f602">ISD::SIGN_EXTEND</a>, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#ae59804b87136d0ddf452a25b025b768c">getLocVT</a>(), Arg);
+<a name="l04353"></a>04353 <span class="keywordflow">break</span>;
+<a name="l04354"></a>04354 }
+<a name="l04355"></a>04355
+<a name="l04356"></a>04356 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a64720b4e2b3deb1f80177f31d1843691">getCopyToReg</a>(Chain, dl, VA.<a class="code" href="classllvm_1_1CCValAssign.html#a5cb182c203efa2f1fc4797fb76b15daf">getLocReg</a>(), Arg, Flag);
+<a name="l04357"></a>04357 Flag = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l04358"></a>04358 }
+<a name="l04359"></a>04359
+<a name="l04360"></a>04360 <span class="keywordflow">if</span> (Flag.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>())
+<a name="l04361"></a>04361 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aca057f3b5880594ff9a4ef1750a61924" title="Return with a flag operand, matched by 'blr'.">PPCISD::RET_FLAG</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Chain, Flag);
+<a name="l04362"></a>04362 <span class="keywordflow">else</span>
+<a name="l04363"></a>04363 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aca057f3b5880594ff9a4ef1750a61924" title="Return with a flag operand, matched by 'blr'.">PPCISD::RET_FLAG</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Chain);
+<a name="l04364"></a>04364 }
+<a name="l04365"></a>04365
+<a name="l04366"></a>04366 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerSTACKRESTORE(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l04367"></a>04367 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a> &Subtarget)<span class="keyword"> const </span>{
+<a name="l04368"></a>04368 <span class="comment">// When we pop the dynamic allocation we need to restore the SP link.</span>
+<a name="l04369"></a>04369 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04370"></a>04370
+<a name="l04371"></a>04371 <span class="comment">// Get the corect type for pointers.</span>
+<a name="l04372"></a>04372 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l04373"></a>04373
+<a name="l04374"></a>04374 <span class="comment">// Construct the stack pointer operand.</span>
+<a name="l04375"></a>04375 <span class="keywordtype">bool</span> isPPC64 = Subtarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>();
+<a name="l04376"></a>04376 <span class="keywordtype">unsigned</span> SP = isPPC64 ? PPC::X1 : PPC::R1;
+<a name="l04377"></a>04377 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> StackPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(SP, PtrVT);
+<a name="l04378"></a>04378
+<a name="l04379"></a>04379 <span class="comment">// Get the operands for the STACKRESTORE.</span>
+<a name="l04380"></a>04380 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l04381"></a>04381 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SaveSP = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l04382"></a>04382
+<a name="l04383"></a>04383 <span class="comment">// Load the old link SP.</span>
+<a name="l04384"></a>04384 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LoadLinkSP = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(PtrVT, dl, Chain, StackPtr,
+<a name="l04385"></a>04385 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04386"></a>04386 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04387"></a>04387
+<a name="l04388"></a>04388 <span class="comment">// Restore the stack pointer.</span>
+<a name="l04389"></a>04389 Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a64720b4e2b3deb1f80177f31d1843691">getCopyToReg</a>(LoadLinkSP.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1), dl, SP, SaveSP);
+<a name="l04390"></a>04390
+<a name="l04391"></a>04391 <span class="comment">// Store the old link SP.</span>
+<a name="l04392"></a>04392 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(Chain, dl, LoadLinkSP, StackPtr, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04393"></a>04393 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04394"></a>04394 }
+<a name="l04395"></a>04395
+<a name="l04396"></a>04396
+<a name="l04397"></a>04397
+<a name="l04398"></a>04398 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l04399"></a>04399 PPCTargetLowering::getReturnAddrFrameIndex(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> & DAG)<span class="keyword"> const </span>{
+<a name="l04400"></a>04400 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l04401"></a>04401 <span class="keywordtype">bool</span> isPPC64 = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>();
+<a name="l04402"></a>04402 <span class="keywordtype">bool</span> isDarwinABI = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#a27ef3d0113fbcca318c3ed2a86116932">isDarwinABI</a>();
+<a name="l04403"></a>04403 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l04404"></a>04404
+<a name="l04405"></a>04405 <span class="comment">// Get current frame pointer save index. The users of this index will be</span>
+<a name="l04406"></a>04406 <span class="comment">// primarily DYNALLOC instructions.</span>
+<a name="l04407"></a>04407 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l04408"></a>04408 <span class="keywordtype">int</span> RASI = FI-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a5466153a2e22cd8f1cfcf2dd77d1b3d7">getReturnAddrSaveIndex</a>();
+<a name="l04409"></a>04409
+<a name="l04410"></a>04410 <span class="comment">// If the frame pointer save index hasn't been defined yet.</span>
+<a name="l04411"></a>04411 <span class="keywordflow">if</span> (!RASI) {
+<a name="l04412"></a>04412 <span class="comment">// Find out what the fix offset of the frame pointer save area.</span>
+<a name="l04413"></a>04413 <span class="keywordtype">int</span> LROffset = <a class="code" href="classllvm_1_1PPCFrameLowering.html#a4d69526bf0c3ba246820af1cbc25effe">PPCFrameLowering::getReturnSaveOffset</a>(isPPC64, isDarwinABI);
+<a name="l04414"></a>04414 <span class="comment">// Allocate the frame index for frame pointer save area.</span>
+<a name="l04415"></a>04415 RASI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(isPPC64? 8 : 4, LROffset, <span class="keyword">true</span>);
+<a name="l04416"></a>04416 <span class="comment">// Save the result.</span>
+<a name="l04417"></a>04417 FI-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a19957a6465c3a7a64ada8dfdec4d5aba">setReturnAddrSaveIndex</a>(RASI);
+<a name="l04418"></a>04418 }
+<a name="l04419"></a>04419 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(RASI, PtrVT);
+<a name="l04420"></a>04420 }
+<a name="l04421"></a>04421
+<a name="l04422"></a>04422 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>
+<a name="l04423"></a>04423 PPCTargetLowering::getFramePointerFrameIndex(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> & DAG)<span class="keyword"> const </span>{
+<a name="l04424"></a>04424 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l04425"></a>04425 <span class="keywordtype">bool</span> isPPC64 = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>();
+<a name="l04426"></a>04426 <span class="keywordtype">bool</span> isDarwinABI = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#a27ef3d0113fbcca318c3ed2a86116932">isDarwinABI</a>();
+<a name="l04427"></a>04427 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l04428"></a>04428
+<a name="l04429"></a>04429 <span class="comment">// Get current frame pointer save index. The users of this index will be</span>
+<a name="l04430"></a>04430 <span class="comment">// primarily DYNALLOC instructions.</span>
+<a name="l04431"></a>04431 <a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a> *FI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1PPCFunctionInfo.html">PPCFunctionInfo</a>>();
+<a name="l04432"></a>04432 <span class="keywordtype">int</span> FPSI = FI-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#a0071b1186435b05bd312b95e5d09a50b">getFramePointerSaveIndex</a>();
+<a name="l04433"></a>04433
+<a name="l04434"></a>04434 <span class="comment">// If the frame pointer save index hasn't been defined yet.</span>
+<a name="l04435"></a>04435 <span class="keywordflow">if</span> (!FPSI) {
+<a name="l04436"></a>04436 <span class="comment">// Find out what the fix offset of the frame pointer save area.</span>
+<a name="l04437"></a>04437 <span class="keywordtype">int</span> FPOffset = <a class="code" href="classllvm_1_1PPCFrameLowering.html#a97db50b03c1daa960e8d2e0fcb9e9f8b">PPCFrameLowering::getFramePointerSaveOffset</a>(isPPC64,
+<a name="l04438"></a>04438 isDarwinABI);
+<a name="l04439"></a>04439
+<a name="l04440"></a>04440 <span class="comment">// Allocate the frame index for frame pointer save area.</span>
+<a name="l04441"></a>04441 FPSI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a511de1ba76de77289749f82883fada4b">CreateFixedObject</a>(isPPC64? 8 : 4, FPOffset, <span class="keyword">true</span>);
+<a name="l04442"></a>04442 <span class="comment">// Save the result.</span>
+<a name="l04443"></a>04443 FI-><a class="code" href="classllvm_1_1PPCFunctionInfo.html#afd615e1f3b75dc847e26ce6bd4932a56">setFramePointerSaveIndex</a>(FPSI);
+<a name="l04444"></a>04444 }
+<a name="l04445"></a>04445 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FPSI, PtrVT);
+<a name="l04446"></a>04446 }
+<a name="l04447"></a>04447
+<a name="l04448"></a>04448 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerDYNAMIC_STACKALLOC(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l04449"></a>04449 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l04450"></a>04450 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a> &Subtarget)<span class="keyword"> const </span>{
+<a name="l04451"></a>04451 <span class="comment">// Get the inputs.</span>
+<a name="l04452"></a>04452 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l04453"></a>04453 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Size = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l04454"></a>04454 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04455"></a>04455
+<a name="l04456"></a>04456 <span class="comment">// Get the corect type for pointers.</span>
+<a name="l04457"></a>04457 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l04458"></a>04458 <span class="comment">// Negate the size.</span>
+<a name="l04459"></a>04459 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> NegSize = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>, dl, PtrVT,
+<a name="l04460"></a>04460 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(0, PtrVT), Size);
+<a name="l04461"></a>04461 <span class="comment">// Construct a node for the frame pointer save index.</span>
+<a name="l04462"></a>04462 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FPSIdx = getFramePointerFrameIndex(DAG);
+<a name="l04463"></a>04463 <span class="comment">// Build a DYNALLOC node.</span>
+<a name="l04464"></a>04464 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[3] = { Chain, NegSize, FPSIdx };
+<a name="l04465"></a>04465 <a class="code" href="structllvm_1_1SDVTList.html">SDVTList</a> VTs = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a196c23d6cb4d768d037970f1f35bbf66">getVTList</a>(PtrVT, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>);
+<a name="l04466"></a>04466 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a098fa0d2b0ca58b9d504edb6a164ee54">PPCISD::DYNALLOC</a>, dl, VTs, Ops, 3);
+<a name="l04467"></a>04467 }
+<a name="l04468"></a>04468 <span class="comment"></span>
+<a name="l04469"></a>04469 <span class="comment">/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when</span>
+<a name="l04470"></a>04470 <span class="comment">/// possible.</span>
+<a name="l04471"></a>04471 <span class="comment"></span><a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerSELECT_CC(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l04472"></a>04472 <span class="comment">// Not FP? Not a fsel.</span>
+<a name="l04473"></a>04473 <span class="keywordflow">if</span> (!Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#afc4147764cdb5599c67f747813ef9bdc" title="isFloatingPoint - Return true if this is a FP, or a vector FP type.">isFloatingPoint</a>() ||
+<a name="l04474"></a>04474 !Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#afc4147764cdb5599c67f747813ef9bdc" title="isFloatingPoint - Return true if this is a FP, or a vector FP type.">isFloatingPoint</a>())
+<a name="l04475"></a>04475 <span class="keywordflow">return</span> Op;
+<a name="l04476"></a>04476
+<a name="l04477"></a>04477 <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> CC = cast<CondCodeSDNode>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(4))-><span class="keyword">get</span>();
+<a name="l04478"></a>04478
+<a name="l04479"></a>04479 <span class="comment">// Cannot handle SETEQ/SETNE.</span>
+<a name="l04480"></a>04480 <span class="keywordflow">if</span> (CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a> || CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>) <span class="keywordflow">return</span> Op;
+<a name="l04481"></a>04481
+<a name="l04482"></a>04482 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ResVT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04483"></a>04483 <a class="code" href="structllvm_1_1EVT.html">EVT</a> CmpVT = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04484"></a>04484 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), RHS = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l04485"></a>04485 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TV = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2), FV = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(3);
+<a name="l04486"></a>04486 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04487"></a>04487
+<a name="l04488"></a>04488 <span class="comment">// If the RHS of the comparison is a 0.0, we don't need to do the</span>
+<a name="l04489"></a>04489 <span class="comment">// subtraction at all.</span>
+<a name="l04490"></a>04490 <span class="keywordflow">if</span> (<a class="code" href="PPCISelLowering_8cpp.html#af4674b301fdc98e0a729a8d4690e45f2" title="isFloatingPointZero - Return true if this is 0.0 or -0.0.">isFloatingPointZero</a>(RHS))
+<a name="l04491"></a>04491 <span class="keywordflow">switch</span> (CC) {
+<a name="l04492"></a>04492 <span class="keywordflow">default</span>: <span class="keywordflow">break</span>; <span class="comment">// SETUO etc aren't handled by fsel.</span>
+<a name="l04493"></a>04493 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>:
+<a name="l04494"></a>04494 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>:
+<a name="l04495"></a>04495 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(TV, FV); <span class="comment">// fsel is natively setge, swap operands for setlt</span>
+<a name="l04496"></a>04496 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac7bb30d4918c1ee9dd208083154e109f">ISD::SETOGE</a>:
+<a name="l04497"></a>04497 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a7f47862de23f7210f88ccf98ae1efbe4">ISD::SETGE</a>:
+<a name="l04498"></a>04498 <span class="keywordflow">if</span> (LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) <span class="comment">// Comparison is always 64-bits</span>
+<a name="l04499"></a>04499 LHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aadfdefcb133a7f0262a05934aba8ce5d" title="X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.">ISD::FP_EXTEND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, LHS);
+<a name="l04500"></a>04500 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aed93fe593cbca270b48f14bc00c5d73a">PPCISD::FSEL</a>, dl, ResVT, LHS, TV, FV);
+<a name="l04501"></a>04501 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>:
+<a name="l04502"></a>04502 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a5ad12b466e3a5900d0c307b301465d25">ISD::SETGT</a>:
+<a name="l04503"></a>04503 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(TV, FV); <span class="comment">// fsel is natively setge, swap operands for setlt</span>
+<a name="l04504"></a>04504 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a1febf3bac2f3d7d98ec19f1ff5c385ea">ISD::SETOLE</a>:
+<a name="l04505"></a>04505 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ab49f81c2ecbbff3d0fbe55dd46353774">ISD::SETLE</a>:
+<a name="l04506"></a>04506 <span class="keywordflow">if</span> (LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) <span class="comment">// Comparison is always 64-bits</span>
+<a name="l04507"></a>04507 LHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aadfdefcb133a7f0262a05934aba8ce5d" title="X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.">ISD::FP_EXTEND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, LHS);
+<a name="l04508"></a>04508 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aed93fe593cbca270b48f14bc00c5d73a">PPCISD::FSEL</a>, dl, ResVT,
+<a name="l04509"></a>04509 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6d26c45c040d8f85d577a5f645261d1a">ISD::FNEG</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, LHS), TV, FV);
+<a name="l04510"></a>04510 }
+<a name="l04511"></a>04511
+<a name="l04512"></a>04512 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Cmp;
+<a name="l04513"></a>04513 <span class="keywordflow">switch</span> (CC) {
+<a name="l04514"></a>04514 <span class="keywordflow">default</span>: <span class="keywordflow">break</span>; <span class="comment">// SETUO etc aren't handled by fsel.</span>
+<a name="l04515"></a>04515 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>:
+<a name="l04516"></a>04516 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>:
+<a name="l04517"></a>04517 Cmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a2852a5b6baa80b1589a46737210a8cad">ISD::FSUB</a>, dl, CmpVT, LHS, RHS);
+<a name="l04518"></a>04518 <span class="keywordflow">if</span> (Cmp.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) <span class="comment">// Comparison is always 64-bits</span>
+<a name="l04519"></a>04519 Cmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aadfdefcb133a7f0262a05934aba8ce5d" title="X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.">ISD::FP_EXTEND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, Cmp);
+<a name="l04520"></a>04520 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aed93fe593cbca270b48f14bc00c5d73a">PPCISD::FSEL</a>, dl, ResVT, Cmp, FV, TV);
+<a name="l04521"></a>04521 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac7bb30d4918c1ee9dd208083154e109f">ISD::SETOGE</a>:
+<a name="l04522"></a>04522 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a7f47862de23f7210f88ccf98ae1efbe4">ISD::SETGE</a>:
+<a name="l04523"></a>04523 Cmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a2852a5b6baa80b1589a46737210a8cad">ISD::FSUB</a>, dl, CmpVT, LHS, RHS);
+<a name="l04524"></a>04524 <span class="keywordflow">if</span> (Cmp.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) <span class="comment">// Comparison is always 64-bits</span>
+<a name="l04525"></a>04525 Cmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aadfdefcb133a7f0262a05934aba8ce5d" title="X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.">ISD::FP_EXTEND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, Cmp);
+<a name="l04526"></a>04526 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aed93fe593cbca270b48f14bc00c5d73a">PPCISD::FSEL</a>, dl, ResVT, Cmp, TV, FV);
+<a name="l04527"></a>04527 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>:
+<a name="l04528"></a>04528 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a5ad12b466e3a5900d0c307b301465d25">ISD::SETGT</a>:
+<a name="l04529"></a>04529 Cmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a2852a5b6baa80b1589a46737210a8cad">ISD::FSUB</a>, dl, CmpVT, RHS, LHS);
+<a name="l04530"></a>04530 <span class="keywordflow">if</span> (Cmp.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) <span class="comment">// Comparison is always 64-bits</span>
+<a name="l04531"></a>04531 Cmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aadfdefcb133a7f0262a05934aba8ce5d" title="X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.">ISD::FP_EXTEND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, Cmp);
+<a name="l04532"></a>04532 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aed93fe593cbca270b48f14bc00c5d73a">PPCISD::FSEL</a>, dl, ResVT, Cmp, FV, TV);
+<a name="l04533"></a>04533 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a1febf3bac2f3d7d98ec19f1ff5c385ea">ISD::SETOLE</a>:
+<a name="l04534"></a>04534 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ab49f81c2ecbbff3d0fbe55dd46353774">ISD::SETLE</a>:
+<a name="l04535"></a>04535 Cmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a2852a5b6baa80b1589a46737210a8cad">ISD::FSUB</a>, dl, CmpVT, RHS, LHS);
+<a name="l04536"></a>04536 <span class="keywordflow">if</span> (Cmp.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) <span class="comment">// Comparison is always 64-bits</span>
+<a name="l04537"></a>04537 Cmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aadfdefcb133a7f0262a05934aba8ce5d" title="X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.">ISD::FP_EXTEND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, Cmp);
+<a name="l04538"></a>04538 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aed93fe593cbca270b48f14bc00c5d73a">PPCISD::FSEL</a>, dl, ResVT, Cmp, TV, FV);
+<a name="l04539"></a>04539 }
+<a name="l04540"></a>04540 <span class="keywordflow">return</span> Op;
+<a name="l04541"></a>04541 }
+<a name="l04542"></a>04542
+<a name="l04543"></a>04543 <span class="comment">// FIXME: Split this code up when LegalizeDAGTypes lands.</span>
+<a name="l04544"></a>04544 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerFP_TO_INT(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l04545"></a>04545 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl)<span class="keyword"> const </span>{
+<a name="l04546"></a>04546 assert(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#afc4147764cdb5599c67f747813ef9bdc" title="isFloatingPoint - Return true if this is a FP, or a vector FP type.">isFloatingPoint</a>());
+<a name="l04547"></a>04547 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Src = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l04548"></a>04548 <span class="keywordflow">if</span> (Src.getValueType() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>)
+<a name="l04549"></a>04549 Src = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aadfdefcb133a7f0262a05934aba8ce5d" title="X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.">ISD::FP_EXTEND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, Src);
+<a name="l04550"></a>04550
+<a name="l04551"></a>04551 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp;
+<a name="l04552"></a>04552 <span class="keywordflow">switch</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l04553"></a>04553 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unhandled FP_TO_INT type in custom expander!"</span>);
+<a name="l04554"></a>04554 <span class="keywordflow">case</span> MVT::i32:
+<a name="l04555"></a>04555 Tmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>()==<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac3f8f8d8437c64b2e2e9f978e2707210">ISD::FP_TO_SINT</a> ? <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2a6e33357fd46c15294432ab65adecec">PPCISD::FCTIWZ</a> :
+<a name="l04556"></a>04556 <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2a79156c141fbb0faadd358c767b906b">PPCISD::FCTIDZ</a>,
+<a name="l04557"></a>04557 dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>, Src);
+<a name="l04558"></a>04558 <span class="keywordflow">break</span>;
+<a name="l04559"></a>04559 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>:
+<a name="l04560"></a>04560 Tmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2a79156c141fbb0faadd358c767b906b">PPCISD::FCTIDZ</a>, dl, MVT::f64, Src);
+<a name="l04561"></a>04561 <span class="keywordflow">break</span>;
+<a name="l04562"></a>04562 }
+<a name="l04563"></a>04563
+<a name="l04564"></a>04564 <span class="comment">// Convert the FP value to an int value through memory.</span>
+<a name="l04565"></a>04565 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3de9644ea2dd81453acf760bd2c1f921">CreateStackTemporary</a>(MVT::f64);
+<a name="l04566"></a>04566
+<a name="l04567"></a>04567 <span class="comment">// Emit a store to the stack slot.</span>
+<a name="l04568"></a>04568 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad755b1a25cf0c4507d5f615f64471ae9">getEntryNode</a>(), dl, Tmp, FIPtr,
+<a name="l04569"></a>04569 <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04570"></a>04570
+<a name="l04571"></a>04571 <span class="comment">// Result is a load from the stack slot. If loading 4 bytes, make sure to</span>
+<a name="l04572"></a>04572 <span class="comment">// add in a bias.</span>
+<a name="l04573"></a>04573 <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == MVT::i32)
+<a name="l04574"></a>04574 FIPtr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, FIPtr.getValueType(), FIPtr,
+<a name="l04575"></a>04575 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(4, FIPtr.getValueType()));
+<a name="l04576"></a>04576 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), dl, Chain, FIPtr, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04577"></a>04577 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04578"></a>04578 }
+<a name="l04579"></a>04579
+<a name="l04580"></a>04580 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerSINT_TO_FP(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l04581"></a>04581 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l04582"></a>04582 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04583"></a>04583 <span class="comment">// Don't handle ppc_fp128 here; let it be lowered to a libcall.</span>
+<a name="l04584"></a>04584 <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() != <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a> && Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() != MVT::f64)
+<a name="l04585"></a>04585 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l04586"></a>04586
+<a name="l04587"></a>04587 <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>) {
+<a name="l04588"></a>04588 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SINT = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l04589"></a>04589 <span class="comment">// When converting to single-precision, we actually need to convert</span>
+<a name="l04590"></a>04590 <span class="comment">// to double-precision first and then round to single-precision.</span>
+<a name="l04591"></a>04591 <span class="comment">// To avoid double-rounding effects during that operation, we have</span>
+<a name="l04592"></a>04592 <span class="comment">// to prepare the input operand. Bits that might be truncated when</span>
+<a name="l04593"></a>04593 <span class="comment">// converting to double-precision are replaced by a bit that won't</span>
+<a name="l04594"></a>04594 <span class="comment">// be lost at this stage, but is below the single-precision rounding</span>
+<a name="l04595"></a>04595 <span class="comment">// position.</span>
+<a name="l04596"></a>04596 <span class="comment">//</span>
+<a name="l04597"></a>04597 <span class="comment">// However, if -enable-unsafe-fp-math is in effect, accept double</span>
+<a name="l04598"></a>04598 <span class="comment">// rounding to avoid the extra overhead.</span>
+<a name="l04599"></a>04599 <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a> &&
+<a name="l04600"></a>04600 !DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a6b60694d1d9d7f634e7638856898e20d">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ab1fb67187fc37e569cc5171cbebba873">Options</a>.<a class="code" href="classllvm_1_1TargetOptions.html#a0544e2966374684ff74255e5a4290fa7">UnsafeFPMath</a>) {
+<a name="l04601"></a>04601
+<a name="l04602"></a>04602 <span class="comment">// Twiddle input to make sure the low 11 bits are zero. (If this</span>
+<a name="l04603"></a>04603 <span class="comment">// is the case, we are guaranteed the value will fit into the 53 bit</span>
+<a name="l04604"></a>04604 <span class="comment">// mantissa of an IEEE double-precision value without rounding.)</span>
+<a name="l04605"></a>04605 <span class="comment">// If any of those low 11 bits were not zero originally, make sure</span>
+<a name="l04606"></a>04606 <span class="comment">// bit 12 (value 2048) is set instead, so that the final rounding</span>
+<a name="l04607"></a>04607 <span class="comment">// to single-precision gets the correct result.</span>
+<a name="l04608"></a>04608 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Round = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l04609"></a>04609 SINT, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(2047, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>));
+<a name="l04610"></a>04610 Round = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l04611"></a>04611 Round, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(2047, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>));
+<a name="l04612"></a>04612 Round = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, Round, SINT);
+<a name="l04613"></a>04613 Round = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l04614"></a>04614 Round, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(-2048, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>));
+<a name="l04615"></a>04615
+<a name="l04616"></a>04616 <span class="comment">// However, we cannot use that value unconditionally: if the magnitude</span>
+<a name="l04617"></a>04617 <span class="comment">// of the input value is small, the bit-twiddling we did above might</span>
+<a name="l04618"></a>04618 <span class="comment">// end up visibly changing the output. Fortunately, in that case, we</span>
+<a name="l04619"></a>04619 <span class="comment">// don't need to twiddle bits since the original input will convert</span>
+<a name="l04620"></a>04620 <span class="comment">// exactly to double-precision floating-point already. Therefore,</span>
+<a name="l04621"></a>04621 <span class="comment">// construct a conditional to use the original value if the top 11</span>
+<a name="l04622"></a>04622 <span class="comment">// bits are all sign-bit copies, and use the rounded value computed</span>
+<a name="l04623"></a>04623 <span class="comment">// above otherwise.</span>
+<a name="l04624"></a>04624 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Cond = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4a055321c361a0f6ee77ed764730ffc1">ISD::SRA</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l04625"></a>04625 SINT, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(53, MVT::i32));
+<a name="l04626"></a>04626 Cond = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l04627"></a>04627 Cond, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>));
+<a name="l04628"></a>04628 Cond = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#aaec11804ffd22ad34531e88df8fb2aa1">getSetCC</a>(dl, MVT::i32,
+<a name="l04629"></a>04629 Cond, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>), <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>);
+<a name="l04630"></a>04630
+<a name="l04631"></a>04631 SINT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78d0f198115bfe3331ab7cfcf7a40a97">ISD::SELECT</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, Cond, Round, SINT);
+<a name="l04632"></a>04632 }
+<a name="l04633"></a>04633 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1tgtok.html#abbc5259d649363016626e2529fabe0c5a3c0710aa6b054662f67b480712fa2b95">Bits</a> = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, MVT::f64, SINT);
+<a name="l04634"></a>04634 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FP = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a7d46bc38a9f3de58adde307de9c5e892">PPCISD::FCFID</a>, dl, MVT::f64, Bits);
+<a name="l04635"></a>04635 <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>)
+<a name="l04636"></a>04636 FP = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110adaf9a3cb5c2ef5eb713bd6bf4ae23aeb">ISD::FP_ROUND</a>, dl,
+<a name="l04637"></a>04637 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, FP, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(0));
+<a name="l04638"></a>04638 <span class="keywordflow">return</span> FP;
+<a name="l04639"></a>04639 }
+<a name="l04640"></a>04640
+<a name="l04641"></a>04641 assert(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == MVT::i32 &&
+<a name="l04642"></a>04642 <span class="stringliteral">"Unhandled SINT_TO_FP type in custom expander!"</span>);
+<a name="l04643"></a>04643 <span class="comment">// Since we only generate this in 64-bit mode, we can take advantage of</span>
+<a name="l04644"></a>04644 <span class="comment">// 64-bit registers. In particular, sign extend the input value into the</span>
+<a name="l04645"></a>04645 <span class="comment">// 64-bit register with extsw, store the WHOLE 64-bit value into the stack</span>
+<a name="l04646"></a>04646 <span class="comment">// then lfd it and fcfid it.</span>
+<a name="l04647"></a>04647 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l04648"></a>04648 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *FrameInfo = MF.getFrameInfo();
+<a name="l04649"></a>04649 <span class="keywordtype">int</span> FrameIdx = FrameInfo-><a class="code" href="classllvm_1_1MachineFrameInfo.html#acd4dd34a1fe2579c4e2a349aacd76bcb">CreateStackObject</a>(8, 8, <span class="keyword">false</span>);
+<a name="l04650"></a>04650 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l04651"></a>04651 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIdx = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FrameIdx, PtrVT);
+<a name="l04652"></a>04652
+<a name="l04653"></a>04653 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ext64 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a73d5538a5e8e3868aa25756ec31a416f">PPCISD::EXTSW_32</a>, dl, MVT::i32,
+<a name="l04654"></a>04654 Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0));
+<a name="l04655"></a>04655
+<a name="l04656"></a>04656 <span class="comment">// STD the extended value into the stack slot.</span>
+<a name="l04657"></a>04657 <a class="code" href="classllvm_1_1MachineMemOperand.html">MachineMemOperand</a> *MMO =
+<a name="l04658"></a>04658 MF.getMachineMemOperand(<a class="code" href="structllvm_1_1MachinePointerInfo.html#acb492206d94d8f8179f797d4c7966ba9">MachinePointerInfo::getFixedStack</a>(FrameIdx),
+<a name="l04659"></a>04659 <a class="code" href="classllvm_1_1MachineMemOperand.html#a120d548151541463831d22519eb9b82faed357b1367bc90a56fefa4d1b0e17374" title="The memory access writes data.">MachineMemOperand::MOStore</a>, 8, 8);
+<a name="l04660"></a>04660 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad755b1a25cf0c4507d5f615f64471ae9">getEntryNode</a>(), Ext64, FIdx };
+<a name="l04661"></a>04661 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store =
+<a name="l04662"></a>04662 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac123f0b2781ce2747a842340915902a7">getMemIntrinsicNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1ad5156dad8dfe65002aeb13e0da5c5e" title="STD_32 - This is the STD instruction for use with "32-bit" registers.">PPCISD::STD_32</a>, dl, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a196c23d6cb4d768d037970f1f35bbf66">getVTList</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>),
+<a name="l04663"></a>04663 Ops, 4, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, MMO);
+<a name="l04664"></a>04664 <span class="comment">// Load the value as a double.</span>
+<a name="l04665"></a>04665 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ld = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(MVT::f64, dl, Store, FIdx, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04666"></a>04666 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04667"></a>04667
+<a name="l04668"></a>04668 <span class="comment">// FCFID it and return it.</span>
+<a name="l04669"></a>04669 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FP = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a7d46bc38a9f3de58adde307de9c5e892">PPCISD::FCFID</a>, dl, MVT::f64, Ld);
+<a name="l04670"></a>04670 <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>)
+<a name="l04671"></a>04671 FP = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110adaf9a3cb5c2ef5eb713bd6bf4ae23aeb">ISD::FP_ROUND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>, FP, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(0));
+<a name="l04672"></a>04672 <span class="keywordflow">return</span> FP;
+<a name="l04673"></a>04673 }
+<a name="l04674"></a>04674
+<a name="l04675"></a>04675 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerFLT_ROUNDS_(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l04676"></a>04676 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l04677"></a>04677 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04678"></a>04678 <span class="comment">/*</span>
+<a name="l04679"></a>04679 <span class="comment"> The rounding mode is in bits 30:31 of FPSR, and has the following</span>
+<a name="l04680"></a>04680 <span class="comment"> settings:</span>
+<a name="l04681"></a>04681 <span class="comment"> 00 Round to nearest</span>
+<a name="l04682"></a>04682 <span class="comment"> 01 Round to 0</span>
+<a name="l04683"></a>04683 <span class="comment"> 10 Round to +inf</span>
+<a name="l04684"></a>04684 <span class="comment"> 11 Round to -inf</span>
+<a name="l04685"></a>04685 <span class="comment"></span>
+<a name="l04686"></a>04686 <span class="comment"> FLT_ROUNDS, on the other hand, expects the following:</span>
+<a name="l04687"></a>04687 <span class="comment"> -1 Undefined</span>
+<a name="l04688"></a>04688 <span class="comment"> 0 Round to 0</span>
+<a name="l04689"></a>04689 <span class="comment"> 1 Round to nearest</span>
+<a name="l04690"></a>04690 <span class="comment"> 2 Round to +inf</span>
+<a name="l04691"></a>04691 <span class="comment"> 3 Round to -inf</span>
+<a name="l04692"></a>04692 <span class="comment"></span>
+<a name="l04693"></a>04693 <span class="comment"> To perform the conversion, we do:</span>
+<a name="l04694"></a>04694 <span class="comment"> ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))</span>
+<a name="l04695"></a>04695 <span class="comment"> */</span>
+<a name="l04696"></a>04696
+<a name="l04697"></a>04697 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>();
+<a name="l04698"></a>04698 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04699"></a>04699 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a848b46af8fabd1ab34b28adbc3665609">getTargetLoweringInfo</a>().<a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l04700"></a>04700 std::vector<EVT> NodeTys;
+<a name="l04701"></a>04701 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MFFSreg, InFlag;
+<a name="l04702"></a>04702
+<a name="l04703"></a>04703 <span class="comment">// Save FP Control Word to register</span>
+<a name="l04704"></a>04704 NodeTys.push_back(MVT::f64); <span class="comment">// return register</span>
+<a name="l04705"></a>04705 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>); <span class="comment">// unused in this context</span>
+<a name="l04706"></a>04706 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aab6a046c536c71121190fefd548d6b25">PPCISD::MFFS</a>, dl, NodeTys, &InFlag, 0);
+<a name="l04707"></a>04707
+<a name="l04708"></a>04708 <span class="comment">// Save FP register to stack slot</span>
+<a name="l04709"></a>04709 <span class="keywordtype">int</span> SSFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#acd4dd34a1fe2579c4e2a349aacd76bcb">CreateStackObject</a>(8, 8, <span class="keyword">false</span>);
+<a name="l04710"></a>04710 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> StackSlot = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(SSFI, PtrVT);
+<a name="l04711"></a>04711 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad755b1a25cf0c4507d5f615f64471ae9">getEntryNode</a>(), dl, Chain,
+<a name="l04712"></a>04712 StackSlot, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(), <span class="keyword">false</span>, <span class="keyword">false</span>,0);
+<a name="l04713"></a>04713
+<a name="l04714"></a>04714 <span class="comment">// Load FP Control Word from low 32 bits of stack slot.</span>
+<a name="l04715"></a>04715 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Four = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(4, PtrVT);
+<a name="l04716"></a>04716 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Addr = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, PtrVT, StackSlot, Four);
+<a name="l04717"></a>04717 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CWD = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(MVT::i32, dl, Store, Addr, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l04718"></a>04718 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l04719"></a>04719
+<a name="l04720"></a>04720 <span class="comment">// Transform as necessary</span>
+<a name="l04721"></a>04721 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CWD1 =
+<a name="l04722"></a>04722 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, dl, MVT::i32,
+<a name="l04723"></a>04723 CWD, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(3, MVT::i32));
+<a name="l04724"></a>04724 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CWD2 =
+<a name="l04725"></a>04725 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>, dl, MVT::i32,
+<a name="l04726"></a>04726 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, dl, MVT::i32,
+<a name="l04727"></a>04727 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a>, dl, MVT::i32,
+<a name="l04728"></a>04728 CWD, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(3, MVT::i32)),
+<a name="l04729"></a>04729 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(3, MVT::i32)),
+<a name="l04730"></a>04730 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, MVT::i32));
+<a name="l04731"></a>04731
+<a name="l04732"></a>04732 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RetVal =
+<a name="l04733"></a>04733 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a>, dl, MVT::i32, CWD1, CWD2);
+<a name="l04734"></a>04734
+<a name="l04735"></a>04735 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>((VT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>() < 16 ?
+<a name="l04736"></a>04736 <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae690127648393001a7d5b93dc23da7b3" title="TRUNCATE - Completely drop the high bits.">ISD::TRUNCATE</a> : <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a93fdf85eff945f1a668b4915a051453e" title="ZERO_EXTEND - Used for integer types, zeroing the new bits.">ISD::ZERO_EXTEND</a>), dl, VT, RetVal);
+<a name="l04737"></a>04737 }
+<a name="l04738"></a>04738
+<a name="l04739"></a>04739 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerSHL_PARTS(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l04740"></a>04740 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04741"></a>04741 <span class="keywordtype">unsigned</span> BitWidth = VT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>();
+<a name="l04742"></a>04742 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04743"></a>04743 assert(Op.<a class="code" href="classllvm_1_1SDValue.html#a5f0447ef8ec128563ad131b76e5062bd">getNumOperands</a>() == 3 &&
+<a name="l04744"></a>04744 VT == Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() &&
+<a name="l04745"></a>04745 <span class="stringliteral">"Unexpected SHL!"</span>);
+<a name="l04746"></a>04746
+<a name="l04747"></a>04747 <span class="comment">// Expand into a bunch of logical ops. Note that these ops</span>
+<a name="l04748"></a>04748 <span class="comment">// depend on the PPC behavior for oversized shift amounts.</span>
+<a name="l04749"></a>04749 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ab68a439987d870da623ed899fa47344c" title="Low address component (lower 16)">Lo</a> = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l04750"></a>04750 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Hi = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l04751"></a>04751 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Amt = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2);
+<a name="l04752"></a>04752 <a class="code" href="structllvm_1_1EVT.html">EVT</a> AmtVT = Amt.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04753"></a>04753
+<a name="l04754"></a>04754 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp1 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>, dl, AmtVT,
+<a name="l04755"></a>04755 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(BitWidth, AmtVT), Amt);
+<a name="l04756"></a>04756 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp2 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a56a6aa00c6f25ef2c1f51277099a78a4">PPCISD::SHL</a>, dl, VT, Hi, Amt);
+<a name="l04757"></a>04757 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp3 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1b0abca17bd696928f9399acfd3d1522">PPCISD::SRL</a>, dl, VT, Lo, Tmp1);
+<a name="l04758"></a>04758 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp4 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a> , dl, VT, Tmp2, Tmp3);
+<a name="l04759"></a>04759 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp5 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, AmtVT, Amt,
+<a name="l04760"></a>04760 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(-BitWidth, AmtVT));
+<a name="l04761"></a>04761 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp6 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a56a6aa00c6f25ef2c1f51277099a78a4">PPCISD::SHL</a>, dl, VT, Lo, Tmp5);
+<a name="l04762"></a>04762 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutHi = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a>, dl, VT, Tmp4, Tmp6);
+<a name="l04763"></a>04763 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutLo = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a56a6aa00c6f25ef2c1f51277099a78a4">PPCISD::SHL</a>, dl, VT, Lo, Amt);
+<a name="l04764"></a>04764 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutOps[] = { OutLo, OutHi };
+<a name="l04765"></a>04765 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ae98f282ed976b9caab89388dd3c40209" title="getMergeValues - Create a MERGE_VALUES node from the given operands.">getMergeValues</a>(OutOps, 2, dl);
+<a name="l04766"></a>04766 }
+<a name="l04767"></a>04767
+<a name="l04768"></a>04768 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerSRL_PARTS(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l04769"></a>04769 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04770"></a>04770 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04771"></a>04771 <span class="keywordtype">unsigned</span> BitWidth = VT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>();
+<a name="l04772"></a>04772 assert(Op.<a class="code" href="classllvm_1_1SDValue.html#a5f0447ef8ec128563ad131b76e5062bd">getNumOperands</a>() == 3 &&
+<a name="l04773"></a>04773 VT == Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() &&
+<a name="l04774"></a>04774 <span class="stringliteral">"Unexpected SRL!"</span>);
+<a name="l04775"></a>04775
+<a name="l04776"></a>04776 <span class="comment">// Expand into a bunch of logical ops. Note that these ops</span>
+<a name="l04777"></a>04777 <span class="comment">// depend on the PPC behavior for oversized shift amounts.</span>
+<a name="l04778"></a>04778 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Lo = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l04779"></a>04779 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Hi = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l04780"></a>04780 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Amt = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2);
+<a name="l04781"></a>04781 <a class="code" href="structllvm_1_1EVT.html">EVT</a> AmtVT = Amt.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04782"></a>04782
+<a name="l04783"></a>04783 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp1 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>, dl, AmtVT,
+<a name="l04784"></a>04784 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(BitWidth, AmtVT), Amt);
+<a name="l04785"></a>04785 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp2 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1b0abca17bd696928f9399acfd3d1522">PPCISD::SRL</a>, dl, VT, Lo, Amt);
+<a name="l04786"></a>04786 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp3 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a56a6aa00c6f25ef2c1f51277099a78a4">PPCISD::SHL</a>, dl, VT, Hi, Tmp1);
+<a name="l04787"></a>04787 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp4 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a>, dl, VT, Tmp2, Tmp3);
+<a name="l04788"></a>04788 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp5 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, AmtVT, Amt,
+<a name="l04789"></a>04789 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(-BitWidth, AmtVT));
+<a name="l04790"></a>04790 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp6 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1b0abca17bd696928f9399acfd3d1522">PPCISD::SRL</a>, dl, VT, Hi, Tmp5);
+<a name="l04791"></a>04791 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutLo = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a>, dl, VT, Tmp4, Tmp6);
+<a name="l04792"></a>04792 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutHi = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1b0abca17bd696928f9399acfd3d1522">PPCISD::SRL</a>, dl, VT, Hi, Amt);
+<a name="l04793"></a>04793 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutOps[] = { OutLo, OutHi };
+<a name="l04794"></a>04794 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ae98f282ed976b9caab89388dd3c40209" title="getMergeValues - Create a MERGE_VALUES node from the given operands.">getMergeValues</a>(OutOps, 2, dl);
+<a name="l04795"></a>04795 }
+<a name="l04796"></a>04796
+<a name="l04797"></a>04797 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerSRA_PARTS(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l04798"></a>04798 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04799"></a>04799 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04800"></a>04800 <span class="keywordtype">unsigned</span> BitWidth = VT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>();
+<a name="l04801"></a>04801 assert(Op.<a class="code" href="classllvm_1_1SDValue.html#a5f0447ef8ec128563ad131b76e5062bd">getNumOperands</a>() == 3 &&
+<a name="l04802"></a>04802 VT == Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() &&
+<a name="l04803"></a>04803 <span class="stringliteral">"Unexpected SRA!"</span>);
+<a name="l04804"></a>04804
+<a name="l04805"></a>04805 <span class="comment">// Expand into a bunch of logical ops, followed by a select_cc.</span>
+<a name="l04806"></a>04806 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Lo = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l04807"></a>04807 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Hi = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l04808"></a>04808 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Amt = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2);
+<a name="l04809"></a>04809 <a class="code" href="structllvm_1_1EVT.html">EVT</a> AmtVT = Amt.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04810"></a>04810
+<a name="l04811"></a>04811 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp1 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>, dl, AmtVT,
+<a name="l04812"></a>04812 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(BitWidth, AmtVT), Amt);
+<a name="l04813"></a>04813 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp2 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1b0abca17bd696928f9399acfd3d1522">PPCISD::SRL</a>, dl, VT, Lo, Amt);
+<a name="l04814"></a>04814 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp3 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a56a6aa00c6f25ef2c1f51277099a78a4">PPCISD::SHL</a>, dl, VT, Hi, Tmp1);
+<a name="l04815"></a>04815 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp4 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a>, dl, VT, Tmp2, Tmp3);
+<a name="l04816"></a>04816 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp5 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, AmtVT, Amt,
+<a name="l04817"></a>04817 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(-BitWidth, AmtVT));
+<a name="l04818"></a>04818 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp6 = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aad0d80bf5cf5a07b271e4357ed436f62">PPCISD::SRA</a>, dl, VT, Hi, Tmp5);
+<a name="l04819"></a>04819 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutHi = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aad0d80bf5cf5a07b271e4357ed436f62">PPCISD::SRA</a>, dl, VT, Hi, Amt);
+<a name="l04820"></a>04820 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutLo = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a8a480174e95bd2d3b18f6e63cbd98de4">getSelectCC</a>(dl, Tmp5, DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(0, AmtVT),
+<a name="l04821"></a>04821 Tmp4, Tmp6, <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ab49f81c2ecbbff3d0fbe55dd46353774">ISD::SETLE</a>);
+<a name="l04822"></a>04822 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OutOps[] = { OutLo, OutHi };
+<a name="l04823"></a>04823 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ae98f282ed976b9caab89388dd3c40209" title="getMergeValues - Create a MERGE_VALUES node from the given operands.">getMergeValues</a>(OutOps, 2, dl);
+<a name="l04824"></a>04824 }
+<a name="l04825"></a>04825
+<a name="l04826"></a>04826 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l04827"></a>04827 <span class="comment">// Vector related lowering.</span>
+<a name="l04828"></a>04828 <span class="comment">//</span>
+<a name="l04829"></a>04829 <span class="comment"></span>
+<a name="l04830"></a>04830 <span class="comment">/// BuildSplatI - Build a canonical splati of Val with an element size of</span>
+<a name="l04831"></a>04831 <span class="comment">/// SplatSize. Cast the result to VT.</span>
+<a name="l04832"></a><a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">04832</a> <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(<span class="keywordtype">int</span> Val, <span class="keywordtype">unsigned</span> SplatSize, <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT,
+<a name="l04833"></a>04833 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG, <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl) {
+<a name="l04834"></a>04834 assert(Val >= -16 && Val <= 15 && <span class="stringliteral">"vsplti is out of range!"</span>);
+<a name="l04835"></a>04835
+<a name="l04836"></a>04836 <span class="keyword">static</span> <span class="keyword">const</span> <a class="code" href="structllvm_1_1EVT.html">EVT</a> VTys[] = { <span class="comment">// canonical VT to use for each size.</span>
+<a name="l04837"></a>04837 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>
+<a name="l04838"></a>04838 };
+<a name="l04839"></a>04839
+<a name="l04840"></a>04840 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ReqVT = VT != <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a> ? VT : VTys[SplatSize-1];
+<a name="l04841"></a>04841
+<a name="l04842"></a>04842 <span class="comment">// Force vspltis[hw] -1 to vspltisb -1 to canonicalize.</span>
+<a name="l04843"></a>04843 <span class="keywordflow">if</span> (Val == -1)
+<a name="l04844"></a>04844 SplatSize = 1;
+<a name="l04845"></a>04845
+<a name="l04846"></a>04846 <a class="code" href="structllvm_1_1EVT.html">EVT</a> CanonicalVT = VTys[SplatSize-1];
+<a name="l04847"></a>04847
+<a name="l04848"></a>04848 <span class="comment">// Build a canonical splat for this value.</span>
+<a name="l04849"></a>04849 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Elt = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(Val, MVT::i32);
+<a name="l04850"></a>04850 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> Ops;
+<a name="l04851"></a>04851 Ops.<a class="code" href="classllvm_1_1SmallVectorImpl.html#a465f75c78f1dc551152248c9f203b88d">assign</a>(CanonicalVT.<a class="code" href="structllvm_1_1EVT.html#a42bca41d2438197c12b6db2c710a959c">getVectorNumElements</a>(), Elt);
+<a name="l04852"></a>04852 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Res = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>, dl, CanonicalVT,
+<a name="l04853"></a>04853 &Ops[0], Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l04854"></a>04854 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, ReqVT, Res);
+<a name="l04855"></a>04855 }
+<a name="l04856"></a>04856 <span class="comment"></span>
+<a name="l04857"></a>04857 <span class="comment">/// BuildIntrinsicOp - Return a binary operator intrinsic node with the</span>
+<a name="l04858"></a>04858 <span class="comment">/// specified intrinsic ID.</span>
+<a name="l04859"></a><a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">04859</a> <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(<span class="keywordtype">unsigned</span> IID, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHS,
+<a name="l04860"></a>04860 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG, <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl,
+<a name="l04861"></a>04861 <a class="code" href="structllvm_1_1EVT.html">EVT</a> DestVT = <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>) {
+<a name="l04862"></a>04862 <span class="keywordflow">if</span> (DestVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>) DestVT = LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04863"></a>04863 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac771b9cda3b889242d457cc4d9b2159c">ISD::INTRINSIC_WO_CHAIN</a>, dl, DestVT,
+<a name="l04864"></a>04864 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(IID, MVT::i32), LHS, RHS);
+<a name="l04865"></a>04865 }
+<a name="l04866"></a>04866 <span class="comment"></span>
+<a name="l04867"></a>04867 <span class="comment">/// BuildIntrinsicOp - Return a ternary operator intrinsic node with the</span>
+<a name="l04868"></a>04868 <span class="comment">/// specified intrinsic ID.</span>
+<a name="l04869"></a><a class="code" href="PPCISelLowering_8cpp.html#a233c143b1499680a75a60e9e8c8da3e2">04869</a> <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(<span class="keywordtype">unsigned</span> IID, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op1,
+<a name="l04870"></a>04870 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op2, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l04871"></a>04871 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <a class="code" href="structllvm_1_1EVT.html">EVT</a> DestVT = <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>) {
+<a name="l04872"></a>04872 <span class="keywordflow">if</span> (DestVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>) DestVT = Op0.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l04873"></a>04873 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac771b9cda3b889242d457cc4d9b2159c">ISD::INTRINSIC_WO_CHAIN</a>, dl, DestVT,
+<a name="l04874"></a>04874 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(IID, MVT::i32), Op0, Op1, Op2);
+<a name="l04875"></a>04875 }
+<a name="l04876"></a>04876
+<a name="l04877"></a>04877 <span class="comment"></span>
+<a name="l04878"></a>04878 <span class="comment">/// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified</span>
+<a name="l04879"></a>04879 <span class="comment">/// amount. The result has the specified value type.</span>
+<a name="l04880"></a><a class="code" href="PPCISelLowering_8cpp.html#a34ce47cb789e13973af0ebdba9a6046b">04880</a> <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="PPCISelLowering_8cpp.html#a34ce47cb789e13973af0ebdba9a6046b">BuildVSLDOI</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHS, <span class="keywordtype">unsigned</span> Amt,
+<a name="l04881"></a>04881 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG, <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl) {
+<a name="l04882"></a>04882 <span class="comment">// Force LHS/RHS to be the right type.</span>
+<a name="l04883"></a>04883 LHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, LHS);
+<a name="l04884"></a>04884 RHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, RHS);
+<a name="l04885"></a>04885
+<a name="l04886"></a>04886 <span class="keywordtype">int</span> Ops[16];
+<a name="l04887"></a>04887 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 16; ++i)
+<a name="l04888"></a>04888 Ops[i] = i + Amt;
+<a name="l04889"></a>04889 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> T = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a28fe416bbaf4208d45b23705a3deb168">getVectorShuffle</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, dl, LHS, RHS, Ops);
+<a name="l04890"></a>04890 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, VT, T);
+<a name="l04891"></a>04891 }
+<a name="l04892"></a>04892
+<a name="l04893"></a>04893 <span class="comment">// If this is a case we can't handle, return null and let the default</span>
+<a name="l04894"></a>04894 <span class="comment">// expansion code take care of it. If we CAN select this case, and if it</span>
+<a name="l04895"></a>04895 <span class="comment">// selects to a single instruction, return Op. Otherwise, if we can codegen</span>
+<a name="l04896"></a>04896 <span class="comment">// this case more efficiently than a constant pool load, lower it to the</span>
+<a name="l04897"></a>04897 <span class="comment">// sequence of ops that should be used.</span>
+<a name="l04898"></a>04898 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerBUILD_VECTOR(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l04899"></a>04899 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l04900"></a>04900 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l04901"></a>04901 <a class="code" href="classllvm_1_1BuildVectorSDNode.html">BuildVectorSDNode</a> *BVN = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1BuildVectorSDNode.html">BuildVectorSDNode</a>>(Op.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>());
+<a name="l04902"></a>04902 assert(BVN != 0 && <span class="stringliteral">"Expected a BuildVectorSDNode in LowerBUILD_VECTOR"</span>);
+<a name="l04903"></a>04903
+<a name="l04904"></a>04904 <span class="comment">// Check if this is a splat of a constant value.</span>
+<a name="l04905"></a>04905 <a class="code" href="classllvm_1_1APInt.html" title="Class for arbitrary precision integers.">APInt</a> APSplatBits, APSplatUndef;
+<a name="l04906"></a>04906 <span class="keywordtype">unsigned</span> SplatBitSize;
+<a name="l04907"></a>04907 <span class="keywordtype">bool</span> HasAnyUndefs;
+<a name="l04908"></a>04908 <span class="keywordflow">if</span> (! BVN-><a class="code" href="classllvm_1_1BuildVectorSDNode.html#a0d1aedc8b57ec58e82db037ccb38c2a2">isConstantSplat</a>(APSplatBits, APSplatUndef, SplatBitSize,
+<a name="l04909"></a>04909 HasAnyUndefs, 0, <span class="keyword">true</span>) || SplatBitSize > 32)
+<a name="l04910"></a>04910 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l04911"></a>04911
+<a name="l04912"></a>04912 <span class="keywordtype">unsigned</span> SplatBits = APSplatBits.<a class="code" href="classllvm_1_1APInt.html#a7dc983ebf0eb2d255fa90a67063c72e2" title="Get zero extended value.">getZExtValue</a>();
+<a name="l04913"></a>04913 <span class="keywordtype">unsigned</span> SplatUndef = APSplatUndef.<a class="code" href="classllvm_1_1APInt.html#a7dc983ebf0eb2d255fa90a67063c72e2" title="Get zero extended value.">getZExtValue</a>();
+<a name="l04914"></a>04914 <span class="keywordtype">unsigned</span> SplatSize = SplatBitSize / 8;
+<a name="l04915"></a>04915
+<a name="l04916"></a>04916 <span class="comment">// First, handle single instruction cases.</span>
+<a name="l04917"></a>04917
+<a name="l04918"></a>04918 <span class="comment">// All zeros?</span>
+<a name="l04919"></a>04919 <span class="keywordflow">if</span> (SplatBits == 0) {
+<a name="l04920"></a>04920 <span class="comment">// Canonicalize all zero vectors to be v4i32.</span>
+<a name="l04921"></a>04921 <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() != <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a> || HasAnyUndefs) {
+<a name="l04922"></a>04922 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Z = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(0, MVT::i32);
+<a name="l04923"></a>04923 Z = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, Z, Z, Z, Z);
+<a name="l04924"></a>04924 Op = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Z);
+<a name="l04925"></a>04925 }
+<a name="l04926"></a>04926 <span class="keywordflow">return</span> Op;
+<a name="l04927"></a>04927 }
+<a name="l04928"></a>04928
+<a name="l04929"></a>04929 <span class="comment">// If the sign extended value is in the range [-16,15], use VSPLTI[bhw].</span>
+<a name="l04930"></a>04930 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
+<a name="l04931"></a>04931 (32-SplatBitSize));
+<a name="l04932"></a>04932 <span class="keywordflow">if</span> (SextVal >= -16 && SextVal <= 15)
+<a name="l04933"></a>04933 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(SextVal, SplatSize, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), DAG, dl);
+<a name="l04934"></a>04934
+<a name="l04935"></a>04935
+<a name="l04936"></a>04936 <span class="comment">// Two instruction sequences.</span>
+<a name="l04937"></a>04937
+<a name="l04938"></a>04938 <span class="comment">// If this value is in the range [-32,30] and is even, use:</span>
+<a name="l04939"></a>04939 <span class="comment">// tmp = VSPLTI[bhw], result = add tmp, tmp</span>
+<a name="l04940"></a>04940 <span class="keywordflow">if</span> (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
+<a name="l04941"></a>04941 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Res = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(SextVal >> 1, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l04942"></a>04942 Res = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, Res.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Res, Res);
+<a name="l04943"></a>04943 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Res);
+<a name="l04944"></a>04944 }
+<a name="l04945"></a>04945
+<a name="l04946"></a>04946 <span class="comment">// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is</span>
+<a name="l04947"></a>04947 <span class="comment">// 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important</span>
+<a name="l04948"></a>04948 <span class="comment">// for fneg/fabs.</span>
+<a name="l04949"></a>04949 <span class="keywordflow">if</span> (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
+<a name="l04950"></a>04950 <span class="comment">// Make -1 and vspltisw -1:</span>
+<a name="l04951"></a>04951 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OnesV = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(-1, 4, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, DAG, dl);
+<a name="l04952"></a>04952
+<a name="l04953"></a>04953 <span class="comment">// Make the VSLW intrinsic, computing 0x8000_0000.</span>
+<a name="l04954"></a>04954 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Res = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(Intrinsic::ppc_altivec_vslw, OnesV,
+<a name="l04955"></a>04955 OnesV, DAG, dl);
+<a name="l04956"></a>04956
+<a name="l04957"></a>04957 <span class="comment">// xor by OnesV to invert it.</span>
+<a name="l04958"></a>04958 Res = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, Res, OnesV);
+<a name="l04959"></a>04959 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Res);
+<a name="l04960"></a>04960 }
+<a name="l04961"></a>04961
+<a name="l04962"></a>04962 <span class="comment">// Check to see if this is a wide variety of vsplti*, binop self cases.</span>
+<a name="l04963"></a>04963 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">signed</span> <span class="keywordtype">char</span> SplatCsts[] = {
+<a name="l04964"></a>04964 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
+<a name="l04965"></a>04965 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
+<a name="l04966"></a>04966 };
+<a name="l04967"></a>04967
+<a name="l04968"></a>04968 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> idx = 0; idx < <a class="code" href="namespacellvm.html#a370ed0e0f2bb66d17cd13f84be54e867" title="Find the length of an array.">array_lengthof</a>(SplatCsts); ++idx) {
+<a name="l04969"></a>04969 <span class="comment">// Indirect through the SplatCsts array so that we favor 'vsplti -1' for</span>
+<a name="l04970"></a>04970 <span class="comment">// cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'</span>
+<a name="l04971"></a>04971 <span class="keywordtype">int</span> i = SplatCsts[idx];
+<a name="l04972"></a>04972
+<a name="l04973"></a>04973 <span class="comment">// Figure out what shift amount will be used by altivec if shifted by i in</span>
+<a name="l04974"></a>04974 <span class="comment">// this splat size.</span>
+<a name="l04975"></a>04975 <span class="keywordtype">unsigned</span> TypeShiftAmt = i & (SplatBitSize-1);
+<a name="l04976"></a>04976
+<a name="l04977"></a>04977 <span class="comment">// vsplti + shl self.</span>
+<a name="l04978"></a>04978 <span class="keywordflow">if</span> (SextVal == (<span class="keywordtype">int</span>)((<a class="code" href="classunsigned.html">unsigned</a>)i << TypeShiftAmt)) {
+<a name="l04979"></a>04979 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Res = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(i, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l04980"></a>04980 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">unsigned</span> IIDs[] = { <span class="comment">// Intrinsic to use for each size.</span>
+<a name="l04981"></a>04981 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
+<a name="l04982"></a>04982 Intrinsic::ppc_altivec_vslw
+<a name="l04983"></a>04983 };
+<a name="l04984"></a>04984 Res = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(IIDs[SplatSize-1], Res, Res, DAG, dl);
+<a name="l04985"></a>04985 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Res);
+<a name="l04986"></a>04986 }
+<a name="l04987"></a>04987
+<a name="l04988"></a>04988 <span class="comment">// vsplti + srl self.</span>
+<a name="l04989"></a>04989 <span class="keywordflow">if</span> (SextVal == (<span class="keywordtype">int</span>)((<a class="code" href="classunsigned.html">unsigned</a>)i >> TypeShiftAmt)) {
+<a name="l04990"></a>04990 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Res = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(i, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l04991"></a>04991 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">unsigned</span> IIDs[] = { <span class="comment">// Intrinsic to use for each size.</span>
+<a name="l04992"></a>04992 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
+<a name="l04993"></a>04993 Intrinsic::ppc_altivec_vsrw
+<a name="l04994"></a>04994 };
+<a name="l04995"></a>04995 Res = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(IIDs[SplatSize-1], Res, Res, DAG, dl);
+<a name="l04996"></a>04996 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Res);
+<a name="l04997"></a>04997 }
+<a name="l04998"></a>04998
+<a name="l04999"></a>04999 <span class="comment">// vsplti + sra self.</span>
+<a name="l05000"></a>05000 <span class="keywordflow">if</span> (SextVal == (<span class="keywordtype">int</span>)((<a class="code" href="classunsigned.html">unsigned</a>)i >> TypeShiftAmt)) {
+<a name="l05001"></a>05001 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Res = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(i, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l05002"></a>05002 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">unsigned</span> IIDs[] = { <span class="comment">// Intrinsic to use for each size.</span>
+<a name="l05003"></a>05003 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
+<a name="l05004"></a>05004 Intrinsic::ppc_altivec_vsraw
+<a name="l05005"></a>05005 };
+<a name="l05006"></a>05006 Res = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(IIDs[SplatSize-1], Res, Res, DAG, dl);
+<a name="l05007"></a>05007 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Res);
+<a name="l05008"></a>05008 }
+<a name="l05009"></a>05009
+<a name="l05010"></a>05010 <span class="comment">// vsplti + rol self.</span>
+<a name="l05011"></a>05011 <span class="keywordflow">if</span> (SextVal == (<span class="keywordtype">int</span>)(((<a class="code" href="classunsigned.html">unsigned</a>)i << TypeShiftAmt) |
+<a name="l05012"></a>05012 ((<a class="code" href="classunsigned.html">unsigned</a>)i >> (SplatBitSize-TypeShiftAmt)))) {
+<a name="l05013"></a>05013 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Res = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(i, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l05014"></a>05014 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">unsigned</span> IIDs[] = { <span class="comment">// Intrinsic to use for each size.</span>
+<a name="l05015"></a>05015 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
+<a name="l05016"></a>05016 Intrinsic::ppc_altivec_vrlw
+<a name="l05017"></a>05017 };
+<a name="l05018"></a>05018 Res = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(IIDs[SplatSize-1], Res, Res, DAG, dl);
+<a name="l05019"></a>05019 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Res);
+<a name="l05020"></a>05020 }
+<a name="l05021"></a>05021
+<a name="l05022"></a>05022 <span class="comment">// t = vsplti c, result = vsldoi t, t, 1</span>
+<a name="l05023"></a>05023 <span class="keywordflow">if</span> (SextVal == (<span class="keywordtype">int</span>)(((<a class="code" href="classunsigned.html">unsigned</a>)i << 8) | (i < 0 ? 0xFF : 0))) {
+<a name="l05024"></a>05024 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> T = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(i, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, DAG, dl);
+<a name="l05025"></a>05025 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a34ce47cb789e13973af0ebdba9a6046b">BuildVSLDOI</a>(T, T, 1, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), DAG, dl);
+<a name="l05026"></a>05026 }
+<a name="l05027"></a>05027 <span class="comment">// t = vsplti c, result = vsldoi t, t, 2</span>
+<a name="l05028"></a>05028 <span class="keywordflow">if</span> (SextVal == (<span class="keywordtype">int</span>)(((<a class="code" href="classunsigned.html">unsigned</a>)i << 16) | (i < 0 ? 0xFFFF : 0))) {
+<a name="l05029"></a>05029 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> T = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(i, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, DAG, dl);
+<a name="l05030"></a>05030 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a34ce47cb789e13973af0ebdba9a6046b">BuildVSLDOI</a>(T, T, 2, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), DAG, dl);
+<a name="l05031"></a>05031 }
+<a name="l05032"></a>05032 <span class="comment">// t = vsplti c, result = vsldoi t, t, 3</span>
+<a name="l05033"></a>05033 <span class="keywordflow">if</span> (SextVal == (<span class="keywordtype">int</span>)(((<a class="code" href="classunsigned.html">unsigned</a>)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
+<a name="l05034"></a>05034 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> T = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(i, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, DAG, dl);
+<a name="l05035"></a>05035 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a34ce47cb789e13973af0ebdba9a6046b">BuildVSLDOI</a>(T, T, 3, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), DAG, dl);
+<a name="l05036"></a>05036 }
+<a name="l05037"></a>05037 }
+<a name="l05038"></a>05038
+<a name="l05039"></a>05039 <span class="comment">// Three instruction sequences.</span>
+<a name="l05040"></a>05040
+<a name="l05041"></a>05041 <span class="comment">// Odd, in range [17,31]: (vsplti C)-(vsplti -16).</span>
+<a name="l05042"></a>05042 <span class="keywordflow">if</span> (SextVal >= 0 && SextVal <= 31) {
+<a name="l05043"></a>05043 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(SextVal-16, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l05044"></a>05044 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHS = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(-16, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l05045"></a>05045 LHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>, dl, LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), LHS, RHS);
+<a name="l05046"></a>05046 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), LHS);
+<a name="l05047"></a>05047 }
+<a name="l05048"></a>05048 <span class="comment">// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).</span>
+<a name="l05049"></a>05049 <span class="keywordflow">if</span> (SextVal >= -31 && SextVal <= 0) {
+<a name="l05050"></a>05050 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(SextVal+16, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l05051"></a>05051 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHS = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(-16, SplatSize, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, DAG, dl);
+<a name="l05052"></a>05052 LHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), LHS, RHS);
+<a name="l05053"></a>05053 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), LHS);
+<a name="l05054"></a>05054 }
+<a name="l05055"></a>05055
+<a name="l05056"></a>05056 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>();
+<a name="l05057"></a>05057 }
+<a name="l05058"></a>05058 <span class="comment"></span>
+<a name="l05059"></a>05059 <span class="comment">/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit</span>
+<a name="l05060"></a>05060 <span class="comment">/// the specified operations to build the shuffle.</span>
+<a name="l05061"></a><a class="code" href="PPCISelLowering_8cpp.html#a6dd11f903a726446c4039f51b884894c">05061</a> <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="PPCISelLowering_8cpp.html#a6dd11f903a726446c4039f51b884894c">GeneratePerfectShuffle</a>(<span class="keywordtype">unsigned</span> PFEntry, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS,
+<a name="l05062"></a>05062 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHS, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG,
+<a name="l05063"></a>05063 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl) {
+<a name="l05064"></a>05064 <span class="keywordtype">unsigned</span> OpNum = (PFEntry >> 26) & 0x0F;
+<a name="l05065"></a>05065 <span class="keywordtype">unsigned</span> LHSID = (PFEntry >> 13) & ((1 << 13)-1);
+<a name="l05066"></a>05066 <span class="keywordtype">unsigned</span> RHSID = (PFEntry >> 0) & ((1 << 13)-1);
+<a name="l05067"></a>05067
+<a name="l05068"></a>05068 <span class="keyword">enum</span> {
+<a name="l05069"></a>05069 OP_COPY = 0, <span class="comment">// Copy, used for things like <u,u,u,3> to say it is <0,1,2,3></span>
+<a name="l05070"></a>05070 OP_VMRGHW,
+<a name="l05071"></a>05071 OP_VMRGLW,
+<a name="l05072"></a>05072 OP_VSPLTISW0,
+<a name="l05073"></a>05073 OP_VSPLTISW1,
+<a name="l05074"></a>05074 OP_VSPLTISW2,
+<a name="l05075"></a>05075 OP_VSPLTISW3,
+<a name="l05076"></a>05076 OP_VSLDOI4,
+<a name="l05077"></a>05077 OP_VSLDOI8,
+<a name="l05078"></a>05078 OP_VSLDOI12
+<a name="l05079"></a>05079 };
+<a name="l05080"></a>05080
+<a name="l05081"></a>05081 <span class="keywordflow">if</span> (OpNum == OP_COPY) {
+<a name="l05082"></a>05082 <span class="keywordflow">if</span> (LHSID == (1*9+2)*9+3) <span class="keywordflow">return</span> LHS;
+<a name="l05083"></a>05083 assert(LHSID == ((4*9+5)*9+6)*9+7 && <span class="stringliteral">"Illegal OP_COPY!"</span>);
+<a name="l05084"></a>05084 <span class="keywordflow">return</span> RHS;
+<a name="l05085"></a>05085 }
+<a name="l05086"></a>05086
+<a name="l05087"></a>05087 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OpLHS, OpRHS;
+<a name="l05088"></a>05088 OpLHS = <a class="code" href="PPCISelLowering_8cpp.html#a6dd11f903a726446c4039f51b884894c">GeneratePerfectShuffle</a>(<a class="code" href="ARMPerfectShuffle_8h.html#a461cf57a94707854fa27b598c2e7826b">PerfectShuffleTable</a>[LHSID], LHS, RHS, DAG, dl);
+<a name="l05089"></a>05089 OpRHS = <a class="code" href="PPCISelLowering_8cpp.html#a6dd11f903a726446c4039f51b884894c">GeneratePerfectShuffle</a>(<a class="code" href="ARMPerfectShuffle_8h.html#a461cf57a94707854fa27b598c2e7826b">PerfectShuffleTable</a>[RHSID], LHS, RHS, DAG, dl);
+<a name="l05090"></a>05090
+<a name="l05091"></a>05091 <span class="keywordtype">int</span> ShufIdxs[16];
+<a name="l05092"></a>05092 <span class="keywordflow">switch</span> (OpNum) {
+<a name="l05093"></a>05093 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unknown i32 permute!"</span>);
+<a name="l05094"></a>05094 <span class="keywordflow">case</span> OP_VMRGHW:
+<a name="l05095"></a>05095 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
+<a name="l05096"></a>05096 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
+<a name="l05097"></a>05097 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
+<a name="l05098"></a>05098 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
+<a name="l05099"></a>05099 <span class="keywordflow">break</span>;
+<a name="l05100"></a>05100 <span class="keywordflow">case</span> OP_VMRGLW:
+<a name="l05101"></a>05101 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
+<a name="l05102"></a>05102 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
+<a name="l05103"></a>05103 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
+<a name="l05104"></a>05104 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
+<a name="l05105"></a>05105 <span class="keywordflow">break</span>;
+<a name="l05106"></a>05106 <span class="keywordflow">case</span> OP_VSPLTISW0:
+<a name="l05107"></a>05107 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 16; ++i)
+<a name="l05108"></a>05108 ShufIdxs[i] = (i&3)+0;
+<a name="l05109"></a>05109 <span class="keywordflow">break</span>;
+<a name="l05110"></a>05110 <span class="keywordflow">case</span> OP_VSPLTISW1:
+<a name="l05111"></a>05111 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 16; ++i)
+<a name="l05112"></a>05112 ShufIdxs[i] = (i&3)+4;
+<a name="l05113"></a>05113 <span class="keywordflow">break</span>;
+<a name="l05114"></a>05114 <span class="keywordflow">case</span> OP_VSPLTISW2:
+<a name="l05115"></a>05115 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 16; ++i)
+<a name="l05116"></a>05116 ShufIdxs[i] = (i&3)+8;
+<a name="l05117"></a>05117 <span class="keywordflow">break</span>;
+<a name="l05118"></a>05118 <span class="keywordflow">case</span> OP_VSPLTISW3:
+<a name="l05119"></a>05119 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 16; ++i)
+<a name="l05120"></a>05120 ShufIdxs[i] = (i&3)+12;
+<a name="l05121"></a>05121 <span class="keywordflow">break</span>;
+<a name="l05122"></a>05122 <span class="keywordflow">case</span> OP_VSLDOI4:
+<a name="l05123"></a>05123 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a34ce47cb789e13973af0ebdba9a6046b">BuildVSLDOI</a>(OpLHS, OpRHS, 4, OpLHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), DAG, dl);
+<a name="l05124"></a>05124 <span class="keywordflow">case</span> OP_VSLDOI8:
+<a name="l05125"></a>05125 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a34ce47cb789e13973af0ebdba9a6046b">BuildVSLDOI</a>(OpLHS, OpRHS, 8, OpLHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), DAG, dl);
+<a name="l05126"></a>05126 <span class="keywordflow">case</span> OP_VSLDOI12:
+<a name="l05127"></a>05127 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a34ce47cb789e13973af0ebdba9a6046b">BuildVSLDOI</a>(OpLHS, OpRHS, 12, OpLHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), DAG, dl);
+<a name="l05128"></a>05128 }
+<a name="l05129"></a>05129 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = OpLHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l05130"></a>05130 OpLHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, OpLHS);
+<a name="l05131"></a>05131 OpRHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, OpRHS);
+<a name="l05132"></a>05132 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> T = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a28fe416bbaf4208d45b23705a3deb168">getVectorShuffle</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, dl, OpLHS, OpRHS, ShufIdxs);
+<a name="l05133"></a>05133 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, VT, T);
+<a name="l05134"></a>05134 }
+<a name="l05135"></a>05135 <span class="comment"></span>
+<a name="l05136"></a>05136 <span class="comment">/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this</span>
+<a name="l05137"></a>05137 <span class="comment">/// is a shuffle we can handle in a single instruction, return it. Otherwise,</span>
+<a name="l05138"></a>05138 <span class="comment">/// return the code it can be lowered into. Worst case, it can always be</span>
+<a name="l05139"></a>05139 <span class="comment">/// lowered into a vperm.</span>
+<a name="l05140"></a>05140 <span class="comment"></span><a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerVECTOR_SHUFFLE(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l05141"></a>05141 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l05142"></a>05142 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l05143"></a>05143 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1 = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l05144"></a>05144 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a> = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l05145"></a>05145 <a class="code" href="classllvm_1_1ShuffleVectorSDNode.html">ShuffleVectorSDNode</a> *SVOp = cast<ShuffleVectorSDNode>(Op);
+<a name="l05146"></a>05146 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l05147"></a>05147
+<a name="l05148"></a>05148 <span class="comment">// Cases that are handled by instructions that take permute immediates</span>
+<a name="l05149"></a>05149 <span class="comment">// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be</span>
+<a name="l05150"></a>05150 <span class="comment">// selected by the instruction selector.</span>
+<a name="l05151"></a>05151 <span class="keywordflow">if</span> (V2.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7c6d8f265e9e16e5debdb9a536b55d3d" title="UNDEF - An undefined node.">ISD::UNDEF</a>) {
+<a name="l05152"></a>05152 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm_1_1PPC.html#adf912033ee385662cb4e40bd06206b67">PPC::isSplatShuffleMask</a>(SVOp, 1) ||
+<a name="l05153"></a>05153 <a class="code" href="namespacellvm_1_1PPC.html#adf912033ee385662cb4e40bd06206b67">PPC::isSplatShuffleMask</a>(SVOp, 2) ||
+<a name="l05154"></a>05154 <a class="code" href="namespacellvm_1_1PPC.html#adf912033ee385662cb4e40bd06206b67">PPC::isSplatShuffleMask</a>(SVOp, 4) ||
+<a name="l05155"></a>05155 <a class="code" href="namespacellvm_1_1PPC.html#ac08dd0e631069166e1c864b2bfbc05fe">PPC::isVPKUWUMShuffleMask</a>(SVOp, <span class="keyword">true</span>) ||
+<a name="l05156"></a>05156 <a class="code" href="namespacellvm_1_1PPC.html#a4546a80a0dc0cca8a263b80cc86122b0">PPC::isVPKUHUMShuffleMask</a>(SVOp, <span class="keyword">true</span>) ||
+<a name="l05157"></a>05157 <a class="code" href="namespacellvm_1_1PPC.html#a9fdffa1326c897a221fdba3dc82f0ec4">PPC::isVSLDOIShuffleMask</a>(SVOp, <span class="keyword">true</span>) != -1 ||
+<a name="l05158"></a>05158 <a class="code" href="namespacellvm_1_1PPC.html#ac5d667b47894c7546da2e58080fe2144">PPC::isVMRGLShuffleMask</a>(SVOp, 1, <span class="keyword">true</span>) ||
+<a name="l05159"></a>05159 <a class="code" href="namespacellvm_1_1PPC.html#ac5d667b47894c7546da2e58080fe2144">PPC::isVMRGLShuffleMask</a>(SVOp, 2, <span class="keyword">true</span>) ||
+<a name="l05160"></a>05160 <a class="code" href="namespacellvm_1_1PPC.html#ac5d667b47894c7546da2e58080fe2144">PPC::isVMRGLShuffleMask</a>(SVOp, 4, <span class="keyword">true</span>) ||
+<a name="l05161"></a>05161 <a class="code" href="namespacellvm_1_1PPC.html#a8ddfb467153e079ac0e9c4951b948887">PPC::isVMRGHShuffleMask</a>(SVOp, 1, <span class="keyword">true</span>) ||
+<a name="l05162"></a>05162 <a class="code" href="namespacellvm_1_1PPC.html#a8ddfb467153e079ac0e9c4951b948887">PPC::isVMRGHShuffleMask</a>(SVOp, 2, <span class="keyword">true</span>) ||
+<a name="l05163"></a>05163 <a class="code" href="namespacellvm_1_1PPC.html#a8ddfb467153e079ac0e9c4951b948887">PPC::isVMRGHShuffleMask</a>(SVOp, 4, <span class="keyword">true</span>)) {
+<a name="l05164"></a>05164 <span class="keywordflow">return</span> Op;
+<a name="l05165"></a>05165 }
+<a name="l05166"></a>05166 }
+<a name="l05167"></a>05167
+<a name="l05168"></a>05168 <span class="comment">// Altivec has a variety of "shuffle immediates" that take two vector inputs</span>
+<a name="l05169"></a>05169 <span class="comment">// and produce a fixed permutation. If any of these match, do not lower to</span>
+<a name="l05170"></a>05170 <span class="comment">// VPERM.</span>
+<a name="l05171"></a>05171 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm_1_1PPC.html#ac08dd0e631069166e1c864b2bfbc05fe">PPC::isVPKUWUMShuffleMask</a>(SVOp, <span class="keyword">false</span>) ||
+<a name="l05172"></a>05172 <a class="code" href="namespacellvm_1_1PPC.html#a4546a80a0dc0cca8a263b80cc86122b0">PPC::isVPKUHUMShuffleMask</a>(SVOp, <span class="keyword">false</span>) ||
+<a name="l05173"></a>05173 <a class="code" href="namespacellvm_1_1PPC.html#a9fdffa1326c897a221fdba3dc82f0ec4">PPC::isVSLDOIShuffleMask</a>(SVOp, <span class="keyword">false</span>) != -1 ||
+<a name="l05174"></a>05174 <a class="code" href="namespacellvm_1_1PPC.html#ac5d667b47894c7546da2e58080fe2144">PPC::isVMRGLShuffleMask</a>(SVOp, 1, <span class="keyword">false</span>) ||
+<a name="l05175"></a>05175 <a class="code" href="namespacellvm_1_1PPC.html#ac5d667b47894c7546da2e58080fe2144">PPC::isVMRGLShuffleMask</a>(SVOp, 2, <span class="keyword">false</span>) ||
+<a name="l05176"></a>05176 <a class="code" href="namespacellvm_1_1PPC.html#ac5d667b47894c7546da2e58080fe2144">PPC::isVMRGLShuffleMask</a>(SVOp, 4, <span class="keyword">false</span>) ||
+<a name="l05177"></a>05177 <a class="code" href="namespacellvm_1_1PPC.html#a8ddfb467153e079ac0e9c4951b948887">PPC::isVMRGHShuffleMask</a>(SVOp, 1, <span class="keyword">false</span>) ||
+<a name="l05178"></a>05178 <a class="code" href="namespacellvm_1_1PPC.html#a8ddfb467153e079ac0e9c4951b948887">PPC::isVMRGHShuffleMask</a>(SVOp, 2, <span class="keyword">false</span>) ||
+<a name="l05179"></a>05179 <a class="code" href="namespacellvm_1_1PPC.html#a8ddfb467153e079ac0e9c4951b948887">PPC::isVMRGHShuffleMask</a>(SVOp, 4, <span class="keyword">false</span>))
+<a name="l05180"></a>05180 <span class="keywordflow">return</span> Op;
+<a name="l05181"></a>05181
+<a name="l05182"></a>05182 <span class="comment">// Check to see if this is a shuffle of 4-byte values. If so, we can use our</span>
+<a name="l05183"></a>05183 <span class="comment">// perfect shuffle table to emit an optimal matching sequence.</span>
+<a name="l05184"></a>05184 <a class="code" href="classllvm_1_1ArrayRef.html">ArrayRef<int></a> PermMask = SVOp-><a class="code" href="classllvm_1_1ShuffleVectorSDNode.html#a6fe922cdd5bea1aee12d8719bac484d3">getMask</a>();
+<a name="l05185"></a>05185
+<a name="l05186"></a>05186 <span class="keywordtype">unsigned</span> PFIndexes[4];
+<a name="l05187"></a>05187 <span class="keywordtype">bool</span> isFourElementShuffle = <span class="keyword">true</span>;
+<a name="l05188"></a>05188 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 4 && isFourElementShuffle; ++i) { <span class="comment">// Element number</span>
+<a name="l05189"></a>05189 <span class="keywordtype">unsigned</span> EltNo = 8; <span class="comment">// Start out undef.</span>
+<a name="l05190"></a>05190 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j = 0; j != 4; ++j) { <span class="comment">// Intra-element byte.</span>
+<a name="l05191"></a>05191 <span class="keywordflow">if</span> (PermMask[i*4+j] < 0)
+<a name="l05192"></a>05192 <span class="keywordflow">continue</span>; <span class="comment">// Undef, ignore it.</span>
+<a name="l05193"></a>05193
+<a name="l05194"></a>05194 <span class="keywordtype">unsigned</span> ByteSource = PermMask[i*4+j];
+<a name="l05195"></a>05195 <span class="keywordflow">if</span> ((ByteSource & 3) != j) {
+<a name="l05196"></a>05196 isFourElementShuffle = <span class="keyword">false</span>;
+<a name="l05197"></a>05197 <span class="keywordflow">break</span>;
+<a name="l05198"></a>05198 }
+<a name="l05199"></a>05199
+<a name="l05200"></a>05200 <span class="keywordflow">if</span> (EltNo == 8) {
+<a name="l05201"></a>05201 EltNo = ByteSource/4;
+<a name="l05202"></a>05202 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (EltNo != ByteSource/4) {
+<a name="l05203"></a>05203 isFourElementShuffle = <span class="keyword">false</span>;
+<a name="l05204"></a>05204 <span class="keywordflow">break</span>;
+<a name="l05205"></a>05205 }
+<a name="l05206"></a>05206 }
+<a name="l05207"></a>05207 PFIndexes[i] = EltNo;
+<a name="l05208"></a>05208 }
+<a name="l05209"></a>05209
+<a name="l05210"></a>05210 <span class="comment">// If this shuffle can be expressed as a shuffle of 4-byte elements, use the</span>
+<a name="l05211"></a>05211 <span class="comment">// perfect shuffle vector to determine if it is cost effective to do this as</span>
+<a name="l05212"></a>05212 <span class="comment">// discrete instructions, or whether we should use a vperm.</span>
+<a name="l05213"></a>05213 <span class="keywordflow">if</span> (isFourElementShuffle) {
+<a name="l05214"></a>05214 <span class="comment">// Compute the index in the perfect shuffle table.</span>
+<a name="l05215"></a>05215 <span class="keywordtype">unsigned</span> PFTableIndex =
+<a name="l05216"></a>05216 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
+<a name="l05217"></a>05217
+<a name="l05218"></a>05218 <span class="keywordtype">unsigned</span> PFEntry = <a class="code" href="ARMPerfectShuffle_8h.html#a461cf57a94707854fa27b598c2e7826b">PerfectShuffleTable</a>[PFTableIndex];
+<a name="l05219"></a>05219 <span class="keywordtype">unsigned</span> Cost = (PFEntry >> 30);
+<a name="l05220"></a>05220
+<a name="l05221"></a>05221 <span class="comment">// Determining when to avoid vperm is tricky. Many things affect the cost</span>
+<a name="l05222"></a>05222 <span class="comment">// of vperm, particularly how many times the perm mask needs to be computed.</span>
+<a name="l05223"></a>05223 <span class="comment">// For example, if the perm mask can be hoisted out of a loop or is already</span>
+<a name="l05224"></a>05224 <span class="comment">// used (perhaps because there are multiple permutes with the same shuffle</span>
+<a name="l05225"></a>05225 <span class="comment">// mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of</span>
+<a name="l05226"></a>05226 <span class="comment">// the loop requires an extra register.</span>
+<a name="l05227"></a>05227 <span class="comment">//</span>
+<a name="l05228"></a>05228 <span class="comment">// As a compromise, we only emit discrete instructions if the shuffle can be</span>
+<a name="l05229"></a>05229 <span class="comment">// generated in 3 or fewer operations. When we have loop information</span>
+<a name="l05230"></a>05230 <span class="comment">// available, if this block is within a loop, we should avoid using vperm</span>
+<a name="l05231"></a>05231 <span class="comment">// for 3-operation perms and use a constant pool load instead.</span>
+<a name="l05232"></a>05232 <span class="keywordflow">if</span> (Cost < 3)
+<a name="l05233"></a>05233 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#a6dd11f903a726446c4039f51b884894c">GeneratePerfectShuffle</a>(PFEntry, V1, V2, DAG, dl);
+<a name="l05234"></a>05234 }
+<a name="l05235"></a>05235
+<a name="l05236"></a>05236 <span class="comment">// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant</span>
+<a name="l05237"></a>05237 <span class="comment">// vector that will get spilled to the constant pool.</span>
+<a name="l05238"></a>05238 <span class="keywordflow">if</span> (V2.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7c6d8f265e9e16e5debdb9a536b55d3d" title="UNDEF - An undefined node.">ISD::UNDEF</a>) V2 = V1;
+<a name="l05239"></a>05239
+<a name="l05240"></a>05240 <span class="comment">// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except</span>
+<a name="l05241"></a>05241 <span class="comment">// that it is in input element units, not in bytes. Convert now.</span>
+<a name="l05242"></a>05242 <a class="code" href="structllvm_1_1EVT.html">EVT</a> EltVT = V1.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#a3a07c062cc9330acd8e8c4e3930cbb25">getVectorElementType</a>();
+<a name="l05243"></a>05243 <span class="keywordtype">unsigned</span> BytesPerElement = EltVT.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8;
+<a name="l05244"></a>05244
+<a name="l05245"></a>05245 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 16></a> ResultMask;
+<a name="l05246"></a>05246 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
+<a name="l05247"></a>05247 <span class="keywordtype">unsigned</span> SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
+<a name="l05248"></a>05248
+<a name="l05249"></a>05249 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> j = 0; j != BytesPerElement; ++j)
+<a name="l05250"></a>05250 ResultMask.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(SrcElt*BytesPerElement+j,
+<a name="l05251"></a>05251 MVT::i32));
+<a name="l05252"></a>05252 }
+<a name="l05253"></a>05253
+<a name="l05254"></a>05254 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> VPermMask = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>,
+<a name="l05255"></a>05255 &ResultMask[0], ResultMask.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l05256"></a>05256 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abd37e9e242507f9bcda602075a67c9dd">PPCISD::VPERM</a>, dl, V1.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), V1, <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a>, VPermMask);
+<a name="l05257"></a>05257 }
+<a name="l05258"></a>05258 <span class="comment"></span>
+<a name="l05259"></a>05259 <span class="comment">/// getAltivecCompareInfo - Given an intrinsic, return false if it is not an</span>
+<a name="l05260"></a>05260 <span class="comment">/// altivec comparison. If it is, return true and fill in Opc/isDot with</span>
+<a name="l05261"></a>05261 <span class="comment">/// information about the intrinsic.</span>
+<a name="l05262"></a><a class="code" href="PPCISelLowering_8cpp.html#a35053bb3e328d74ce342c149dde6ead8">05262</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelLowering_8cpp.html#a35053bb3e328d74ce342c149dde6ead8">getAltivecCompareInfo</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Intrin, <span class="keywordtype">int</span> &CompareOpc,
+<a name="l05263"></a>05263 <span class="keywordtype">bool</span> &isDot) {
+<a name="l05264"></a>05264 <span class="keywordtype">unsigned</span> IntrinsicID =
+<a name="l05265"></a>05265 cast<ConstantSDNode>(Intrin.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0))->getZExtValue();
+<a name="l05266"></a>05266 CompareOpc = -1;
+<a name="l05267"></a>05267 isDot = <span class="keyword">false</span>;
+<a name="l05268"></a>05268 <span class="keywordflow">switch</span> (IntrinsicID) {
+<a name="l05269"></a>05269 <span class="keywordflow">default</span>: <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l05270"></a>05270 <span class="comment">// Comparison predicates.</span>
+<a name="l05271"></a>05271 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05272"></a>05272 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05273"></a>05273 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05274"></a>05274 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05275"></a>05275 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05276"></a>05276 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05277"></a>05277 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05278"></a>05278 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05279"></a>05279 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05280"></a>05280 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05281"></a>05281 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05282"></a>05282 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05283"></a>05283 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; <span class="keywordflow">break</span>;
+<a name="l05284"></a>05284
+<a name="l05285"></a>05285 <span class="comment">// Normal Comparisons.</span>
+<a name="l05286"></a>05286 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05287"></a>05287 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05288"></a>05288 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05289"></a>05289 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05290"></a>05290 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05291"></a>05291 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05292"></a>05292 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05293"></a>05293 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05294"></a>05294 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05295"></a>05295 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05296"></a>05296 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05297"></a>05297 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05298"></a>05298 <span class="keywordflow">case</span> Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; <span class="keywordflow">break</span>;
+<a name="l05299"></a>05299 }
+<a name="l05300"></a>05300 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l05301"></a>05301 }
+<a name="l05302"></a>05302 <span class="comment"></span>
+<a name="l05303"></a>05303 <span class="comment">/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom</span>
+<a name="l05304"></a>05304 <span class="comment">/// lower, do it, otherwise return null.</span>
+<a name="l05305"></a>05305 <span class="comment"></span><a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l05306"></a>05306 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l05307"></a>05307 <span class="comment">// If this is a lowered altivec predicate compare, CompareOpc is set to the</span>
+<a name="l05308"></a>05308 <span class="comment">// opcode number of the comparison.</span>
+<a name="l05309"></a>05309 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l05310"></a>05310 <span class="keywordtype">int</span> CompareOpc;
+<a name="l05311"></a>05311 <span class="keywordtype">bool</span> isDot;
+<a name="l05312"></a>05312 <span class="keywordflow">if</span> (!<a class="code" href="PPCISelLowering_8cpp.html#a35053bb3e328d74ce342c149dde6ead8">getAltivecCompareInfo</a>(Op, CompareOpc, isDot))
+<a name="l05313"></a>05313 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(); <span class="comment">// Don't custom lower most intrinsics.</span>
+<a name="l05314"></a>05314
+<a name="l05315"></a>05315 <span class="comment">// If this is a non-dot comparison, make the VCMP node and we are done.</span>
+<a name="l05316"></a>05316 <span class="keywordflow">if</span> (!isDot) {
+<a name="l05317"></a>05317 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a43a3ad5a512466965973ac46c8239c60">PPCISD::VCMP</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(),
+<a name="l05318"></a>05318 Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2),
+<a name="l05319"></a>05319 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(CompareOpc, MVT::i32));
+<a name="l05320"></a>05320 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), Tmp);
+<a name="l05321"></a>05321 }
+<a name="l05322"></a>05322
+<a name="l05323"></a>05323 <span class="comment">// Create the PPCISD altivec 'dot' comparison node.</span>
+<a name="l05324"></a>05324 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = {
+<a name="l05325"></a>05325 Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2), <span class="comment">// LHS</span>
+<a name="l05326"></a>05326 Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(3), <span class="comment">// RHS</span>
+<a name="l05327"></a>05327 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(CompareOpc, MVT::i32)
+<a name="l05328"></a>05328 };
+<a name="l05329"></a>05329 std::vector<EVT> VTs;
+<a name="l05330"></a>05330 VTs.push_back(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(2).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>());
+<a name="l05331"></a>05331 VTs.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>);
+<a name="l05332"></a>05332 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CompNode = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2739f8327120cab9e21846dee3a5366b">PPCISD::VCMPo</a>, dl, VTs, Ops, 3);
+<a name="l05333"></a>05333
+<a name="l05334"></a>05334 <span class="comment">// Now that we have the comparison, emit a copy from the CR to a GPR.</span>
+<a name="l05335"></a>05335 <span class="comment">// This is flagged to the above dot comparison.</span>
+<a name="l05336"></a>05336 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Flags = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1850fed22e97200319f85dd13fc7d798">PPCISD::MFCR</a>, dl, MVT::i32,
+<a name="l05337"></a>05337 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9268086dd9d1ba4e60cfe872dde5c173">getRegister</a>(PPC::CR6, MVT::i32),
+<a name="l05338"></a>05338 CompNode.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l05339"></a>05339
+<a name="l05340"></a>05340 <span class="comment">// Unpack the result based on how the target uses it.</span>
+<a name="l05341"></a>05341 <span class="keywordtype">unsigned</span> BitNo; <span class="comment">// Bit # of CR6.</span>
+<a name="l05342"></a>05342 <span class="keywordtype">bool</span> InvertBit; <span class="comment">// Invert result?</span>
+<a name="l05343"></a>05343 <span class="keywordflow">switch</span> (cast<ConstantSDNode>(Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))->getZExtValue()) {
+<a name="l05344"></a>05344 <span class="keywordflow">default</span>: <span class="comment">// Can't happen, don't crash on invalid number though.</span>
+<a name="l05345"></a>05345 <span class="keywordflow">case</span> 0: <span class="comment">// Return the value of the EQ bit of CR6.</span>
+<a name="l05346"></a>05346 BitNo = 0; InvertBit = <span class="keyword">false</span>;
+<a name="l05347"></a>05347 <span class="keywordflow">break</span>;
+<a name="l05348"></a>05348 <span class="keywordflow">case</span> 1: <span class="comment">// Return the inverted value of the EQ bit of CR6.</span>
+<a name="l05349"></a>05349 BitNo = 0; InvertBit = <span class="keyword">true</span>;
+<a name="l05350"></a>05350 <span class="keywordflow">break</span>;
+<a name="l05351"></a>05351 <span class="keywordflow">case</span> 2: <span class="comment">// Return the value of the LT bit of CR6.</span>
+<a name="l05352"></a>05352 BitNo = 2; InvertBit = <span class="keyword">false</span>;
+<a name="l05353"></a>05353 <span class="keywordflow">break</span>;
+<a name="l05354"></a>05354 <span class="keywordflow">case</span> 3: <span class="comment">// Return the inverted value of the LT bit of CR6.</span>
+<a name="l05355"></a>05355 BitNo = 2; InvertBit = <span class="keyword">true</span>;
+<a name="l05356"></a>05356 <span class="keywordflow">break</span>;
+<a name="l05357"></a>05357 }
+<a name="l05358"></a>05358
+<a name="l05359"></a>05359 <span class="comment">// Shift the bit into the low position.</span>
+<a name="l05360"></a>05360 Flags = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>, dl, MVT::i32, Flags,
+<a name="l05361"></a>05361 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(8-(3-BitNo), MVT::i32));
+<a name="l05362"></a>05362 <span class="comment">// Isolate the bit.</span>
+<a name="l05363"></a>05363 Flags = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, dl, MVT::i32, Flags,
+<a name="l05364"></a>05364 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, MVT::i32));
+<a name="l05365"></a>05365
+<a name="l05366"></a>05366 <span class="comment">// If we are supposed to, toggle the bit.</span>
+<a name="l05367"></a>05367 <span class="keywordflow">if</span> (InvertBit)
+<a name="l05368"></a>05368 Flags = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a>, dl, MVT::i32, Flags,
+<a name="l05369"></a>05369 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, MVT::i32));
+<a name="l05370"></a>05370 <span class="keywordflow">return</span> Flags;
+<a name="l05371"></a>05371 }
+<a name="l05372"></a>05372
+<a name="l05373"></a>05373 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerSCALAR_TO_VECTOR(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op,
+<a name="l05374"></a>05374 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l05375"></a>05375 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l05376"></a>05376 <span class="comment">// Create a stack slot that is 16-byte aligned.</span>
+<a name="l05377"></a>05377 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *FrameInfo = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a95d3f899fd68931ed5fa42e012468bdb">getMachineFunction</a>().<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l05378"></a>05378 <span class="keywordtype">int</span> FrameIdx = FrameInfo-><a class="code" href="classllvm_1_1MachineFrameInfo.html#acd4dd34a1fe2579c4e2a349aacd76bcb">CreateStackObject</a>(16, 16, <span class="keyword">false</span>);
+<a name="l05379"></a>05379 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = <a class="code" href="classllvm_1_1TargetLowering.html#a725d20a2d00a8b54cc01e6f02cb31522">getPointerTy</a>();
+<a name="l05380"></a>05380 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FIdx = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#acb59cbd8f4a8c1cf820b2b540aebdac1">getFrameIndex</a>(FrameIdx, PtrVT);
+<a name="l05381"></a>05381
+<a name="l05382"></a>05382 <span class="comment">// Store the input value into Value#0 of the stack slot.</span>
+<a name="l05383"></a>05383 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Store = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a3add7ded09f2407aa698c24c0007293d">getStore</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ad755b1a25cf0c4507d5f615f64471ae9">getEntryNode</a>(), dl,
+<a name="l05384"></a>05384 Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), FIdx, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l05385"></a>05385 <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l05386"></a>05386 <span class="comment">// Load it out.</span>
+<a name="l05387"></a>05387 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#af5413c5ecb08b1bbf8d83bdd4b5e1dae">getLoad</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(), dl, <a class="code" href="namespacellvm_1_1SPII.html#add994c36633ba2d8f6a1366b775e88a6a36b3dd3b84fde3f8494a9b18af131856">Store</a>, FIdx, <a class="code" href="structllvm_1_1MachinePointerInfo.html">MachinePointerInfo</a>(),
+<a name="l05388"></a>05388 <span class="keyword">false</span>, <span class="keyword">false</span>, <span class="keyword">false</span>, 0);
+<a name="l05389"></a>05389 }
+<a name="l05390"></a>05390
+<a name="l05391"></a>05391 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCTargetLowering::LowerMUL(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l05392"></a>05392 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>();
+<a name="l05393"></a>05393 <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>) {
+<a name="l05394"></a>05394 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), RHS = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l05395"></a>05395
+<a name="l05396"></a>05396 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Zero = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>( 0, 1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, DAG, dl);
+<a name="l05397"></a>05397 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Neg16 = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(-16, 4, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, DAG, dl);<span class="comment">//+16 as shift amt.</span>
+<a name="l05398"></a>05398
+<a name="l05399"></a>05399 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHSSwap = <span class="comment">// = vrlw RHS, 16</span>
+<a name="l05400"></a>05400 <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
+<a name="l05401"></a>05401
+<a name="l05402"></a>05402 <span class="comment">// Shrinkify inputs to v8i16.</span>
+<a name="l05403"></a>05403 LHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>, LHS);
+<a name="l05404"></a>05404 RHS = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>, RHS);
+<a name="l05405"></a>05405 RHSSwap = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>, RHSSwap);
+<a name="l05406"></a>05406
+<a name="l05407"></a>05407 <span class="comment">// Low parts multiplied together, generating 32-bit results (we ignore the</span>
+<a name="l05408"></a>05408 <span class="comment">// top parts).</span>
+<a name="l05409"></a>05409 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LoProd = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(Intrinsic::ppc_altivec_vmulouh,
+<a name="l05410"></a>05410 LHS, RHS, DAG, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>);
+<a name="l05411"></a>05411
+<a name="l05412"></a>05412 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> HiProd = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(Intrinsic::ppc_altivec_vmsumuhm,
+<a name="l05413"></a>05413 LHS, RHSSwap, Zero, DAG, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>);
+<a name="l05414"></a>05414 <span class="comment">// Shift the high parts up 16 bits.</span>
+<a name="l05415"></a>05415 HiProd = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(Intrinsic::ppc_altivec_vslw, HiProd,
+<a name="l05416"></a>05416 Neg16, DAG, dl);
+<a name="l05417"></a>05417 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>, LoProd, HiProd);
+<a name="l05418"></a>05418 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>) {
+<a name="l05419"></a>05419 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), RHS = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l05420"></a>05420
+<a name="l05421"></a>05421 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Zero = <a class="code" href="PPCISelLowering_8cpp.html#a22d3a9712cd59b040f6289be66c4a8e6">BuildSplatI</a>(0, 1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>, DAG, dl);
+<a name="l05422"></a>05422
+<a name="l05423"></a>05423 <span class="keywordflow">return</span> <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(Intrinsic::ppc_altivec_vmladduhm,
+<a name="l05424"></a>05424 LHS, RHS, Zero, DAG, dl);
+<a name="l05425"></a>05425 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>) {
+<a name="l05426"></a>05426 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), RHS = Op.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l05427"></a>05427
+<a name="l05428"></a>05428 <span class="comment">// Multiply the even 8-bit parts, producing 16-bit sums.</span>
+<a name="l05429"></a>05429 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> EvenParts = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(Intrinsic::ppc_altivec_vmuleub,
+<a name="l05430"></a>05430 LHS, RHS, DAG, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>);
+<a name="l05431"></a>05431 EvenParts = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, EvenParts);
+<a name="l05432"></a>05432
+<a name="l05433"></a>05433 <span class="comment">// Multiply the odd 8-bit parts, producing 16-bit sums.</span>
+<a name="l05434"></a>05434 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OddParts = <a class="code" href="PPCISelLowering_8cpp.html#af8f4da38cdd2653f109fe2caf6d2379a">BuildIntrinsicOp</a>(Intrinsic::ppc_altivec_vmuloub,
+<a name="l05435"></a>05435 LHS, RHS, DAG, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>);
+<a name="l05436"></a>05436 OddParts = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a412ddf522b53f07690a86bffba1278e7">ISD::BITCAST</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, OddParts);
+<a name="l05437"></a>05437
+<a name="l05438"></a>05438 <span class="comment">// Merge the results together.</span>
+<a name="l05439"></a>05439 <span class="keywordtype">int</span> Ops[16];
+<a name="l05440"></a>05440 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; i != 8; ++i) {
+<a name="l05441"></a>05441 Ops[i*2 ] = 2*i+1;
+<a name="l05442"></a>05442 Ops[i*2+1] = 2*i+1+16;
+<a name="l05443"></a>05443 }
+<a name="l05444"></a>05444 <span class="keywordflow">return</span> DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a28fe416bbaf4208d45b23705a3deb168">getVectorShuffle</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, dl, EvenParts, OddParts, Ops);
+<a name="l05445"></a>05445 } <span class="keywordflow">else</span> {
+<a name="l05446"></a>05446 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unknown mul to lower!"</span>);
+<a name="l05447"></a>05447 }
+<a name="l05448"></a>05448 }
+<a name="l05449"></a>05449 <span class="comment"></span>
+<a name="l05450"></a>05450 <span class="comment">/// LowerOperation - Provide custom lowering hooks for some operations.</span>
+<a name="l05451"></a>05451 <span class="comment">///</span>
+<a name="l05452"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#ae2a0b9bd4deed69296ac2aaf273e0ada">05452</a> <span class="comment"></span><a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="classllvm_1_1PPCTargetLowering.html#ae2a0b9bd4deed69296ac2aaf273e0ada">PPCTargetLowering::LowerOperation</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l05453"></a>05453 <span class="keywordflow">switch</span> (Op.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>()) {
+<a name="l05454"></a>05454 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Wasn't expecting to be able to lower this!"</span>);
+<a name="l05455"></a>05455 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aa8cad208c3cb96b33b5d8544590325b1">ISD::ConstantPool</a>: <span class="keywordflow">return</span> LowerConstantPool(Op, DAG);
+<a name="l05456"></a>05456 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae98378a8672947382d343d75a5df3003">ISD::BlockAddress</a>: <span class="keywordflow">return</span> LowerBlockAddress(Op, DAG);
+<a name="l05457"></a>05457 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a30316f8f9985260c49d7c26bc70a6cad">ISD::GlobalAddress</a>: <span class="keywordflow">return</span> LowerGlobalAddress(Op, DAG);
+<a name="l05458"></a>05458 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a49f1172c7014cc4fa3570792e6834e2c">ISD::GlobalTLSAddress</a>: <span class="keywordflow">return</span> LowerGlobalTLSAddress(Op, DAG);
+<a name="l05459"></a>05459 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0c70100db6ddc0b37b56feb242145cf4">ISD::JumpTable</a>: <span class="keywordflow">return</span> LowerJumpTable(Op, DAG);
+<a name="l05460"></a>05460 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0158ee47dfa868be5d28e2cbef70d5d0">ISD::SETCC</a>: <span class="keywordflow">return</span> LowerSETCC(Op, DAG);
+<a name="l05461"></a>05461 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4534a6db2862a28324932a8ea1cb54d6">ISD::INIT_TRAMPOLINE</a>: <span class="keywordflow">return</span> LowerINIT_TRAMPOLINE(Op, DAG);
+<a name="l05462"></a>05462 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110af7bfad446dfd85837fe7ff904ebb1aff">ISD::ADJUST_TRAMPOLINE</a>: <span class="keywordflow">return</span> LowerADJUST_TRAMPOLINE(Op, DAG);
+<a name="l05463"></a>05463 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110adfe32beaa596a1512b17e66b46e773ed">ISD::VASTART</a>:
+<a name="l05464"></a>05464 <span class="keywordflow">return</span> LowerVASTART(Op, DAG, PPCSubTarget);
+<a name="l05465"></a>05465
+<a name="l05466"></a>05466 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>:
+<a name="l05467"></a>05467 <span class="keywordflow">return</span> LowerVAARG(Op, DAG, PPCSubTarget);
+<a name="l05468"></a>05468
+<a name="l05469"></a>05469 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a023a9de787026fe61b024476bf9c32cb">ISD::STACKRESTORE</a>: <span class="keywordflow">return</span> LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
+<a name="l05470"></a>05470 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aa71ac22470bf853868fe6b39a25bac72">ISD::DYNAMIC_STACKALLOC</a>:
+<a name="l05471"></a>05471 <span class="keywordflow">return</span> LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
+<a name="l05472"></a>05472
+<a name="l05473"></a>05473 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a99ad6b342b7457df56b91d24e66016b3">ISD::SELECT_CC</a>: <span class="keywordflow">return</span> LowerSELECT_CC(Op, DAG);
+<a name="l05474"></a>05474 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a71640703ec096a8b07111e85cfff6987">ISD::FP_TO_UINT</a>:
+<a name="l05475"></a>05475 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac3f8f8d8437c64b2e2e9f978e2707210">ISD::FP_TO_SINT</a>: <span class="keywordflow">return</span> LowerFP_TO_INT(Op, DAG,
+<a name="l05476"></a>05476 Op.<a class="code" href="classllvm_1_1SDValue.html#ab1def9e1178c8ee31acc7ef8d257b0ed">getDebugLoc</a>());
+<a name="l05477"></a>05477 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a315004656a75a3c3a9d7294f105a8da2">ISD::SINT_TO_FP</a>: <span class="keywordflow">return</span> LowerSINT_TO_FP(Op, DAG);
+<a name="l05478"></a>05478 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a06a1a0916d630a342fc3c355b0de8eab">ISD::FLT_ROUNDS_</a>: <span class="keywordflow">return</span> LowerFLT_ROUNDS_(Op, DAG);
+<a name="l05479"></a>05479
+<a name="l05480"></a>05480 <span class="comment">// Lower 64-bit shifts.</span>
+<a name="l05481"></a>05481 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aeb80f9832dad739ee9c6deaa3110d98f">ISD::SHL_PARTS</a>: <span class="keywordflow">return</span> LowerSHL_PARTS(Op, DAG);
+<a name="l05482"></a>05482 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9ed8e1dc0db59ab2a071da53ee794759">ISD::SRL_PARTS</a>: <span class="keywordflow">return</span> LowerSRL_PARTS(Op, DAG);
+<a name="l05483"></a>05483 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a78139be59781ad05e1698eb95c58e0b1">ISD::SRA_PARTS</a>: <span class="keywordflow">return</span> LowerSRA_PARTS(Op, DAG);
+<a name="l05484"></a>05484
+<a name="l05485"></a>05485 <span class="comment">// Vector-related lowering.</span>
+<a name="l05486"></a>05486 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aff6f73b624fecca7dbe94259f9437e32">ISD::BUILD_VECTOR</a>: <span class="keywordflow">return</span> LowerBUILD_VECTOR(Op, DAG);
+<a name="l05487"></a>05487 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8d8773b28111d8898663d4a0f6223d68">ISD::VECTOR_SHUFFLE</a>: <span class="keywordflow">return</span> LowerVECTOR_SHUFFLE(Op, DAG);
+<a name="l05488"></a>05488 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac771b9cda3b889242d457cc4d9b2159c">ISD::INTRINSIC_WO_CHAIN</a>: <span class="keywordflow">return</span> LowerINTRINSIC_WO_CHAIN(Op, DAG);
+<a name="l05489"></a>05489 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a576080a08ef1bbab0308eac9d5838f75">ISD::SCALAR_TO_VECTOR</a>: <span class="keywordflow">return</span> LowerSCALAR_TO_VECTOR(Op, DAG);
+<a name="l05490"></a>05490 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a>: <span class="keywordflow">return</span> LowerMUL(Op, DAG);
+<a name="l05491"></a>05491
+<a name="l05492"></a>05492 <span class="comment">// Frame & Return address.</span>
+<a name="l05493"></a>05493 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a2dfacb29792dd59f2cfbe529206265bc">ISD::RETURNADDR</a>: <span class="keywordflow">return</span> LowerRETURNADDR(Op, DAG);
+<a name="l05494"></a>05494 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110abdb38c8daa8c1ab881007062d113cef3">ISD::FRAMEADDR</a>: <span class="keywordflow">return</span> LowerFRAMEADDR(Op, DAG);
+<a name="l05495"></a>05495 }
+<a name="l05496"></a>05496 }
+<a name="l05497"></a>05497
+<a name="l05498"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#a83cd5e15e6aa20b6646dbcd619a20120">05498</a> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1PPCTargetLowering.html#a83cd5e15e6aa20b6646dbcd619a20120">PPCTargetLowering::ReplaceNodeResults</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N,
+<a name="l05499"></a>05499 <a class="code" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl<SDValue></a>&Results,
+<a name="l05500"></a>05500 <a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> &DAG)<span class="keyword"> const </span>{
+<a name="l05501"></a>05501 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetMachine.html">TargetMachine</a> &TM = <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>();
+<a name="l05502"></a>05502 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l05503"></a>05503 <span class="keywordflow">switch</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>()) {
+<a name="l05504"></a>05504 <span class="keywordflow">default</span>:
+<a name="l05505"></a>05505 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Do not know how to custom type legalize this operation!"</span>);
+<a name="l05506"></a>05506 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae77d03846b31c41c4860bcd96d780a78">ISD::VAARG</a>: {
+<a name="l05507"></a>05507 <span class="keywordflow">if</span> (!TM.<a class="code" href="classllvm_1_1TargetMachine.html#a5af2fed99951774b6a14d30ec6e73792">getSubtarget</a><<a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a>>().<a class="code" href="classllvm_1_1PPCSubtarget.html#ad3563d2997bf4ab88c11c3ba13dc4a3e">isSVR4ABI</a>()
+<a name="l05508"></a>05508 || TM.<a class="code" href="classllvm_1_1TargetMachine.html#a5af2fed99951774b6a14d30ec6e73792">getSubtarget</a><<a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a>>().isPPC64())
+<a name="l05509"></a>05509 <span class="keywordflow">return</span>;
+<a name="l05510"></a>05510
+<a name="l05511"></a>05511 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l05512"></a>05512
+<a name="l05513"></a>05513 <span class="keywordflow">if</span> (VT == MVT::i64) {
+<a name="l05514"></a>05514 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> NewNode = LowerVAARG(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 1), DAG, PPCSubTarget);
+<a name="l05515"></a>05515
+<a name="l05516"></a>05516 Results.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(NewNode);
+<a name="l05517"></a>05517 Results.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(NewNode.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l05518"></a>05518 }
+<a name="l05519"></a>05519 <span class="keywordflow">return</span>;
+<a name="l05520"></a>05520 }
+<a name="l05521"></a>05521 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8745901e68ed76ceaf48791715cefcb4">ISD::FP_ROUND_INREG</a>: {
+<a name="l05522"></a>05522 assert(N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>);
+<a name="l05523"></a>05523 assert(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>);
+<a name="l05524"></a>05524 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Lo = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7e6dca8262a3de788d1bab4ba184d675">ISD::EXTRACT_ELEMENT</a>, dl,
+<a name="l05525"></a>05525 MVT::f64, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0),
+<a name="l05526"></a>05526 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(0));
+<a name="l05527"></a>05527 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Hi = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7e6dca8262a3de788d1bab4ba184d675">ISD::EXTRACT_ELEMENT</a>, dl,
+<a name="l05528"></a>05528 MVT::f64, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0),
+<a name="l05529"></a>05529 DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a9a66b00ea9db7d80bf1bcbbcaa108239">getIntPtrConstant</a>(1));
+<a name="l05530"></a>05530
+<a name="l05531"></a>05531 <span class="comment">// This sequence changes FPSCR to do round-to-zero, adds the two halves</span>
+<a name="l05532"></a>05532 <span class="comment">// of the long double, and puts FPSCR back the way it was. We do not</span>
+<a name="l05533"></a>05533 <span class="comment">// actually model FPSCR.</span>
+<a name="l05534"></a>05534 std::vector<EVT> NodeTys;
+<a name="l05535"></a>05535 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[4], Result, MFFSreg, InFlag, FPreg;
+<a name="l05536"></a>05536
+<a name="l05537"></a>05537 NodeTys.push_back(MVT::f64); <span class="comment">// Return register</span>
+<a name="l05538"></a>05538 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>); <span class="comment">// Returns a flag for later insns</span>
+<a name="l05539"></a>05539 Result = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aab6a046c536c71121190fefd548d6b25">PPCISD::MFFS</a>, dl, NodeTys, &InFlag, 0);
+<a name="l05540"></a>05540 MFFSreg = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(0);
+<a name="l05541"></a>05541 InFlag = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l05542"></a>05542
+<a name="l05543"></a>05543 NodeTys.clear();
+<a name="l05544"></a>05544 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>); <span class="comment">// Returns a flag</span>
+<a name="l05545"></a>05545 Ops[0] = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(31, MVT::i32);
+<a name="l05546"></a>05546 Ops[1] = InFlag;
+<a name="l05547"></a>05547 Result = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a2c4c29545f861421669b2c8db4464d0a" title="OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.">PPCISD::MTFSB1</a>, dl, NodeTys, Ops, 2);
+<a name="l05548"></a>05548 InFlag = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(0);
+<a name="l05549"></a>05549
+<a name="l05550"></a>05550 NodeTys.clear();
+<a name="l05551"></a>05551 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>); <span class="comment">// Returns a flag</span>
+<a name="l05552"></a>05552 Ops[0] = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(30, MVT::i32);
+<a name="l05553"></a>05553 Ops[1] = InFlag;
+<a name="l05554"></a>05554 Result = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a993035abda4f7c501e3ca88e8297e37d" title="OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.">PPCISD::MTFSB0</a>, dl, NodeTys, Ops, 2);
+<a name="l05555"></a>05555 InFlag = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(0);
+<a name="l05556"></a>05556
+<a name="l05557"></a>05557 NodeTys.clear();
+<a name="l05558"></a>05558 NodeTys.push_back(MVT::f64); <span class="comment">// result of add</span>
+<a name="l05559"></a>05559 NodeTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>); <span class="comment">// Returns a flag</span>
+<a name="l05560"></a>05560 Ops[0] = <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ab68a439987d870da623ed899fa47344c" title="Low address component (lower 16)">Lo</a>;
+<a name="l05561"></a>05561 Ops[1] = <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ae3a56d8e7b43b7a68cbb0e7655a062cd" title="High address component (upper 16)">Hi</a>;
+<a name="l05562"></a>05562 Ops[2] = InFlag;
+<a name="l05563"></a>05563 Result = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66ad2b0da006c4560646ac3eb561a8b73b2">PPCISD::FADDRTZ</a>, dl, NodeTys, Ops, 3);
+<a name="l05564"></a>05564 FPreg = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(0);
+<a name="l05565"></a>05565 InFlag = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l05566"></a>05566
+<a name="l05567"></a>05567 NodeTys.clear();
+<a name="l05568"></a>05568 NodeTys.push_back(MVT::f64);
+<a name="l05569"></a>05569 Ops[0] = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#a13ad902229b8b6b3a7a1d29dedac01e0">getConstant</a>(1, MVT::i32);
+<a name="l05570"></a>05570 Ops[1] = MFFSreg;
+<a name="l05571"></a>05571 Ops[2] = FPreg;
+<a name="l05572"></a>05572 Ops[3] = InFlag;
+<a name="l05573"></a>05573 Result = DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a29fbc2a15e633db7ade7b0ee2f137a1c" title="MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.">PPCISD::MTFSF</a>, dl, NodeTys, Ops, 4);
+<a name="l05574"></a>05574 FPreg = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(0);
+<a name="l05575"></a>05575
+<a name="l05576"></a>05576 <span class="comment">// We know the low half is about to be thrown away, so just use something</span>
+<a name="l05577"></a>05577 <span class="comment">// convenient.</span>
+<a name="l05578"></a>05578 Results.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(DAG.<a class="code" href="classllvm_1_1SelectionDAG.html#ac65c8a6cfb8608d6722c6df997870780">getNode</a>(<a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a41bd84b853e2c03fb1af1f4ca9ebdcaf">ISD::BUILD_PAIR</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca497ebfc1d05b772bf14cd530c950cf80">MVT::ppcf128</a>,
+<a name="l05579"></a>05579 FPreg, FPreg));
+<a name="l05580"></a>05580 <span class="keywordflow">return</span>;
+<a name="l05581"></a>05581 }
+<a name="l05582"></a>05582 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac3f8f8d8437c64b2e2e9f978e2707210">ISD::FP_TO_SINT</a>:
+<a name="l05583"></a>05583 Results.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(LowerFP_TO_INT(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 0), DAG, dl));
+<a name="l05584"></a>05584 <span class="keywordflow">return</span>;
+<a name="l05585"></a>05585 }
+<a name="l05586"></a>05586 }
+<a name="l05587"></a>05587
+<a name="l05588"></a>05588
+<a name="l05589"></a>05589 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l05590"></a>05590 <span class="comment">// Other Lowering Code</span>
+<a name="l05591"></a>05591 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l05592"></a>05592
+<a name="l05593"></a>05593 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *
+<a name="l05594"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">05594</a> <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">PPCTargetLowering::EmitAtomicBinary</a>(<a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>, <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *BB,
+<a name="l05595"></a>05595 <span class="keywordtype">bool</span> is64bit, <span class="keywordtype">unsigned</span> BinOpcode)<span class="keyword"> const </span>{
+<a name="l05596"></a>05596 <span class="comment">// This also handles ATOMIC_SWAP, indicated by BinOpcode==0.</span>
+<a name="l05597"></a>05597 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII = <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>();
+<a name="l05598"></a>05598
+<a name="l05599"></a>05599 <span class="keyword">const</span> <a class="code" href="classllvm_1_1BasicBlock.html" title="LLVM Basic Block Representation.">BasicBlock</a> *LLVM_BB = BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a2961c31b29db17a4f2964899c8569a64">getBasicBlock</a>();
+<a name="l05600"></a>05600 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> *<a class="code" href="LLParser_8cpp.html#a33ece1ef8074506a15d7f86eb76dbae6">F</a> = BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l05601"></a>05601 <a class="code" href="classllvm_1_1MachineFunction.html#a340712de3e78fec11c338735cab17df7">MachineFunction::iterator</a> It = BB;
+<a name="l05602"></a>05602 ++It;
+<a name="l05603"></a>05603
+<a name="l05604"></a>05604 <span class="keywordtype">unsigned</span> dest = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(0).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05605"></a>05605 <span class="keywordtype">unsigned</span> ptrA = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(1).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05606"></a>05606 <span class="keywordtype">unsigned</span> ptrB = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(2).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05607"></a>05607 <span class="keywordtype">unsigned</span> incr = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(3).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05608"></a>05608 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a5ca4af2a257043145ad650eafb4402f9">getDebugLoc</a>();
+<a name="l05609"></a>05609
+<a name="l05610"></a>05610 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *loopMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05611"></a>05611 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *exitMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05612"></a>05612 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, loopMBB);
+<a name="l05613"></a>05613 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, exitMBB);
+<a name="l05614"></a>05614 exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a4caec104f2ab9fe27e8fb0da33497635">splice</a>(exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(), BB,
+<a name="l05615"></a>05615 <a class="code" href="namespacellvm.html#aa1704159f75e6eacd595962ea6d93ffe">llvm::next</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a>(MI)),
+<a name="l05616"></a>05616 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#acbc921830578e2741be6549db716c0ce">end</a>());
+<a name="l05617"></a>05617 exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#adae25a8cf267a802c72c3d6ad8c044e3">transferSuccessorsAndUpdatePHIs</a>(BB);
+<a name="l05618"></a>05618
+<a name="l05619"></a>05619 <a class="code" href="classllvm_1_1MachineRegisterInfo.html">MachineRegisterInfo</a> &RegInfo = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>();
+<a name="l05620"></a>05620 <span class="keywordtype">unsigned</span> TmpReg = (!BinOpcode) ? incr :
+<a name="l05621"></a>05621 RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(
+<a name="l05622"></a>05622 is64bit ? (<span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *) &PPC::G8RCRegClass :
+<a name="l05623"></a>05623 (<span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *) &PPC::GPRCRegClass);
+<a name="l05624"></a>05624
+<a name="l05625"></a>05625 <span class="comment">// thisMBB:</span>
+<a name="l05626"></a>05626 <span class="comment">// ...</span>
+<a name="l05627"></a>05627 <span class="comment">// fallthrough --> loopMBB</span>
+<a name="l05628"></a>05628 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(loopMBB);
+<a name="l05629"></a>05629
+<a name="l05630"></a>05630 <span class="comment">// loopMBB:</span>
+<a name="l05631"></a>05631 <span class="comment">// l[wd]arx dest, ptr</span>
+<a name="l05632"></a>05632 <span class="comment">// add r0, dest, incr</span>
+<a name="l05633"></a>05633 <span class="comment">// st[wd]cx. r0, ptr</span>
+<a name="l05634"></a>05634 <span class="comment">// bne- loopMBB</span>
+<a name="l05635"></a>05635 <span class="comment">// fallthrough --> exitMBB</span>
+<a name="l05636"></a>05636 BB = loopMBB;
+<a name="l05637"></a>05637 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+<a name="l05638"></a>05638 .addReg(ptrA).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrB);
+<a name="l05639"></a>05639 <span class="keywordflow">if</span> (BinOpcode)
+<a name="l05640"></a>05640 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(BinOpcode), TmpReg).addReg(incr).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(dest);
+<a name="l05641"></a>05641 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::STDCX : PPC::STWCX))
+<a name="l05642"></a>05642 .addReg(TmpReg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrA).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrB);
+<a name="l05643"></a>05643 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::BCC))
+<a name="l05644"></a>05644 .addImm(<a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355ad9add708b3d9680d64242cf06f448462">PPC::PRED_NE</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(PPC::CR0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#aa1ec82398ade62414be35d8431c0a33b">addMBB</a>(loopMBB);
+<a name="l05645"></a>05645 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(loopMBB);
+<a name="l05646"></a>05646 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(exitMBB);
+<a name="l05647"></a>05647
+<a name="l05648"></a>05648 <span class="comment">// exitMBB:</span>
+<a name="l05649"></a>05649 <span class="comment">// ...</span>
+<a name="l05650"></a>05650 BB = exitMBB;
+<a name="l05651"></a>05651 <span class="keywordflow">return</span> BB;
+<a name="l05652"></a>05652 }
+<a name="l05653"></a>05653
+<a name="l05654"></a>05654 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *
+<a name="l05655"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">05655</a> <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">PPCTargetLowering::EmitPartwordAtomicBinary</a>(<a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>,
+<a name="l05656"></a>05656 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *BB,
+<a name="l05657"></a>05657 <span class="keywordtype">bool</span> is8bit, <span class="comment">// operation</span>
+<a name="l05658"></a>05658 <span class="keywordtype">unsigned</span> BinOpcode)<span class="keyword"> const </span>{
+<a name="l05659"></a>05659 <span class="comment">// This also handles ATOMIC_SWAP, indicated by BinOpcode==0.</span>
+<a name="l05660"></a>05660 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII = <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>();
+<a name="l05661"></a>05661 <span class="comment">// In 64 bit mode we have to use 64 bits for addresses, even though the</span>
+<a name="l05662"></a>05662 <span class="comment">// lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address</span>
+<a name="l05663"></a>05663 <span class="comment">// registers without caring whether they're 32 or 64, but here we're</span>
+<a name="l05664"></a>05664 <span class="comment">// doing actual arithmetic on the addresses.</span>
+<a name="l05665"></a>05665 <span class="keywordtype">bool</span> is64bit = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>();
+<a name="l05666"></a>05666 <span class="keywordtype">unsigned</span> ZeroReg = is64bit ? PPC::X0 : PPC::R0;
+<a name="l05667"></a>05667
+<a name="l05668"></a>05668 <span class="keyword">const</span> <a class="code" href="classllvm_1_1BasicBlock.html" title="LLVM Basic Block Representation.">BasicBlock</a> *LLVM_BB = BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a2961c31b29db17a4f2964899c8569a64">getBasicBlock</a>();
+<a name="l05669"></a>05669 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> *<a class="code" href="LLParser_8cpp.html#a33ece1ef8074506a15d7f86eb76dbae6">F</a> = BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l05670"></a>05670 <a class="code" href="classllvm_1_1MachineFunction.html#a340712de3e78fec11c338735cab17df7">MachineFunction::iterator</a> It = BB;
+<a name="l05671"></a>05671 ++It;
+<a name="l05672"></a>05672
+<a name="l05673"></a>05673 <span class="keywordtype">unsigned</span> dest = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(0).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05674"></a>05674 <span class="keywordtype">unsigned</span> ptrA = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(1).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05675"></a>05675 <span class="keywordtype">unsigned</span> ptrB = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(2).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05676"></a>05676 <span class="keywordtype">unsigned</span> incr = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(3).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05677"></a>05677 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a5ca4af2a257043145ad650eafb4402f9">getDebugLoc</a>();
+<a name="l05678"></a>05678
+<a name="l05679"></a>05679 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *loopMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05680"></a>05680 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *exitMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05681"></a>05681 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, loopMBB);
+<a name="l05682"></a>05682 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, exitMBB);
+<a name="l05683"></a>05683 exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a4caec104f2ab9fe27e8fb0da33497635">splice</a>(exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(), BB,
+<a name="l05684"></a>05684 <a class="code" href="namespacellvm.html#aa1704159f75e6eacd595962ea6d93ffe">llvm::next</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a>(MI)),
+<a name="l05685"></a>05685 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#acbc921830578e2741be6549db716c0ce">end</a>());
+<a name="l05686"></a>05686 exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#adae25a8cf267a802c72c3d6ad8c044e3">transferSuccessorsAndUpdatePHIs</a>(BB);
+<a name="l05687"></a>05687
+<a name="l05688"></a>05688 <a class="code" href="classllvm_1_1MachineRegisterInfo.html">MachineRegisterInfo</a> &RegInfo = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>();
+<a name="l05689"></a>05689 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *RC =
+<a name="l05690"></a>05690 is64bit ? (<span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *) &PPC::G8RCRegClass :
+<a name="l05691"></a>05691 (<span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *) &PPC::GPRCRegClass;
+<a name="l05692"></a>05692 <span class="keywordtype">unsigned</span> PtrReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05693"></a>05693 <span class="keywordtype">unsigned</span> Shift1Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05694"></a>05694 <span class="keywordtype">unsigned</span> ShiftReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05695"></a>05695 <span class="keywordtype">unsigned</span> Incr2Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05696"></a>05696 <span class="keywordtype">unsigned</span> MaskReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05697"></a>05697 <span class="keywordtype">unsigned</span> Mask2Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05698"></a>05698 <span class="keywordtype">unsigned</span> Mask3Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05699"></a>05699 <span class="keywordtype">unsigned</span> Tmp2Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05700"></a>05700 <span class="keywordtype">unsigned</span> Tmp3Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05701"></a>05701 <span class="keywordtype">unsigned</span> Tmp4Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05702"></a>05702 <span class="keywordtype">unsigned</span> TmpDestReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05703"></a>05703 <span class="keywordtype">unsigned</span> Ptr1Reg;
+<a name="l05704"></a>05704 <span class="keywordtype">unsigned</span> TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05705"></a>05705
+<a name="l05706"></a>05706 <span class="comment">// thisMBB:</span>
+<a name="l05707"></a>05707 <span class="comment">// ...</span>
+<a name="l05708"></a>05708 <span class="comment">// fallthrough --> loopMBB</span>
+<a name="l05709"></a>05709 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(loopMBB);
+<a name="l05710"></a>05710
+<a name="l05711"></a>05711 <span class="comment">// The 4-byte load must be aligned, while a char or short may be</span>
+<a name="l05712"></a>05712 <span class="comment">// anywhere in the word. Hence all this nasty bookkeeping code.</span>
+<a name="l05713"></a>05713 <span class="comment">// add ptr1, ptrA, ptrB [copy if ptrA==0]</span>
+<a name="l05714"></a>05714 <span class="comment">// rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]</span>
+<a name="l05715"></a>05715 <span class="comment">// xori shift, shift1, 24 [16]</span>
+<a name="l05716"></a>05716 <span class="comment">// rlwinm ptr, ptr1, 0, 0, 29</span>
+<a name="l05717"></a>05717 <span class="comment">// slw incr2, incr, shift</span>
+<a name="l05718"></a>05718 <span class="comment">// li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]</span>
+<a name="l05719"></a>05719 <span class="comment">// slw mask, mask2, shift</span>
+<a name="l05720"></a>05720 <span class="comment">// loopMBB:</span>
+<a name="l05721"></a>05721 <span class="comment">// lwarx tmpDest, ptr</span>
+<a name="l05722"></a>05722 <span class="comment">// add tmp, tmpDest, incr2</span>
+<a name="l05723"></a>05723 <span class="comment">// andc tmp2, tmpDest, mask</span>
+<a name="l05724"></a>05724 <span class="comment">// and tmp3, tmp, mask</span>
+<a name="l05725"></a>05725 <span class="comment">// or tmp4, tmp3, tmp2</span>
+<a name="l05726"></a>05726 <span class="comment">// stwcx. tmp4, ptr</span>
+<a name="l05727"></a>05727 <span class="comment">// bne- loopMBB</span>
+<a name="l05728"></a>05728 <span class="comment">// fallthrough --> exitMBB</span>
+<a name="l05729"></a>05729 <span class="comment">// srw dest, tmpDest, shift</span>
+<a name="l05730"></a>05730 <span class="keywordflow">if</span> (ptrA != ZeroReg) {
+<a name="l05731"></a>05731 Ptr1Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l05732"></a>05732 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
+<a name="l05733"></a>05733 .addReg(ptrA).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrB);
+<a name="l05734"></a>05734 } <span class="keywordflow">else</span> {
+<a name="l05735"></a>05735 Ptr1Reg = ptrB;
+<a name="l05736"></a>05736 }
+<a name="l05737"></a>05737 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
+<a name="l05738"></a>05738 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(3).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(27).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(is8bit ? 28 : 27);
+<a name="l05739"></a>05739 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
+<a name="l05740"></a>05740 .addReg(Shift1Reg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(is8bit ? 24 : 16);
+<a name="l05741"></a>05741 <span class="keywordflow">if</span> (is64bit)
+<a name="l05742"></a>05742 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::RLDICR), PtrReg)
+<a name="l05743"></a>05743 .addReg(Ptr1Reg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(61);
+<a name="l05744"></a>05744 <span class="keywordflow">else</span>
+<a name="l05745"></a>05745 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::RLWINM), PtrReg)
+<a name="l05746"></a>05746 .addReg(Ptr1Reg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(29);
+<a name="l05747"></a>05747 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::SLW), Incr2Reg)
+<a name="l05748"></a>05748 .addReg(incr).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ShiftReg);
+<a name="l05749"></a>05749 <span class="keywordflow">if</span> (is8bit)
+<a name="l05750"></a>05750 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(<a class="code" href="LoopInfoImpl_8h.html#ab7b7f3fe4279386eae18cf924053d077">PPC::LI</a>), Mask2Reg).addImm(255);
+<a name="l05751"></a>05751 <span class="keywordflow">else</span> {
+<a name="l05752"></a>05752 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(<a class="code" href="LoopInfoImpl_8h.html#ab7b7f3fe4279386eae18cf924053d077">PPC::LI</a>), Mask3Reg).addImm(0);
+<a name="l05753"></a>05753 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::ORI),Mask2Reg).addReg(Mask3Reg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(65535);
+<a name="l05754"></a>05754 }
+<a name="l05755"></a>05755 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::SLW), MaskReg)
+<a name="l05756"></a>05756 .addReg(Mask2Reg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ShiftReg);
+<a name="l05757"></a>05757
+<a name="l05758"></a>05758 BB = loopMBB;
+<a name="l05759"></a>05759 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::LWARX), TmpDestReg)
+<a name="l05760"></a>05760 .addReg(ZeroReg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(PtrReg);
+<a name="l05761"></a>05761 <span class="keywordflow">if</span> (BinOpcode)
+<a name="l05762"></a>05762 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(BinOpcode), TmpReg)
+<a name="l05763"></a>05763 .addReg(Incr2Reg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(TmpDestReg);
+<a name="l05764"></a>05764 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
+<a name="l05765"></a>05765 .addReg(TmpDestReg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(MaskReg);
+<a name="l05766"></a>05766 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::AND8 : <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a865555c9f2e0458a7078486aa1b3254f">PPC::AND</a>), Tmp3Reg)
+<a name="l05767"></a>05767 .addReg(TmpReg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(MaskReg);
+<a name="l05768"></a>05768 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::OR8 : <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a96727447c0ad447987df1c6415aef074">PPC::OR</a>), Tmp4Reg)
+<a name="l05769"></a>05769 .addReg(Tmp3Reg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(Tmp2Reg);
+<a name="l05770"></a>05770 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::STDCX : PPC::STWCX))
+<a name="l05771"></a>05771 .addReg(Tmp4Reg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ZeroReg).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(PtrReg);
+<a name="l05772"></a>05772 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::BCC))
+<a name="l05773"></a>05773 .addImm(<a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355ad9add708b3d9680d64242cf06f448462">PPC::PRED_NE</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(PPC::CR0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#aa1ec82398ade62414be35d8431c0a33b">addMBB</a>(loopMBB);
+<a name="l05774"></a>05774 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(loopMBB);
+<a name="l05775"></a>05775 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(exitMBB);
+<a name="l05776"></a>05776
+<a name="l05777"></a>05777 <span class="comment">// exitMBB:</span>
+<a name="l05778"></a>05778 <span class="comment">// ...</span>
+<a name="l05779"></a>05779 BB = exitMBB;
+<a name="l05780"></a>05780 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(*BB, BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(), dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::SRW), dest).addReg(TmpDestReg)
+<a name="l05781"></a>05781 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ShiftReg);
+<a name="l05782"></a>05782 <span class="keywordflow">return</span> BB;
+<a name="l05783"></a>05783 }
+<a name="l05784"></a>05784
+<a name="l05785"></a>05785 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *
+<a name="l05786"></a><a class="code" href="classllvm_1_1PPCTargetLowering.html#af330d61b0d53df1eb27d7ef2c5d113e0">05786</a> <a class="code" href="classllvm_1_1PPCTargetLowering.html#af330d61b0d53df1eb27d7ef2c5d113e0">PPCTargetLowering::EmitInstrWithCustomInserter</a>(<a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>,
+<a name="l05787"></a>05787 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *BB)<span class="keyword"> const </span>{
+<a name="l05788"></a>05788 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII = <a class="code" href="classllvm_1_1TargetLowering.html#a58df424b85f3b5c2c4faea47c735c249">getTargetMachine</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>();
+<a name="l05789"></a>05789
+<a name="l05790"></a>05790 <span class="comment">// To "insert" these instructions we actually have to insert their</span>
+<a name="l05791"></a>05791 <span class="comment">// control-flow patterns.</span>
+<a name="l05792"></a>05792 <span class="keyword">const</span> <a class="code" href="classllvm_1_1BasicBlock.html" title="LLVM Basic Block Representation.">BasicBlock</a> *LLVM_BB = BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a2961c31b29db17a4f2964899c8569a64">getBasicBlock</a>();
+<a name="l05793"></a>05793 <a class="code" href="classllvm_1_1MachineFunction.html#a340712de3e78fec11c338735cab17df7">MachineFunction::iterator</a> It = BB;
+<a name="l05794"></a>05794 ++It;
+<a name="l05795"></a>05795
+<a name="l05796"></a>05796 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> *<a class="code" href="LLParser_8cpp.html#a33ece1ef8074506a15d7f86eb76dbae6">F</a> = BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l05797"></a>05797
+<a name="l05798"></a>05798 <span class="keywordflow">if</span> (PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#a4298a0eddfbef5cdef46094fb87b3b02">hasISEL</a>() && (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::SELECT_CC_I4 ||
+<a name="l05799"></a>05799 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::SELECT_CC_I8)) {
+<a name="l05800"></a>05800 <span class="keywordtype">unsigned</span> OpCode = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::SELECT_CC_I8 ?
+<a name="l05801"></a>05801 PPC::ISEL8 : PPC::ISEL;
+<a name="l05802"></a>05802 <span class="keywordtype">unsigned</span> SelectPred = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(4).<a class="code" href="classllvm_1_1MachineOperand.html#a7059d68a29d5ecfb37623ab45cdb4e8d">getImm</a>();
+<a name="l05803"></a>05803 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a5ca4af2a257043145ad650eafb4402f9">getDebugLoc</a>();
+<a name="l05804"></a>05804
+<a name="l05805"></a>05805 <span class="comment">// The SelectPred is ((BI << 5) | BO) for a BCC</span>
+<a name="l05806"></a>05806 <span class="keywordtype">unsigned</span> BO = SelectPred & 0xF;
+<a name="l05807"></a>05807 assert((BO == 12 || BO == 4) && <span class="stringliteral">"invalid predicate BO field for isel"</span>);
+<a name="l05808"></a>05808
+<a name="l05809"></a>05809 <span class="keywordtype">unsigned</span> TrueOpNo, FalseOpNo;
+<a name="l05810"></a>05810 <span class="keywordflow">if</span> (BO == 12) {
+<a name="l05811"></a>05811 TrueOpNo = 2;
+<a name="l05812"></a>05812 FalseOpNo = 3;
+<a name="l05813"></a>05813 } <span class="keywordflow">else</span> {
+<a name="l05814"></a>05814 TrueOpNo = 3;
+<a name="l05815"></a>05815 FalseOpNo = 2;
+<a name="l05816"></a>05816 SelectPred = <a class="code" href="namespacellvm_1_1PPC.html#a430fc7aab545fd5d88076b455542dce3" title="Invert the specified predicate. != -> ==, < -> >=.">PPC::InvertPredicate</a>((<a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355" title="Predicate - These are "(BI << 5) | BO" for various predicates.">PPC::Predicate</a>)SelectPred);
+<a name="l05817"></a>05817 }
+<a name="l05818"></a>05818
+<a name="l05819"></a>05819 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(*BB, MI, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(OpCode), MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(0).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>())
+<a name="l05820"></a>05820 .addReg(MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(TrueOpNo).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>())
+<a name="l05821"></a>05821 .addReg(MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(FalseOpNo).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>())
+<a name="l05822"></a>05822 .addImm(SelectPred).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(1).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>());
+<a name="l05823"></a>05823 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::SELECT_CC_I4 ||
+<a name="l05824"></a>05824 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::SELECT_CC_I8 ||
+<a name="l05825"></a>05825 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::SELECT_CC_F4 ||
+<a name="l05826"></a>05826 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::SELECT_CC_F8 ||
+<a name="l05827"></a>05827 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::SELECT_CC_VRRC) {
+<a name="l05828"></a>05828
+<a name="l05829"></a>05829
+<a name="l05830"></a>05830 <span class="comment">// The incoming instruction knows the destination vreg to set, the</span>
+<a name="l05831"></a>05831 <span class="comment">// condition code register to branch on, the true/false values to</span>
+<a name="l05832"></a>05832 <span class="comment">// select between, and a branch opcode to use.</span>
+<a name="l05833"></a>05833
+<a name="l05834"></a>05834 <span class="comment">// thisMBB:</span>
+<a name="l05835"></a>05835 <span class="comment">// ...</span>
+<a name="l05836"></a>05836 <span class="comment">// TrueVal = ...</span>
+<a name="l05837"></a>05837 <span class="comment">// cmpTY ccX, r1, r2</span>
+<a name="l05838"></a>05838 <span class="comment">// bCC copy1MBB</span>
+<a name="l05839"></a>05839 <span class="comment">// fallthrough --> copy0MBB</span>
+<a name="l05840"></a>05840 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *thisMBB = BB;
+<a name="l05841"></a>05841 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *copy0MBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05842"></a>05842 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *sinkMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05843"></a>05843 <span class="keywordtype">unsigned</span> SelectPred = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(4).<a class="code" href="classllvm_1_1MachineOperand.html#a7059d68a29d5ecfb37623ab45cdb4e8d">getImm</a>();
+<a name="l05844"></a>05844 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a5ca4af2a257043145ad650eafb4402f9">getDebugLoc</a>();
+<a name="l05845"></a>05845 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, copy0MBB);
+<a name="l05846"></a>05846 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, sinkMBB);
+<a name="l05847"></a>05847
+<a name="l05848"></a>05848 <span class="comment">// Transfer the remainder of BB and its successor edges to sinkMBB.</span>
+<a name="l05849"></a>05849 sinkMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a4caec104f2ab9fe27e8fb0da33497635">splice</a>(sinkMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(), BB,
+<a name="l05850"></a>05850 <a class="code" href="namespacellvm.html#aa1704159f75e6eacd595962ea6d93ffe">llvm::next</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a>(MI)),
+<a name="l05851"></a>05851 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#acbc921830578e2741be6549db716c0ce">end</a>());
+<a name="l05852"></a>05852 sinkMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#adae25a8cf267a802c72c3d6ad8c044e3">transferSuccessorsAndUpdatePHIs</a>(BB);
+<a name="l05853"></a>05853
+<a name="l05854"></a>05854 <span class="comment">// Next, add the true and fallthrough blocks as its successors.</span>
+<a name="l05855"></a>05855 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(copy0MBB);
+<a name="l05856"></a>05856 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(sinkMBB);
+<a name="l05857"></a>05857
+<a name="l05858"></a>05858 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::BCC))
+<a name="l05859"></a>05859 .addImm(SelectPred).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(1).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>()).addMBB(sinkMBB);
+<a name="l05860"></a>05860
+<a name="l05861"></a>05861 <span class="comment">// copy0MBB:</span>
+<a name="l05862"></a>05862 <span class="comment">// %FalseValue = ...</span>
+<a name="l05863"></a>05863 <span class="comment">// # fallthrough to sinkMBB</span>
+<a name="l05864"></a>05864 BB = copy0MBB;
+<a name="l05865"></a>05865
+<a name="l05866"></a>05866 <span class="comment">// Update machine-CFG edges</span>
+<a name="l05867"></a>05867 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(sinkMBB);
+<a name="l05868"></a>05868
+<a name="l05869"></a>05869 <span class="comment">// sinkMBB:</span>
+<a name="l05870"></a>05870 <span class="comment">// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]</span>
+<a name="l05871"></a>05871 <span class="comment">// ...</span>
+<a name="l05872"></a>05872 BB = sinkMBB;
+<a name="l05873"></a>05873 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(*BB, BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(), dl,
+<a name="l05874"></a>05874 TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(<a class="code" href="namespacellvm.html#a332cde6eadc39e042b35937d137c83f6">PPC::PHI</a>), MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(0).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>())
+<a name="l05875"></a>05875 .addReg(MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(3).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>()).addMBB(copy0MBB)
+<a name="l05876"></a>05876 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(2).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>()).addMBB(thisMBB);
+<a name="l05877"></a>05877 }
+<a name="l05878"></a>05878 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_ADD_I8)
+<a name="l05879"></a>05879 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::ADD4);
+<a name="l05880"></a>05880 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_ADD_I16)
+<a name="l05881"></a>05881 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, PPC::ADD4);
+<a name="l05882"></a>05882 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_ADD_I32)
+<a name="l05883"></a>05883 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, PPC::ADD4);
+<a name="l05884"></a>05884 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_ADD_I64)
+<a name="l05885"></a>05885 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::ADD8);
+<a name="l05886"></a>05886
+<a name="l05887"></a>05887 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_AND_I8)
+<a name="l05888"></a>05888 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a865555c9f2e0458a7078486aa1b3254f">PPC::AND</a>);
+<a name="l05889"></a>05889 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_AND_I16)
+<a name="l05890"></a>05890 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a865555c9f2e0458a7078486aa1b3254f">PPC::AND</a>);
+<a name="l05891"></a>05891 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_AND_I32)
+<a name="l05892"></a>05892 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a865555c9f2e0458a7078486aa1b3254f">PPC::AND</a>);
+<a name="l05893"></a>05893 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_AND_I64)
+<a name="l05894"></a>05894 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::AND8);
+<a name="l05895"></a>05895
+<a name="l05896"></a>05896 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_OR_I8)
+<a name="l05897"></a>05897 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a96727447c0ad447987df1c6415aef074">PPC::OR</a>);
+<a name="l05898"></a>05898 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_OR_I16)
+<a name="l05899"></a>05899 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a96727447c0ad447987df1c6415aef074">PPC::OR</a>);
+<a name="l05900"></a>05900 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_OR_I32)
+<a name="l05901"></a>05901 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a96727447c0ad447987df1c6415aef074">PPC::OR</a>);
+<a name="l05902"></a>05902 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_OR_I64)
+<a name="l05903"></a>05903 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::OR8);
+<a name="l05904"></a>05904
+<a name="l05905"></a>05905 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_XOR_I8)
+<a name="l05906"></a>05906 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9ac62338ffb5de22369c75caa565b5da1a">PPC::XOR</a>);
+<a name="l05907"></a>05907 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_XOR_I16)
+<a name="l05908"></a>05908 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9ac62338ffb5de22369c75caa565b5da1a">PPC::XOR</a>);
+<a name="l05909"></a>05909 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_XOR_I32)
+<a name="l05910"></a>05910 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9ac62338ffb5de22369c75caa565b5da1a">PPC::XOR</a>);
+<a name="l05911"></a>05911 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_XOR_I64)
+<a name="l05912"></a>05912 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::XOR8);
+<a name="l05913"></a>05913
+<a name="l05914"></a>05914 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_NAND_I8)
+<a name="l05915"></a>05915 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::ANDC);
+<a name="l05916"></a>05916 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_NAND_I16)
+<a name="l05917"></a>05917 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, PPC::ANDC);
+<a name="l05918"></a>05918 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_NAND_I32)
+<a name="l05919"></a>05919 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, PPC::ANDC);
+<a name="l05920"></a>05920 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_NAND_I64)
+<a name="l05921"></a>05921 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::ANDC8);
+<a name="l05922"></a>05922
+<a name="l05923"></a>05923 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_SUB_I8)
+<a name="l05924"></a>05924 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::SUBF);
+<a name="l05925"></a>05925 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_SUB_I16)
+<a name="l05926"></a>05926 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, PPC::SUBF);
+<a name="l05927"></a>05927 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_SUB_I32)
+<a name="l05928"></a>05928 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, PPC::SUBF);
+<a name="l05929"></a>05929 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_LOAD_SUB_I64)
+<a name="l05930"></a>05930 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, PPC::SUBF8);
+<a name="l05931"></a>05931
+<a name="l05932"></a>05932 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_SWAP_I8)
+<a name="l05933"></a>05933 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, 0);
+<a name="l05934"></a>05934 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_SWAP_I16)
+<a name="l05935"></a>05935 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a143d6f7b5867578ea676ecdf2f9ff9ac">EmitPartwordAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, 0);
+<a name="l05936"></a>05936 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_SWAP_I32)
+<a name="l05937"></a>05937 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">false</span>, 0);
+<a name="l05938"></a>05938 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_SWAP_I64)
+<a name="l05939"></a>05939 BB = <a class="code" href="classllvm_1_1PPCTargetLowering.html#a3f5d885e224a662b768922cae5006577">EmitAtomicBinary</a>(MI, BB, <span class="keyword">true</span>, 0);
+<a name="l05940"></a>05940
+<a name="l05941"></a>05941 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_CMP_SWAP_I32 ||
+<a name="l05942"></a>05942 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_CMP_SWAP_I64) {
+<a name="l05943"></a>05943 <span class="keywordtype">bool</span> is64bit = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_CMP_SWAP_I64;
+<a name="l05944"></a>05944
+<a name="l05945"></a>05945 <span class="keywordtype">unsigned</span> dest = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(0).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05946"></a>05946 <span class="keywordtype">unsigned</span> ptrA = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(1).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05947"></a>05947 <span class="keywordtype">unsigned</span> ptrB = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(2).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05948"></a>05948 <span class="keywordtype">unsigned</span> oldval = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(3).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05949"></a>05949 <span class="keywordtype">unsigned</span> newval = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(4).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l05950"></a>05950 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a5ca4af2a257043145ad650eafb4402f9">getDebugLoc</a>();
+<a name="l05951"></a>05951
+<a name="l05952"></a>05952 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *loop1MBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05953"></a>05953 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *loop2MBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05954"></a>05954 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *midMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05955"></a>05955 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *exitMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l05956"></a>05956 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, loop1MBB);
+<a name="l05957"></a>05957 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, loop2MBB);
+<a name="l05958"></a>05958 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, midMBB);
+<a name="l05959"></a>05959 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, exitMBB);
+<a name="l05960"></a>05960 exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a4caec104f2ab9fe27e8fb0da33497635">splice</a>(exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(), BB,
+<a name="l05961"></a>05961 <a class="code" href="namespacellvm.html#aa1704159f75e6eacd595962ea6d93ffe">llvm::next</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a>(MI)),
+<a name="l05962"></a>05962 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#acbc921830578e2741be6549db716c0ce">end</a>());
+<a name="l05963"></a>05963 exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#adae25a8cf267a802c72c3d6ad8c044e3">transferSuccessorsAndUpdatePHIs</a>(BB);
+<a name="l05964"></a>05964
+<a name="l05965"></a>05965 <span class="comment">// thisMBB:</span>
+<a name="l05966"></a>05966 <span class="comment">// ...</span>
+<a name="l05967"></a>05967 <span class="comment">// fallthrough --> loopMBB</span>
+<a name="l05968"></a>05968 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(loop1MBB);
+<a name="l05969"></a>05969
+<a name="l05970"></a>05970 <span class="comment">// loop1MBB:</span>
+<a name="l05971"></a>05971 <span class="comment">// l[wd]arx dest, ptr</span>
+<a name="l05972"></a>05972 <span class="comment">// cmp[wd] dest, oldval</span>
+<a name="l05973"></a>05973 <span class="comment">// bne- midMBB</span>
+<a name="l05974"></a>05974 <span class="comment">// loop2MBB:</span>
+<a name="l05975"></a>05975 <span class="comment">// st[wd]cx. newval, ptr</span>
+<a name="l05976"></a>05976 <span class="comment">// bne- loopMBB</span>
+<a name="l05977"></a>05977 <span class="comment">// b exitBB</span>
+<a name="l05978"></a>05978 <span class="comment">// midMBB:</span>
+<a name="l05979"></a>05979 <span class="comment">// st[wd]cx. dest, ptr</span>
+<a name="l05980"></a>05980 <span class="comment">// exitBB:</span>
+<a name="l05981"></a>05981 BB = loop1MBB;
+<a name="l05982"></a>05982 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::LDARX : PPC::LWARX), dest)
+<a name="l05983"></a>05983 .addReg(ptrA).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrB);
+<a name="l05984"></a>05984 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
+<a name="l05985"></a>05985 .addReg(oldval).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(dest);
+<a name="l05986"></a>05986 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::BCC))
+<a name="l05987"></a>05987 .addImm(<a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355ad9add708b3d9680d64242cf06f448462">PPC::PRED_NE</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(PPC::CR0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#aa1ec82398ade62414be35d8431c0a33b">addMBB</a>(midMBB);
+<a name="l05988"></a>05988 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(loop2MBB);
+<a name="l05989"></a>05989 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(midMBB);
+<a name="l05990"></a>05990
+<a name="l05991"></a>05991 BB = loop2MBB;
+<a name="l05992"></a>05992 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::STDCX : PPC::STWCX))
+<a name="l05993"></a>05993 .addReg(newval).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrA).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrB);
+<a name="l05994"></a>05994 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::BCC))
+<a name="l05995"></a>05995 .addImm(<a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355ad9add708b3d9680d64242cf06f448462">PPC::PRED_NE</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(PPC::CR0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#aa1ec82398ade62414be35d8431c0a33b">addMBB</a>(loop1MBB);
+<a name="l05996"></a>05996 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::B)).addMBB(exitMBB);
+<a name="l05997"></a>05997 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(loop1MBB);
+<a name="l05998"></a>05998 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(exitMBB);
+<a name="l05999"></a>05999
+<a name="l06000"></a>06000 BB = midMBB;
+<a name="l06001"></a>06001 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(BB, dl, TII-><a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(is64bit ? PPC::STDCX : PPC::STWCX))
+<a name="l06002"></a>06002 .addReg(dest).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrA).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ptrB);
+<a name="l06003"></a>06003 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(exitMBB);
+<a name="l06004"></a>06004
+<a name="l06005"></a>06005 <span class="comment">// exitMBB:</span>
+<a name="l06006"></a>06006 <span class="comment">// ...</span>
+<a name="l06007"></a>06007 BB = exitMBB;
+<a name="l06008"></a>06008 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_CMP_SWAP_I8 ||
+<a name="l06009"></a>06009 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_CMP_SWAP_I16) {
+<a name="l06010"></a>06010 <span class="comment">// We must use 64-bit registers for addresses when targeting 64-bit,</span>
+<a name="l06011"></a>06011 <span class="comment">// since we're actually doing arithmetic on them. Other registers</span>
+<a name="l06012"></a>06012 <span class="comment">// can be 32-bit.</span>
+<a name="l06013"></a>06013 <span class="keywordtype">bool</span> is64bit = PPCSubTarget.<a class="code" href="classllvm_1_1PPCSubtarget.html#abe67953ec410f1bbfe499c7a50b2dc8b">isPPC64</a>();
+<a name="l06014"></a>06014 <span class="keywordtype">bool</span> is8bit = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == PPC::ATOMIC_CMP_SWAP_I8;
+<a name="l06015"></a>06015
+<a name="l06016"></a>06016 <span class="keywordtype">unsigned</span> dest = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(0).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l06017"></a>06017 <span class="keywordtype">unsigned</span> ptrA = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(1).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l06018"></a>06018 <span class="keywordtype">unsigned</span> ptrB = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(2).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l06019"></a>06019 <span class="keywordtype">unsigned</span> oldval = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(3).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l06020"></a>06020 <span class="keywordtype">unsigned</span> newval = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(4).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>();
+<a name="l06021"></a>06021 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a5ca4af2a257043145ad650eafb4402f9">getDebugLoc</a>();
+<a name="l06022"></a>06022
+<a name="l06023"></a>06023 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *loop1MBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l06024"></a>06024 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *loop2MBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l06025"></a>06025 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *midMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l06026"></a>06026 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *exitMBB = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab2a56feb4fe943ae2362d61f3a43acca">CreateMachineBasicBlock</a>(LLVM_BB);
+<a name="l06027"></a>06027 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, loop1MBB);
+<a name="l06028"></a>06028 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, loop2MBB);
+<a name="l06029"></a>06029 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, midMBB);
+<a name="l06030"></a>06030 F-><a class="code" href="classllvm_1_1MachineFunction.html#af4c0db6d503e0ba3b8e44067023ffbba">insert</a>(It, exitMBB);
+<a name="l06031"></a>06031 exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a4caec104f2ab9fe27e8fb0da33497635">splice</a>(exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(), BB,
+<a name="l06032"></a>06032 <a class="code" href="namespacellvm.html#aa1704159f75e6eacd595962ea6d93ffe">llvm::next</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a>(MI)),
+<a name="l06033"></a>06033 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#acbc921830578e2741be6549db716c0ce">end</a>());
+<a name="l06034"></a>06034 exitMBB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#adae25a8cf267a802c72c3d6ad8c044e3">transferSuccessorsAndUpdatePHIs</a>(BB);
+<a name="l06035"></a>06035
+<a name="l06036"></a>06036 <a class="code" href="classllvm_1_1MachineRegisterInfo.html">MachineRegisterInfo</a> &RegInfo = F-><a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>();
+<a name="l06037"></a>06037 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *RC =
+<a name="l06038"></a>06038 is64bit ? (<span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *) &PPC::G8RCRegClass :
+<a name="l06039"></a>06039 (<span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *) &PPC::GPRCRegClass;
+<a name="l06040"></a>06040 <span class="keywordtype">unsigned</span> PtrReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06041"></a>06041 <span class="keywordtype">unsigned</span> Shift1Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06042"></a>06042 <span class="keywordtype">unsigned</span> ShiftReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06043"></a>06043 <span class="keywordtype">unsigned</span> NewVal2Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06044"></a>06044 <span class="keywordtype">unsigned</span> NewVal3Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06045"></a>06045 <span class="keywordtype">unsigned</span> OldVal2Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06046"></a>06046 <span class="keywordtype">unsigned</span> OldVal3Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06047"></a>06047 <span class="keywordtype">unsigned</span> MaskReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06048"></a>06048 <span class="keywordtype">unsigned</span> Mask2Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06049"></a>06049 <span class="keywordtype">unsigned</span> Mask3Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06050"></a>06050 <span class="keywordtype">unsigned</span> Tmp2Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06051"></a>06051 <span class="keywordtype">unsigned</span> Tmp4Reg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06052"></a>06052 <span class="keywordtype">unsigned</span> TmpDestReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06053"></a>06053 <span class="keywordtype">unsigned</span> Ptr1Reg;
+<a name="l06054"></a>06054 <span class="keywordtype">unsigned</span> TmpReg = RegInfo.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a76c3c7e3d4f11b4cfad37fc0449c9635">createVirtualRegister</a>(RC);
+<a name="l06055"></a>06055 <span class="keywordtype">unsigned</span> ZeroReg = is64bit ? PPC::X0 : PPC::R0;
+<a name="l06056"></a>06056 <span class="comment">// thisMBB:</span>
+<a name="l06057"></a>06057 <span class="comment">// ...</span>
+<a name="l06058"></a>06058 <span class="comment">// fallthrough --> loopMBB</span>
+<a name="l06059"></a>06059 BB-><a class="code" href="classllvm_1_1MachineBasicBlock.html#a3fcc360e6de146a370e8b0deecfa877f">addSuccessor</a>(loop1MBB);
+<a name="l06060"></a>06060
+<a name="l06061"></a>06061 <span class="comment">// The 4-byte load must be aligned, while a char or short may be</span>
+<a name="l06062"></a>06062 <span class="comment">// anywhere in the word. Hence all this nasty bookkeeping code.</span>
+<a name="l06063"></a>06063 <span class="comment">// add ptr1, ptrA, ptrB [copy if ptrA==0]</span>
+<a name="l06064"></a>06064 <span class="comment">// rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]</span>
+<a name="l06065"></a>06065 <span class="comment">// xori shift, shift1, 24 [16]</span>
+<a name="l06066"></a>06066 <span class="comment">// rlwinm ptr, ptr1, 0, 0, 29</span>
+<a name="l06067"></a>06067 <span class="comment">// slw newval2, newval, shift</span>
+<a name="l06068"></a>06068 <span class="comment">// slw oldval2, oldval,shift</span>
[... 750 lines stripped ...]
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