[llvm-commits] [www-releases] r170845 [23/55] - in /www-releases/trunk/3.2/docs: ./ CommandGuide/ HistoricalNotes/ _static/ _templates/ _themes/ _themes/llvm-theme/ _themes/llvm-theme/static/ doxygen/ doxygen/html/ llvm-theme/ llvm-theme/static/ tutorial/
Tanya Lattner
tonic at nondot.org
Thu Dec 20 22:58:17 PST 2012
Added: www-releases/trunk/3.2/docs/doxygen/html/PPCISelDAGToDAG_8cpp_source.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.2/docs/doxygen/html/PPCISelDAGToDAG_8cpp_source.html?rev=170845&view=auto
==============================================================================
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+++ www-releases/trunk/3.2/docs/doxygen/html/PPCISelDAGToDAG_8cpp_source.html Fri Dec 21 00:57:24 2012
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+<title>LLVM: PPCISelDAGToDAG.cpp Source File</title>
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+ <li class="navelem"><a class="el" href="dir_b41d254693bea6e92988e5bb1ad97e02.html">llvm-3.2.src</a> </li>
+ <li class="navelem"><a class="el" href="dir_74e9364f374e99e3aeab4fae4e196292.html">lib</a> </li>
+ <li class="navelem"><a class="el" href="dir_8a55ec9894173378e0d08f27f306eeee.html">Target</a> </li>
+ <li class="navelem"><a class="el" href="dir_294e0a5f95410d4be44cdd50e2f548b0.html">PowerPC</a> </li>
+ </ul>
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+<div class="header">
+ <div class="headertitle">
+<div class="title">PPCISelDAGToDAG.cpp</div> </div>
+</div>
+<div class="contents">
+<a href="PPCISelDAGToDAG_8cpp.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file defines a pattern matching instruction selector for PowerPC,</span>
+<a name="l00011"></a>00011 <span class="comment">// converting from a legalized dag to a PPC dag.</span>
+<a name="l00012"></a>00012 <span class="comment">//</span>
+<a name="l00013"></a>00013 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00014"></a>00014
+<a name="l00015"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#ad78e062f62e0d6e453941fb4ca843e4d">00015</a> <span class="preprocessor">#define DEBUG_TYPE "ppc-codegen"</span>
+<a name="l00016"></a>00016 <span class="preprocessor"></span><span class="preprocessor">#include "<a class="code" href="PPC_8h.html">PPC.h</a>"</span>
+<a name="l00017"></a>00017 <span class="preprocessor">#include "<a class="code" href="PPCTargetMachine_8h.html">PPCTargetMachine.h</a>"</span>
+<a name="l00018"></a>00018 <span class="preprocessor">#include "<a class="code" href="PPCPredicates_8h.html">MCTargetDesc/PPCPredicates.h</a>"</span>
+<a name="l00019"></a>00019 <span class="preprocessor">#include "<a class="code" href="MachineInstrBuilder_8h.html">llvm/CodeGen/MachineInstrBuilder.h</a>"</span>
+<a name="l00020"></a>00020 <span class="preprocessor">#include "<a class="code" href="MachineFunction_8h.html">llvm/CodeGen/MachineFunction.h</a>"</span>
+<a name="l00021"></a>00021 <span class="preprocessor">#include "<a class="code" href="MachineRegisterInfo_8h.html">llvm/CodeGen/MachineRegisterInfo.h</a>"</span>
+<a name="l00022"></a>00022 <span class="preprocessor">#include "<a class="code" href="SelectionDAG_8h.html">llvm/CodeGen/SelectionDAG.h</a>"</span>
+<a name="l00023"></a>00023 <span class="preprocessor">#include "<a class="code" href="SelectionDAGISel_8h.html">llvm/CodeGen/SelectionDAGISel.h</a>"</span>
+<a name="l00024"></a>00024 <span class="preprocessor">#include "<a class="code" href="TargetOptions_8h.html">llvm/Target/TargetOptions.h</a>"</span>
+<a name="l00025"></a>00025 <span class="preprocessor">#include "<a class="code" href="Constants_8h.html">llvm/Constants.h</a>"</span>
+<a name="l00026"></a>00026 <span class="preprocessor">#include "<a class="code" href="Function_8h.html">llvm/Function.h</a>"</span>
+<a name="l00027"></a>00027 <span class="preprocessor">#include "<a class="code" href="GlobalValue_8h.html">llvm/GlobalValue.h</a>"</span>
+<a name="l00028"></a>00028 <span class="preprocessor">#include "<a class="code" href="Intrinsics_8h.html">llvm/Intrinsics.h</a>"</span>
+<a name="l00029"></a>00029 <span class="preprocessor">#include "<a class="code" href="Debug_8h.html">llvm/Support/Debug.h</a>"</span>
+<a name="l00030"></a>00030 <span class="preprocessor">#include "<a class="code" href="MathExtras_8h.html">llvm/Support/MathExtras.h</a>"</span>
+<a name="l00031"></a>00031 <span class="preprocessor">#include "<a class="code" href="ErrorHandling_8h.html">llvm/Support/ErrorHandling.h</a>"</span>
+<a name="l00032"></a>00032 <span class="preprocessor">#include "<a class="code" href="raw__ostream_8h.html">llvm/Support/raw_ostream.h</a>"</span>
+<a name="l00033"></a>00033 <span class="keyword">using namespace </span>llvm;
+<a name="l00034"></a>00034
+<a name="l00035"></a>00035 <span class="keyword">namespace </span>{
+<a name="l00036"></a>00036 <span class="comment">//===--------------------------------------------------------------------===//</span><span class="comment"></span>
+<a name="l00037"></a>00037 <span class="comment"> /// PPCDAGToDAGISel - PPC specific code to select PPC machine</span>
+<a name="l00038"></a>00038 <span class="comment"> /// instructions for SelectionDAG operations.</span>
+<a name="l00039"></a>00039 <span class="comment"> ///</span>
+<a name="l00040"></a>00040 <span class="comment"></span> <span class="keyword">class </span>PPCDAGToDAGISel : <span class="keyword">public</span> <a class="code" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a> {
+<a name="l00041"></a>00041 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCTargetMachine.html">PPCTargetMachine</a> &TM;
+<a name="l00042"></a>00042 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCTargetLowering.html">PPCTargetLowering</a> &PPCLowering;
+<a name="l00043"></a>00043 <span class="keyword">const</span> <a class="code" href="classllvm_1_1PPCSubtarget.html">PPCSubtarget</a> &PPCSubTarget;
+<a name="l00044"></a>00044 <span class="keywordtype">unsigned</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">GlobalBaseReg</a>;
+<a name="l00045"></a>00045 <span class="keyword">public</span>:
+<a name="l00046"></a>00046 <span class="keyword">explicit</span> PPCDAGToDAGISel(<a class="code" href="classllvm_1_1PPCTargetMachine.html">PPCTargetMachine</a> &tm)
+<a name="l00047"></a>00047 : <a class="code" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a>(tm), TM(tm),
+<a name="l00048"></a>00048 PPCLowering(*TM.getTargetLowering()),
+<a name="l00049"></a>00049 PPCSubTarget(*TM.getSubtargetImpl()) {}
+<a name="l00050"></a>00050
+<a name="l00051"></a>00051 <span class="keyword">virtual</span> <span class="keywordtype">bool</span> runOnMachineFunction(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF) {
+<a name="l00052"></a>00052 <span class="comment">// Make sure we re-emit a set of the global base reg if necessary</span>
+<a name="l00053"></a>00053 <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">GlobalBaseReg</a> = 0;
+<a name="l00054"></a>00054 <a class="code" href="classllvm_1_1SelectionDAGISel.html#ac27df519719929bb886ae92fca30b6d2">SelectionDAGISel::runOnMachineFunction</a>(MF);
+<a name="l00055"></a>00055
+<a name="l00056"></a>00056 <span class="keywordflow">if</span> (!PPCSubTarget.isSVR4ABI())
+<a name="l00057"></a>00057 InsertVRSaveCode(MF);
+<a name="l00058"></a>00058
+<a name="l00059"></a>00059 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00060"></a>00060 }
+<a name="l00061"></a>00061 <span class="comment"></span>
+<a name="l00062"></a>00062 <span class="comment"> /// getI32Imm - Return a target constant with the specified value, of type</span>
+<a name="l00063"></a>00063 <span class="comment"> /// i32.</span>
+<a name="l00064"></a>00064 <span class="comment"></span> <span class="keyword">inline</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> getI32Imm(<span class="keywordtype">unsigned</span> Imm) {
+<a name="l00065"></a>00065 <span class="keywordflow">return</span> CurDAG->getTargetConstant(Imm, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00066"></a>00066 }
+<a name="l00067"></a>00067 <span class="comment"></span>
+<a name="l00068"></a>00068 <span class="comment"> /// getI64Imm - Return a target constant with the specified value, of type</span>
+<a name="l00069"></a>00069 <span class="comment"> /// i64.</span>
+<a name="l00070"></a>00070 <span class="comment"></span> <span class="keyword">inline</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> getI64Imm(uint64_t Imm) {
+<a name="l00071"></a>00071 <span class="keywordflow">return</span> CurDAG->getTargetConstant(Imm, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l00072"></a>00072 }
+<a name="l00073"></a>00073 <span class="comment"></span>
+<a name="l00074"></a>00074 <span class="comment"> /// getSmallIPtrImm - Return a target constant of pointer type.</span>
+<a name="l00075"></a>00075 <span class="comment"></span> <span class="keyword">inline</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> getSmallIPtrImm(<span class="keywordtype">unsigned</span> Imm) {
+<a name="l00076"></a>00076 <span class="keywordflow">return</span> CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
+<a name="l00077"></a>00077 }
+<a name="l00078"></a>00078 <span class="comment"></span>
+<a name="l00079"></a>00079 <span class="comment"> /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s</span>
+<a name="l00080"></a>00080 <span class="comment"> /// with any number of 0s on either side. The 1s are allowed to wrap from</span>
+<a name="l00081"></a>00081 <span class="comment"> /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.</span>
+<a name="l00082"></a>00082 <span class="comment"> /// 0x0F0F0000 is not, since all 1s are not contiguous.</span>
+<a name="l00083"></a>00083 <span class="comment"></span> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="InstCombineAndOrXor_8cpp.html#add947a35dd442e049fda602d9dc9cd20">isRunOfOnes</a>(<span class="keywordtype">unsigned</span> Val, <span class="keywordtype">unsigned</span> &MB, <span class="keywordtype">unsigned</span> &ME);
+<a name="l00084"></a>00084
+<a name="l00085"></a>00085 <span class="comment"></span>
+<a name="l00086"></a>00086 <span class="comment"> /// isRotateAndMask - Returns true if Mask and Shift can be folded into a</span>
+<a name="l00087"></a>00087 <span class="comment"> /// rotate and mask opcode and mask operation.</span>
+<a name="l00088"></a>00088 <span class="comment"></span> <span class="keyword">static</span> <span class="keywordtype">bool</span> isRotateAndMask(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="regcomp_8c.html#a0240ac851181b84ac374872dc5434ee4">N</a>, <span class="keywordtype">unsigned</span> Mask, <span class="keywordtype">bool</span> isShiftMask,
+<a name="l00089"></a>00089 <span class="keywordtype">unsigned</span> &SH, <span class="keywordtype">unsigned</span> &MB, <span class="keywordtype">unsigned</span> &ME);
+<a name="l00090"></a>00090 <span class="comment"></span>
+<a name="l00091"></a>00091 <span class="comment"> /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC</span>
+<a name="l00092"></a>00092 <span class="comment"> /// base register. Return the virtual register that holds this value.</span>
+<a name="l00093"></a>00093 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *getGlobalBaseReg();
+<a name="l00094"></a>00094
+<a name="l00095"></a>00095 <span class="comment">// Select - Convert the specified operand from a target-independent to a</span>
+<a name="l00096"></a>00096 <span class="comment">// target-specific node if it hasn't already been changed.</span>
+<a name="l00097"></a>00097 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="namespacellvm.html#af3ab12efdd6b4902d711e72b7a81f13b">Select</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00098"></a>00098
+<a name="l00099"></a>00099 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectBitfieldInsert(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00100"></a>00100 <span class="comment"></span>
+<a name="l00101"></a>00101 <span class="comment"> /// SelectCC - Select a comparison of the specified values with the</span>
+<a name="l00102"></a>00102 <span class="comment"> /// specified condition code, returning the CR# of the expression.</span>
+<a name="l00103"></a>00103 <span class="comment"></span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SelectCC(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHS, <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl);
+<a name="l00104"></a>00104 <span class="comment"></span>
+<a name="l00105"></a>00105 <span class="comment"> /// SelectAddrImm - Returns true if the address N can be represented by</span>
+<a name="l00106"></a>00106 <span class="comment"> /// a base register plus a signed 16-bit displacement [r+imm].</span>
+<a name="l00107"></a>00107 <span class="comment"></span> <span class="keywordtype">bool</span> SelectAddrImm(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Disp,
+<a name="l00108"></a>00108 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base) {
+<a name="l00109"></a>00109 <span class="keywordflow">return</span> PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
+<a name="l00110"></a>00110 }
+<a name="l00111"></a>00111 <span class="comment"></span>
+<a name="l00112"></a>00112 <span class="comment"> /// SelectAddrImmOffs - Return true if the operand is valid for a preinc</span>
+<a name="l00113"></a>00113 <span class="comment"> /// immediate field. Because preinc imms have already been validated, just</span>
+<a name="l00114"></a>00114 <span class="comment"> /// accept it.</span>
+<a name="l00115"></a>00115 <span class="comment"></span> <span class="keywordtype">bool</span> SelectAddrImmOffs(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Out)<span class="keyword"> const </span>{
+<a name="l00116"></a>00116 <span class="keywordflow">if</span> (isa<ConstantSDNode>(N) || N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abcb9c462158b362a5edc6a1d754c9edb">PPCISD::Lo</a> ||
+<a name="l00117"></a>00117 N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a>) {
+<a name="l00118"></a>00118 Out = N;
+<a name="l00119"></a>00119 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00120"></a>00120 }
+<a name="l00121"></a>00121
+<a name="l00122"></a>00122 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00123"></a>00123 }
+<a name="l00124"></a>00124 <span class="comment"></span>
+<a name="l00125"></a>00125 <span class="comment"> /// SelectAddrIdxOffs - Return true if the operand is valid for a preinc</span>
+<a name="l00126"></a>00126 <span class="comment"> /// index field. Because preinc imms have already been validated, just</span>
+<a name="l00127"></a>00127 <span class="comment"> /// accept it.</span>
+<a name="l00128"></a>00128 <span class="comment"></span> <span class="keywordtype">bool</span> SelectAddrIdxOffs(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Out)<span class="keyword"> const </span>{
+<a name="l00129"></a>00129 <span class="keywordflow">if</span> (isa<ConstantSDNode>(N) || N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66abcb9c462158b362a5edc6a1d754c9edb">PPCISD::Lo</a> ||
+<a name="l00130"></a>00130 N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a>)
+<a name="l00131"></a>00131 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00132"></a>00132
+<a name="l00133"></a>00133 Out = N;
+<a name="l00134"></a>00134 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00135"></a>00135 }
+<a name="l00136"></a>00136 <span class="comment"></span>
+<a name="l00137"></a>00137 <span class="comment"> /// SelectAddrIdx - Given the specified addressed, check to see if it can be</span>
+<a name="l00138"></a>00138 <span class="comment"> /// represented as an indexed [r+r] operation. Returns false if it can</span>
+<a name="l00139"></a>00139 <span class="comment"> /// be represented by [r+imm], which are preferred.</span>
+<a name="l00140"></a>00140 <span class="comment"></span> <span class="keywordtype">bool</span> SelectAddrIdx(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Index) {
+<a name="l00141"></a>00141 <span class="keywordflow">return</span> PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
+<a name="l00142"></a>00142 }
+<a name="l00143"></a>00143 <span class="comment"></span>
+<a name="l00144"></a>00144 <span class="comment"> /// SelectAddrIdxOnly - Given the specified addressed, force it to be</span>
+<a name="l00145"></a>00145 <span class="comment"> /// represented as an indexed [r+r] operation.</span>
+<a name="l00146"></a>00146 <span class="comment"></span> <span class="keywordtype">bool</span> SelectAddrIdxOnly(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Index) {
+<a name="l00147"></a>00147 <span class="keywordflow">return</span> PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
+<a name="l00148"></a>00148 }
+<a name="l00149"></a>00149 <span class="comment"></span>
+<a name="l00150"></a>00150 <span class="comment"> /// SelectAddrImmShift - Returns true if the address N can be represented by</span>
+<a name="l00151"></a>00151 <span class="comment"> /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable</span>
+<a name="l00152"></a>00152 <span class="comment"> /// for use by STD and friends.</span>
+<a name="l00153"></a>00153 <span class="comment"></span> <span class="keywordtype">bool</span> SelectAddrImmShift(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Disp, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base) {
+<a name="l00154"></a>00154 <span class="keywordflow">return</span> PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
+<a name="l00155"></a>00155 }
+<a name="l00156"></a>00156 <span class="comment"></span>
+<a name="l00157"></a>00157 <span class="comment"> /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for</span>
+<a name="l00158"></a>00158 <span class="comment"> /// inline asm expressions. It is always correct to compute the value into</span>
+<a name="l00159"></a>00159 <span class="comment"> /// a register. The case of adding a (possibly relocatable) constant to a</span>
+<a name="l00160"></a>00160 <span class="comment"> /// register can be improved, but it is wrong to substitute Reg+Reg for</span>
+<a name="l00161"></a>00161 <span class="comment"> /// Reg in an asm, because the load or store opcode would have to change.</span>
+<a name="l00162"></a>00162 <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">bool</span> SelectInlineAsmMemoryOperand(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Op,
+<a name="l00163"></a>00163 <span class="keywordtype">char</span> ConstraintCode,
+<a name="l00164"></a>00164 std::vector<SDValue> &OutOps) {
+<a name="l00165"></a>00165 OutOps.push_back(Op);
+<a name="l00166"></a>00166 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00167"></a>00167 }
+<a name="l00168"></a>00168
+<a name="l00169"></a>00169 <span class="keywordtype">void</span> InsertVRSaveCode(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF);
+<a name="l00170"></a>00170
+<a name="l00171"></a>00171 <span class="keyword">virtual</span> <span class="keyword">const</span> <span class="keywordtype">char</span> *getPassName()<span class="keyword"> const </span>{
+<a name="l00172"></a>00172 <span class="keywordflow">return</span> <span class="stringliteral">"PowerPC DAG->DAG Pattern Instruction Selection"</span>;
+<a name="l00173"></a>00173 }
+<a name="l00174"></a>00174
+<a name="l00175"></a>00175 <span class="comment">// Include the pieces autogenerated from the target description.</span>
+<a name="l00176"></a>00176 <span class="preprocessor">#include "PPCGenDAGISel.inc"</span>
+<a name="l00177"></a>00177
+<a name="l00178"></a>00178 <span class="keyword">private</span>:
+<a name="l00179"></a>00179 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectSETCC(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00180"></a>00180 };
+<a name="l00181"></a>00181 }
+<a name="l00182"></a>00182 <span class="comment"></span>
+<a name="l00183"></a>00183 <span class="comment">/// InsertVRSaveCode - Once the entire function has been instruction selected,</span>
+<a name="l00184"></a>00184 <span class="comment">/// all virtual registers are created and all machine instructions are built,</span>
+<a name="l00185"></a>00185 <span class="comment">/// check to see if we need to save/restore VRSAVE. If so, do it.</span>
+<a name="l00186"></a>00186 <span class="comment"></span><span class="keywordtype">void</span> PPCDAGToDAGISel::InsertVRSaveCode(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &Fn) {
+<a name="l00187"></a>00187 <span class="comment">// Check to see if this function uses vector registers, which means we have to</span>
+<a name="l00188"></a>00188 <span class="comment">// save and restore the VRSAVE register and update it with the regs we use.</span>
+<a name="l00189"></a>00189 <span class="comment">//</span>
+<a name="l00190"></a>00190 <span class="comment">// In this case, there will be virtual registers of vector type created</span>
+<a name="l00191"></a>00191 <span class="comment">// by the scheduler. Detect them now.</span>
+<a name="l00192"></a>00192 <span class="keywordtype">bool</span> HasVectorVReg = <span class="keyword">false</span>;
+<a name="l00193"></a>00193 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
+<a name="l00194"></a>00194 <span class="keywordtype">unsigned</span> <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a> = <a class="code" href="classllvm_1_1TargetRegisterInfo.html#a70cd177cd3198c912817a21f373b5651">TargetRegisterInfo::index2VirtReg</a>(i);
+<a name="l00195"></a>00195 <span class="keywordflow">if</span> (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
+<a name="l00196"></a>00196 HasVectorVReg = <span class="keyword">true</span>;
+<a name="l00197"></a>00197 <span class="keywordflow">break</span>;
+<a name="l00198"></a>00198 }
+<a name="l00199"></a>00199 }
+<a name="l00200"></a>00200 <span class="keywordflow">if</span> (!HasVectorVReg) <span class="keywordflow">return</span>; <span class="comment">// nothing to do.</span>
+<a name="l00201"></a>00201
+<a name="l00202"></a>00202 <span class="comment">// If we have a vector register, we want to emit code into the entry and exit</span>
+<a name="l00203"></a>00203 <span class="comment">// blocks to save and restore the VRSAVE register. We do this here (instead</span>
+<a name="l00204"></a>00204 <span class="comment">// of marking all vector instructions as clobbering VRSAVE) for two reasons:</span>
+<a name="l00205"></a>00205 <span class="comment">//</span>
+<a name="l00206"></a>00206 <span class="comment">// 1. This (trivially) reduces the load on the register allocator, by not</span>
+<a name="l00207"></a>00207 <span class="comment">// having to represent the live range of the VRSAVE register.</span>
+<a name="l00208"></a>00208 <span class="comment">// 2. This (more significantly) allows us to create a temporary virtual</span>
+<a name="l00209"></a>00209 <span class="comment">// register to hold the saved VRSAVE value, allowing this temporary to be</span>
+<a name="l00210"></a>00210 <span class="comment">// register allocated, instead of forcing it to be spilled to the stack.</span>
+<a name="l00211"></a>00211
+<a name="l00212"></a>00212 <span class="comment">// Create two vregs - one to hold the VRSAVE register that is live-in to the</span>
+<a name="l00213"></a>00213 <span class="comment">// function and one for the value after having bits or'd into it.</span>
+<a name="l00214"></a>00214 <span class="keywordtype">unsigned</span> InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
+<a name="l00215"></a>00215 <span class="keywordtype">unsigned</span> UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
+<a name="l00216"></a>00216
+<a name="l00217"></a>00217 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> &TII = *TM.getInstrInfo();
+<a name="l00218"></a>00218 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &EntryBB = *Fn.<a class="code" href="classllvm_1_1MachineFunction.html#ab0789854909cf47f640a85fa2bac29c7">begin</a>();
+<a name="l00219"></a>00219 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl;
+<a name="l00220"></a>00220 <span class="comment">// Emit the following code into the entry block:</span>
+<a name="l00221"></a>00221 <span class="comment">// InVRSAVE = MFVRSAVE</span>
+<a name="l00222"></a>00222 <span class="comment">// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE</span>
+<a name="l00223"></a>00223 <span class="comment">// MTVRSAVE UpdatedVRSAVE</span>
+<a name="l00224"></a>00224 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> IP = EntryBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(); <span class="comment">// Insert Point</span>
+<a name="l00225"></a>00225 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(EntryBB, IP, dl, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::MFVRSAVE), InVRSAVE);
+<a name="l00226"></a>00226 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(EntryBB, IP, dl, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::UPDATE_VRSAVE),
+<a name="l00227"></a>00227 UpdatedVRSAVE).addReg(InVRSAVE);
+<a name="l00228"></a>00228 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(EntryBB, IP, dl, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
+<a name="l00229"></a>00229
+<a name="l00230"></a>00230 <span class="comment">// Find all return blocks, outputting a restore in each epilog.</span>
+<a name="l00231"></a>00231 <span class="keywordflow">for</span> (<a class="code" href="classllvm_1_1MachineFunction.html#a340712de3e78fec11c338735cab17df7">MachineFunction::iterator</a> BB = Fn.<a class="code" href="classllvm_1_1MachineFunction.html#ab0789854909cf47f640a85fa2bac29c7">begin</a>(), E = Fn.<a class="code" href="classllvm_1_1MachineFunction.html#a9d017af749f76484cb9aec9ff6e4330c">end</a>(); BB != E; ++BB) {
+<a name="l00232"></a>00232 <span class="keywordflow">if</span> (!BB->empty() && BB->back().isReturn()) {
+<a name="l00233"></a>00233 IP = BB->end(); --IP;
+<a name="l00234"></a>00234
+<a name="l00235"></a>00235 <span class="comment">// Skip over all terminator instructions, which are part of the return</span>
+<a name="l00236"></a>00236 <span class="comment">// sequence.</span>
+<a name="l00237"></a>00237 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> I2 = IP;
+<a name="l00238"></a>00238 <span class="keywordflow">while</span> (I2 != BB->begin() && (--I2)->isTerminator())
+<a name="l00239"></a>00239 IP = I2;
+<a name="l00240"></a>00240
+<a name="l00241"></a>00241 <span class="comment">// Emit: MTVRSAVE InVRSave</span>
+<a name="l00242"></a>00242 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(*BB, IP, dl, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::MTVRSAVE)).addReg(InVRSAVE);
+<a name="l00243"></a>00243 }
+<a name="l00244"></a>00244 }
+<a name="l00245"></a>00245 }
+<a name="l00246"></a>00246
+<a name="l00247"></a>00247 <span class="comment"></span>
+<a name="l00248"></a>00248 <span class="comment">/// getGlobalBaseReg - Output the instructions required to put the</span>
+<a name="l00249"></a>00249 <span class="comment">/// base address to use for accessing globals into a register.</span>
+<a name="l00250"></a>00250 <span class="comment">///</span>
+<a name="l00251"></a>00251 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *PPCDAGToDAGISel::getGlobalBaseReg() {
+<a name="l00252"></a>00252 <span class="keywordflow">if</span> (!<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">GlobalBaseReg</a>) {
+<a name="l00253"></a>00253 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> &TII = *TM.getInstrInfo();
+<a name="l00254"></a>00254 <span class="comment">// Insert the set of GlobalBaseReg into the first MBB of the function</span>
+<a name="l00255"></a>00255 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &FirstMBB = MF-><a class="code" href="classllvm_1_1MachineBasicBlock.html#acb4d7c02992f3821f3e3432b6c65de49">front</a>();
+<a name="l00256"></a>00256 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MBBI = FirstMBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>();
+<a name="l00257"></a>00257 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl;
+<a name="l00258"></a>00258
+<a name="l00259"></a>00259 <span class="keywordflow">if</span> (PPCLowering.getPointerTy() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>) {
+<a name="l00260"></a>00260 <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">GlobalBaseReg</a> = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
+<a name="l00261"></a>00261 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(FirstMBB, MBBI, dl, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::MovePCtoLR));
+<a name="l00262"></a>00262 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(FirstMBB, MBBI, dl, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::MFLR), <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">GlobalBaseReg</a>);
+<a name="l00263"></a>00263 } <span class="keywordflow">else</span> {
+<a name="l00264"></a>00264 <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">GlobalBaseReg</a> = RegInfo->createVirtualRegister(&PPC::G8RCRegClass);
+<a name="l00265"></a>00265 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(FirstMBB, MBBI, dl, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::MovePCtoLR8));
+<a name="l00266"></a>00266 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(FirstMBB, MBBI, dl, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(PPC::MFLR8), <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">GlobalBaseReg</a>);
+<a name="l00267"></a>00267 }
+<a name="l00268"></a>00268 }
+<a name="l00269"></a>00269 <span class="keywordflow">return</span> CurDAG->getRegister(<a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">GlobalBaseReg</a>,
+<a name="l00270"></a>00270 PPCLowering.getPointerTy()).getNode();
+<a name="l00271"></a>00271 }
+<a name="l00272"></a>00272 <span class="comment"></span>
+<a name="l00273"></a>00273 <span class="comment">/// isIntS16Immediate - This method tests to see if the node is either a 32-bit</span>
+<a name="l00274"></a>00274 <span class="comment">/// or 64-bit immediate, and if the value can be accurately represented as a</span>
+<a name="l00275"></a>00275 <span class="comment">/// sign extension from a 16-bit value. If so, this returns true and the</span>
+<a name="l00276"></a>00276 <span class="comment">/// immediate.</span>
+<a name="l00277"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">00277</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">short</span> &Imm) {
+<a name="l00278"></a>00278 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a>)
+<a name="l00279"></a>00279 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00280"></a>00280
+<a name="l00281"></a>00281 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00282"></a>00282 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>)
+<a name="l00283"></a>00283 <span class="keywordflow">return</span> Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00284"></a>00284 <span class="keywordflow">else</span>
+<a name="l00285"></a>00285 <span class="keywordflow">return</span> Imm == (<a class="code" href="classint64__t.html">int64_t</a>)cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00286"></a>00286 }
+<a name="l00287"></a>00287
+<a name="l00288"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#a5a2abfa58ea2a3349750c7f4b4a11694">00288</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op, <span class="keywordtype">short</span> &Imm) {
+<a name="l00289"></a>00289 <span class="keywordflow">return</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(Op.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm);
+<a name="l00290"></a>00290 }
+<a name="l00291"></a>00291
+<a name="l00292"></a>00292 <span class="comment"></span>
+<a name="l00293"></a>00293 <span class="comment">/// isInt32Immediate - This method tests to see if the node is a 32-bit constant</span>
+<a name="l00294"></a>00294 <span class="comment">/// operand. If so Imm will receive the 32-bit value.</span>
+<a name="l00295"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">00295</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">unsigned</span> &Imm) {
+<a name="l00296"></a>00296 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a> && N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>) {
+<a name="l00297"></a>00297 Imm = cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00298"></a>00298 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00299"></a>00299 }
+<a name="l00300"></a>00300 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00301"></a>00301 }
+<a name="l00302"></a>00302 <span class="comment"></span>
+<a name="l00303"></a>00303 <span class="comment">/// isInt64Immediate - This method tests to see if the node is a 64-bit constant</span>
+<a name="l00304"></a>00304 <span class="comment">/// operand. If so Imm will receive the 64-bit value.</span>
+<a name="l00305"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#a7312dc1e31cba7889c13ff9ada91ff15">00305</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#a7312dc1e31cba7889c13ff9ada91ff15">isInt64Immediate</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, uint64_t &Imm) {
+<a name="l00306"></a>00306 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a> && N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>) {
+<a name="l00307"></a>00307 Imm = cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00308"></a>00308 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00309"></a>00309 }
+<a name="l00310"></a>00310 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00311"></a>00311 }
+<a name="l00312"></a>00312
+<a name="l00313"></a>00313 <span class="comment">// isInt32Immediate - This method tests to see if a constant operand.</span>
+<a name="l00314"></a>00314 <span class="comment">// If so Imm will receive the 32 bit value.</span>
+<a name="l00315"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#ace33718e35b67e1af759c3ec4c8f8443">00315</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <span class="keywordtype">unsigned</span> &Imm) {
+<a name="l00316"></a>00316 <span class="keywordflow">return</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm);
+<a name="l00317"></a>00317 }
+<a name="l00318"></a>00318
+<a name="l00319"></a>00319
+<a name="l00320"></a>00320 <span class="comment">// isOpcWithIntImmediate - This method tests to see if the node is a specific</span>
+<a name="l00321"></a>00321 <span class="comment">// opcode and that it has a immediate integer right operand.</span>
+<a name="l00322"></a>00322 <span class="comment">// If so Imm will receive the 32 bit value.</span>
+<a name="l00323"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">00323</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">isOpcWithIntImmediate</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">unsigned</span> Opc, <span class="keywordtype">unsigned</span>& Imm) {
+<a name="l00324"></a>00324 <span class="keywordflow">return</span> N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() == Opc
+<a name="l00325"></a>00325 && <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm);
+<a name="l00326"></a>00326 }
+<a name="l00327"></a>00327
+<a name="l00328"></a>00328 <span class="keywordtype">bool</span> <a class="code" href="InstCombineAndOrXor_8cpp.html#add947a35dd442e049fda602d9dc9cd20">PPCDAGToDAGISel::isRunOfOnes</a>(<span class="keywordtype">unsigned</span> Val, <span class="keywordtype">unsigned</span> &MB, <span class="keywordtype">unsigned</span> &ME) {
+<a name="l00329"></a>00329 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#a211070f2010783c96ec5e11a12519575">isShiftedMask_32</a>(Val)) {
+<a name="l00330"></a>00330 <span class="comment">// look for the first non-zero bit</span>
+<a name="l00331"></a>00331 MB = <a class="code" href="namespacellvm.html#ad49c0b18ebe7aaea47cb5ff7396ec953">CountLeadingZeros_32</a>(Val);
+<a name="l00332"></a>00332 <span class="comment">// look for the first zero bit after the run of ones</span>
+<a name="l00333"></a>00333 ME = <a class="code" href="namespacellvm.html#ad49c0b18ebe7aaea47cb5ff7396ec953">CountLeadingZeros_32</a>((Val - 1) ^ Val);
+<a name="l00334"></a>00334 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00335"></a>00335 } <span class="keywordflow">else</span> {
+<a name="l00336"></a>00336 Val = ~Val; <span class="comment">// invert mask</span>
+<a name="l00337"></a>00337 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#a211070f2010783c96ec5e11a12519575">isShiftedMask_32</a>(Val)) {
+<a name="l00338"></a>00338 <span class="comment">// effectively look for the first zero bit</span>
+<a name="l00339"></a>00339 ME = <a class="code" href="namespacellvm.html#ad49c0b18ebe7aaea47cb5ff7396ec953">CountLeadingZeros_32</a>(Val) - 1;
+<a name="l00340"></a>00340 <span class="comment">// effectively look for the first one bit after the run of zeros</span>
+<a name="l00341"></a>00341 MB = <a class="code" href="namespacellvm.html#ad49c0b18ebe7aaea47cb5ff7396ec953">CountLeadingZeros_32</a>((Val - 1) ^ Val) + 1;
+<a name="l00342"></a>00342 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00343"></a>00343 }
+<a name="l00344"></a>00344 }
+<a name="l00345"></a>00345 <span class="comment">// no run present</span>
+<a name="l00346"></a>00346 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00347"></a>00347 }
+<a name="l00348"></a>00348
+<a name="l00349"></a>00349 <span class="keywordtype">bool</span> PPCDAGToDAGISel::isRotateAndMask(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">unsigned</span> Mask,
+<a name="l00350"></a>00350 <span class="keywordtype">bool</span> isShiftMask, <span class="keywordtype">unsigned</span> &SH,
+<a name="l00351"></a>00351 <span class="keywordtype">unsigned</span> &MB, <span class="keywordtype">unsigned</span> &ME) {
+<a name="l00352"></a>00352 <span class="comment">// Don't even go down this path for i64, since different logic will be</span>
+<a name="l00353"></a>00353 <span class="comment">// necessary for rldicl/rldicr/rldimi.</span>
+<a name="l00354"></a>00354 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) != <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>)
+<a name="l00355"></a>00355 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00356"></a>00356
+<a name="l00357"></a>00357 <span class="keywordtype">unsigned</span> Shift = 32;
+<a name="l00358"></a>00358 <span class="keywordtype">unsigned</span> Indeterminant = ~0; <span class="comment">// bit mask marking indeterminant results</span>
+<a name="l00359"></a>00359 <span class="keywordtype">unsigned</span> Opcode = N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>();
+<a name="l00360"></a>00360 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#abc5c2f1d47a517373030133c6a102106">getNumOperands</a>() != 2 ||
+<a name="l00361"></a>00361 !<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Shift) || (Shift > 31))
+<a name="l00362"></a>00362 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00363"></a>00363
+<a name="l00364"></a>00364 <span class="keywordflow">if</span> (Opcode == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a>) {
+<a name="l00365"></a>00365 <span class="comment">// apply shift left to mask if it comes first</span>
+<a name="l00366"></a>00366 <span class="keywordflow">if</span> (isShiftMask) Mask = Mask << Shift;
+<a name="l00367"></a>00367 <span class="comment">// determine which bits are made indeterminant by shift</span>
+<a name="l00368"></a>00368 Indeterminant = ~(0xFFFFFFFFu << Shift);
+<a name="l00369"></a>00369 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Opcode == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>) {
+<a name="l00370"></a>00370 <span class="comment">// apply shift right to mask if it comes first</span>
+<a name="l00371"></a>00371 <span class="keywordflow">if</span> (isShiftMask) Mask = Mask >> Shift;
+<a name="l00372"></a>00372 <span class="comment">// determine which bits are made indeterminant by shift</span>
+<a name="l00373"></a>00373 Indeterminant = ~(0xFFFFFFFFu >> Shift);
+<a name="l00374"></a>00374 <span class="comment">// adjust for the left rotate</span>
+<a name="l00375"></a>00375 Shift = 32 - Shift;
+<a name="l00376"></a>00376 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Opcode == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae8f8f81d8e8d7a557d67622c05786f1d">ISD::ROTL</a>) {
+<a name="l00377"></a>00377 Indeterminant = 0;
+<a name="l00378"></a>00378 } <span class="keywordflow">else</span> {
+<a name="l00379"></a>00379 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00380"></a>00380 }
+<a name="l00381"></a>00381
+<a name="l00382"></a>00382 <span class="comment">// if the mask doesn't intersect any Indeterminant bits</span>
+<a name="l00383"></a>00383 <span class="keywordflow">if</span> (Mask && !(Mask & Indeterminant)) {
+<a name="l00384"></a>00384 SH = Shift & 31;
+<a name="l00385"></a>00385 <span class="comment">// make sure the mask is still a mask (wrap arounds may not be)</span>
+<a name="l00386"></a>00386 <span class="keywordflow">return</span> <a class="code" href="InstCombineAndOrXor_8cpp.html#add947a35dd442e049fda602d9dc9cd20">isRunOfOnes</a>(Mask, MB, ME);
+<a name="l00387"></a>00387 }
+<a name="l00388"></a>00388 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00389"></a>00389 }
+<a name="l00390"></a>00390 <span class="comment"></span>
+<a name="l00391"></a>00391 <span class="comment">/// SelectBitfieldInsert - turn an or of two masked values into</span>
+<a name="l00392"></a>00392 <span class="comment">/// the rotate left word immediate then mask insert (rlwimi) instruction.</span>
+<a name="l00393"></a>00393 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *PPCDAGToDAGISel::SelectBitfieldInsert(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l00394"></a>00394 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l00395"></a>00395 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l00396"></a>00396 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l00397"></a>00397
+<a name="l00398"></a>00398 <a class="code" href="classllvm_1_1APInt.html" title="Class for arbitrary precision integers.">APInt</a> LKZ, LKO, RKZ, RKO;
+<a name="l00399"></a>00399 CurDAG->ComputeMaskedBits(Op0, LKZ, LKO);
+<a name="l00400"></a>00400 CurDAG->ComputeMaskedBits(Op1, RKZ, RKO);
+<a name="l00401"></a>00401
+<a name="l00402"></a>00402 <span class="keywordtype">unsigned</span> TargetMask = LKZ.<a class="code" href="classllvm_1_1APInt.html#a7dc983ebf0eb2d255fa90a67063c72e2" title="Get zero extended value.">getZExtValue</a>();
+<a name="l00403"></a>00403 <span class="keywordtype">unsigned</span> InsertMask = RKZ.<a class="code" href="classllvm_1_1APInt.html#a7dc983ebf0eb2d255fa90a67063c72e2" title="Get zero extended value.">getZExtValue</a>();
+<a name="l00404"></a>00404
+<a name="l00405"></a>00405 <span class="keywordflow">if</span> ((TargetMask | InsertMask) == 0xFFFFFFFF) {
+<a name="l00406"></a>00406 <span class="keywordtype">unsigned</span> Op0Opc = Op0.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>();
+<a name="l00407"></a>00407 <span class="keywordtype">unsigned</span> Op1Opc = Op1.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>();
+<a name="l00408"></a>00408 <span class="keywordtype">unsigned</span> <a class="code" href="classllvm_1_1Value.html" title="LLVM Value Representation.">Value</a>, SH = 0;
+<a name="l00409"></a>00409 TargetMask = ~TargetMask;
+<a name="l00410"></a>00410 InsertMask = ~InsertMask;
+<a name="l00411"></a>00411
+<a name="l00412"></a>00412 <span class="comment">// If the LHS has a foldable shift and the RHS does not, then swap it to the</span>
+<a name="l00413"></a>00413 <span class="comment">// RHS so that we can fold the shift into the insert.</span>
+<a name="l00414"></a>00414 <span class="keywordflow">if</span> (Op0Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a> && Op1Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>) {
+<a name="l00415"></a>00415 <span class="keywordflow">if</span> (Op0.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a> ||
+<a name="l00416"></a>00416 Op0.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>) {
+<a name="l00417"></a>00417 <span class="keywordflow">if</span> (Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a> &&
+<a name="l00418"></a>00418 Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>) {
+<a name="l00419"></a>00419 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(Op0, Op1);
+<a name="l00420"></a>00420 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(Op0Opc, Op1Opc);
+<a name="l00421"></a>00421 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(TargetMask, InsertMask);
+<a name="l00422"></a>00422 }
+<a name="l00423"></a>00423 }
+<a name="l00424"></a>00424 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Op0Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a> || Op0Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>) {
+<a name="l00425"></a>00425 <span class="keywordflow">if</span> (Op1Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a> && Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a> &&
+<a name="l00426"></a>00426 Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>) {
+<a name="l00427"></a>00427 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(Op0, Op1);
+<a name="l00428"></a>00428 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(Op0Opc, Op1Opc);
+<a name="l00429"></a>00429 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(TargetMask, InsertMask);
+<a name="l00430"></a>00430 }
+<a name="l00431"></a>00431 }
+<a name="l00432"></a>00432
+<a name="l00433"></a>00433 <span class="keywordtype">unsigned</span> MB, ME;
+<a name="l00434"></a>00434 <span class="keywordflow">if</span> (InsertMask && <a class="code" href="InstCombineAndOrXor_8cpp.html#add947a35dd442e049fda602d9dc9cd20">isRunOfOnes</a>(InsertMask, MB, ME)) {
+<a name="l00435"></a>00435 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp1, Tmp2;
+<a name="l00436"></a>00436
+<a name="l00437"></a>00437 <span class="keywordflow">if</span> ((Op1Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a> || Op1Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>) &&
+<a name="l00438"></a>00438 <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), Value)) {
+<a name="l00439"></a>00439 Op1 = Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00440"></a>00440 SH = (Op1Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a>) ? Value : 32 - Value;
+<a name="l00441"></a>00441 }
+<a name="l00442"></a>00442 <span class="keywordflow">if</span> (Op1Opc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>) {
+<a name="l00443"></a>00443 <span class="keywordtype">unsigned</span> SHOpc = Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>();
+<a name="l00444"></a>00444 <span class="keywordflow">if</span> ((SHOpc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a> || SHOpc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>) &&
+<a name="l00445"></a>00445 <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), Value)) {
+<a name="l00446"></a>00446 Op1 = Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00447"></a>00447 SH = (SHOpc == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a>) ? Value : 32 - Value;
+<a name="l00448"></a>00448 } <span class="keywordflow">else</span> {
+<a name="l00449"></a>00449 Op1 = Op1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00450"></a>00450 }
+<a name="l00451"></a>00451 }
+<a name="l00452"></a>00452
+<a name="l00453"></a>00453 SH &= 31;
+<a name="l00454"></a>00454 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
+<a name="l00455"></a>00455 getI32Imm(ME) };
+<a name="l00456"></a>00456 <span class="keywordflow">return</span> CurDAG->getMachineNode(PPC::RLWIMI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 5);
+<a name="l00457"></a>00457 }
+<a name="l00458"></a>00458 }
+<a name="l00459"></a>00459 <span class="keywordflow">return</span> 0;
+<a name="l00460"></a>00460 }
+<a name="l00461"></a>00461 <span class="comment"></span>
+<a name="l00462"></a>00462 <span class="comment">/// SelectCC - Select a comparison of the specified values with the specified</span>
+<a name="l00463"></a>00463 <span class="comment">/// condition code, returning the CR# of the expression.</span>
+<a name="l00464"></a>00464 <span class="comment"></span><a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PPCDAGToDAGISel::SelectCC(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHS,
+<a name="l00465"></a>00465 <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl) {
+<a name="l00466"></a>00466 <span class="comment">// Always select the LHS.</span>
+<a name="l00467"></a>00467 <span class="keywordtype">unsigned</span> Opc;
+<a name="l00468"></a>00468
+<a name="l00469"></a>00469 <span class="keywordflow">if</span> (LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>) {
+<a name="l00470"></a>00470 <span class="keywordtype">unsigned</span> Imm;
+<a name="l00471"></a>00471 <span class="keywordflow">if</span> (CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a> || CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>) {
+<a name="l00472"></a>00472 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(RHS, Imm)) {
+<a name="l00473"></a>00473 <span class="comment">// SETEQ/SETNE comparison with 16-bit immediate, fold it.</span>
+<a name="l00474"></a>00474 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#ad9b2b34494b2799c36a06ba60133bc11">isUInt<16></a>(Imm))
+<a name="l00475"></a>00475 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPLWI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, LHS,
+<a name="l00476"></a>00476 getI32Imm(Imm & 0xFFFF)), 0);
+<a name="l00477"></a>00477 <span class="comment">// If this is a 16-bit signed immediate, fold it.</span>
+<a name="l00478"></a>00478 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#a3b9662928ee4d58fef185abfe20e8184">isInt<16></a>((<span class="keywordtype">int</span>)Imm))
+<a name="l00479"></a>00479 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPWI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, LHS,
+<a name="l00480"></a>00480 getI32Imm(Imm & 0xFFFF)), 0);
+<a name="l00481"></a>00481
+<a name="l00482"></a>00482 <span class="comment">// For non-equality comparisons, the default code would materialize the</span>
+<a name="l00483"></a>00483 <span class="comment">// constant, then compare against it, like this:</span>
+<a name="l00484"></a>00484 <span class="comment">// lis r2, 4660</span>
+<a name="l00485"></a>00485 <span class="comment">// ori r2, r2, 22136</span>
+<a name="l00486"></a>00486 <span class="comment">// cmpw cr0, r3, r2</span>
+<a name="l00487"></a>00487 <span class="comment">// Since we are just comparing for equality, we can emit this instead:</span>
+<a name="l00488"></a>00488 <span class="comment">// xoris r0,r3,0x1234</span>
+<a name="l00489"></a>00489 <span class="comment">// cmplwi cr0,r0,0x5678</span>
+<a name="l00490"></a>00490 <span class="comment">// beq cr0,L6</span>
+<a name="l00491"></a>00491 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1APIntOps.html#afc7c4d88d09cba0c5e920f8a3a3ace55" title="Bitwise XOR function for APInt.">Xor</a>(CurDAG->getMachineNode(PPC::XORIS, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, LHS,
+<a name="l00492"></a>00492 getI32Imm(Imm >> 16)), 0);
+<a name="l00493"></a>00493 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPLWI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="namespacellvm_1_1APIntOps.html#afc7c4d88d09cba0c5e920f8a3a3ace55" title="Bitwise XOR function for APInt.">Xor</a>,
+<a name="l00494"></a>00494 getI32Imm(Imm & 0xFFFF)), 0);
+<a name="l00495"></a>00495 }
+<a name="l00496"></a>00496 Opc = PPC::CMPLW;
+<a name="l00497"></a>00497 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="namespacellvm_1_1ISD.html#adb237925346ec53b00d3c82a42311318">ISD::isUnsignedIntSetCC</a>(CC)) {
+<a name="l00498"></a>00498 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(RHS, Imm) && <a class="code" href="namespacellvm.html#ad9b2b34494b2799c36a06ba60133bc11">isUInt<16></a>(Imm))
+<a name="l00499"></a>00499 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPLWI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, LHS,
+<a name="l00500"></a>00500 getI32Imm(Imm & 0xFFFF)), 0);
+<a name="l00501"></a>00501 Opc = PPC::CMPLW;
+<a name="l00502"></a>00502 } <span class="keywordflow">else</span> {
+<a name="l00503"></a>00503 <span class="keywordtype">short</span> SImm;
+<a name="l00504"></a>00504 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(RHS, SImm))
+<a name="l00505"></a>00505 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPWI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, LHS,
+<a name="l00506"></a>00506 getI32Imm((<span class="keywordtype">int</span>)SImm & 0xFFFF)),
+<a name="l00507"></a>00507 0);
+<a name="l00508"></a>00508 Opc = PPC::CMPW;
+<a name="l00509"></a>00509 }
+<a name="l00510"></a>00510 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>) {
+<a name="l00511"></a>00511 uint64_t Imm;
+<a name="l00512"></a>00512 <span class="keywordflow">if</span> (CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a> || CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>) {
+<a name="l00513"></a>00513 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#a7312dc1e31cba7889c13ff9ada91ff15">isInt64Immediate</a>(RHS.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm)) {
+<a name="l00514"></a>00514 <span class="comment">// SETEQ/SETNE comparison with 16-bit immediate, fold it.</span>
+<a name="l00515"></a>00515 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#ad9b2b34494b2799c36a06ba60133bc11">isUInt<16></a>(Imm))
+<a name="l00516"></a>00516 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPLDI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, LHS,
+<a name="l00517"></a>00517 getI32Imm(Imm & 0xFFFF)), 0);
+<a name="l00518"></a>00518 <span class="comment">// If this is a 16-bit signed immediate, fold it.</span>
+<a name="l00519"></a>00519 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#a3b9662928ee4d58fef185abfe20e8184">isInt<16></a>(Imm))
+<a name="l00520"></a>00520 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPDI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, LHS,
+<a name="l00521"></a>00521 getI32Imm(Imm & 0xFFFF)), 0);
+<a name="l00522"></a>00522
+<a name="l00523"></a>00523 <span class="comment">// For non-equality comparisons, the default code would materialize the</span>
+<a name="l00524"></a>00524 <span class="comment">// constant, then compare against it, like this:</span>
+<a name="l00525"></a>00525 <span class="comment">// lis r2, 4660</span>
+<a name="l00526"></a>00526 <span class="comment">// ori r2, r2, 22136</span>
+<a name="l00527"></a>00527 <span class="comment">// cmpd cr0, r3, r2</span>
+<a name="l00528"></a>00528 <span class="comment">// Since we are just comparing for equality, we can emit this instead:</span>
+<a name="l00529"></a>00529 <span class="comment">// xoris r0,r3,0x1234</span>
+<a name="l00530"></a>00530 <span class="comment">// cmpldi cr0,r0,0x5678</span>
+<a name="l00531"></a>00531 <span class="comment">// beq cr0,L6</span>
+<a name="l00532"></a>00532 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#a623181432ee8a9105bb0b4116a75c4c4">isUInt<32></a>(Imm)) {
+<a name="l00533"></a>00533 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1APIntOps.html#afc7c4d88d09cba0c5e920f8a3a3ace55" title="Bitwise XOR function for APInt.">Xor</a>(CurDAG->getMachineNode(PPC::XORIS8, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, LHS,
+<a name="l00534"></a>00534 getI64Imm(Imm >> 16)), 0);
+<a name="l00535"></a>00535 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPLDI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, <a class="code" href="namespacellvm_1_1APIntOps.html#afc7c4d88d09cba0c5e920f8a3a3ace55" title="Bitwise XOR function for APInt.">Xor</a>,
+<a name="l00536"></a>00536 getI64Imm(Imm & 0xFFFF)), 0);
+<a name="l00537"></a>00537 }
+<a name="l00538"></a>00538 }
+<a name="l00539"></a>00539 Opc = PPC::CMPLD;
+<a name="l00540"></a>00540 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (<a class="code" href="namespacellvm_1_1ISD.html#adb237925346ec53b00d3c82a42311318">ISD::isUnsignedIntSetCC</a>(CC)) {
+<a name="l00541"></a>00541 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#a7312dc1e31cba7889c13ff9ada91ff15">isInt64Immediate</a>(RHS.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm) && <a class="code" href="namespacellvm.html#ad9b2b34494b2799c36a06ba60133bc11">isUInt<16></a>(Imm))
+<a name="l00542"></a>00542 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPLDI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, LHS,
+<a name="l00543"></a>00543 getI64Imm(Imm & 0xFFFF)), 0);
+<a name="l00544"></a>00544 Opc = PPC::CMPLD;
+<a name="l00545"></a>00545 } <span class="keywordflow">else</span> {
+<a name="l00546"></a>00546 <span class="keywordtype">short</span> SImm;
+<a name="l00547"></a>00547 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#aab0e46096b7ef57095fb1746f0c6e4af">isIntS16Immediate</a>(RHS, SImm))
+<a name="l00548"></a>00548 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CMPDI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, LHS,
+<a name="l00549"></a>00549 getI64Imm(SImm & 0xFFFF)),
+<a name="l00550"></a>00550 0);
+<a name="l00551"></a>00551 Opc = PPC::CMPD;
+<a name="l00552"></a>00552 }
+<a name="l00553"></a>00553 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>) {
+<a name="l00554"></a>00554 Opc = PPC::FCMPUS;
+<a name="l00555"></a>00555 } <span class="keywordflow">else</span> {
+<a name="l00556"></a>00556 assert(LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a> && <span class="stringliteral">"Unknown vt!"</span>);
+<a name="l00557"></a>00557 Opc = PPC::FCMPUD;
+<a name="l00558"></a>00558 }
+<a name="l00559"></a>00559 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(Opc, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, LHS, RHS), 0);
+<a name="l00560"></a>00560 }
+<a name="l00561"></a>00561
+<a name="l00562"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#ac60b36afeca1158879e59a32e1a53ecd">00562</a> <span class="keyword">static</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355" title="Predicate - These are "(BI << 5) | BO" for various predicates.">PPC::Predicate</a> <a class="code" href="PPCISelDAGToDAG_8cpp.html#ac60b36afeca1158879e59a32e1a53ecd">getPredicateForSetCC</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> CC) {
+<a name="l00563"></a>00563 <span class="keywordflow">switch</span> (CC) {
+<a name="l00564"></a>00564 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0deb50cd2f3f8e4a94eef4cdf769b848">ISD::SETUEQ</a>:
+<a name="l00565"></a>00565 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a57c68bf7ef20bd558854a24d5b0c1e72">ISD::SETONE</a>:
+<a name="l00566"></a>00566 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a1febf3bac2f3d7d98ec19f1ff5c385ea">ISD::SETOLE</a>:
+<a name="l00567"></a>00567 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac7bb30d4918c1ee9dd208083154e109f">ISD::SETOGE</a>:
+<a name="l00568"></a>00568 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Should be lowered by legalize!"</span>);
+<a name="l00569"></a>00569 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unknown condition!"</span>);
+<a name="l00570"></a>00570 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a08c31033acfb9d6f0bc4a8a82cc26862">ISD::SETOEQ</a>:
+<a name="l00571"></a>00571 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355a34be5288a1bb24e5120358395f7f0dc3">PPC::PRED_EQ</a>;
+<a name="l00572"></a>00572 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0d1546187d4d526fcbdd43183689075e">ISD::SETUNE</a>:
+<a name="l00573"></a>00573 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355ad9add708b3d9680d64242cf06f448462">PPC::PRED_NE</a>;
+<a name="l00574"></a>00574 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a20257a4d3833cf88afd42caeaed70dde">ISD::SETOLT</a>:
+<a name="l00575"></a>00575 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355a46cd6e935d7b9cc679d9cb0cf025ae91">PPC::PRED_LT</a>;
+<a name="l00576"></a>00576 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac538f0b432df970cbaaf6b81d777c6a7">ISD::SETULE</a>:
+<a name="l00577"></a>00577 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ab49f81c2ecbbff3d0fbe55dd46353774">ISD::SETLE</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355ac89b6a30c033abb18a7e81f48b0e3593">PPC::PRED_LE</a>;
+<a name="l00578"></a>00578 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a31d1e24e08b255d6aa290d67d16ce2c9">ISD::SETOGT</a>:
+<a name="l00579"></a>00579 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a5ad12b466e3a5900d0c307b301465d25">ISD::SETGT</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355a8cd4d49277068c1eab8d4d7c4835b817">PPC::PRED_GT</a>;
+<a name="l00580"></a>00580 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a9dff1dcbac65852b71473818c11869b1">ISD::SETUGE</a>:
+<a name="l00581"></a>00581 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a7f47862de23f7210f88ccf98ae1efbe4">ISD::SETGE</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355a44abec85091b571da2189ac4bd139095">PPC::PRED_GE</a>;
+<a name="l00582"></a>00582 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a71f916390487bb109d9968c72553eaf4">ISD::SETO</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355a94061699653bc6df4c3809c7a4d44ac9">PPC::PRED_NU</a>;
+<a name="l00583"></a>00583 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a48a334bbe606d5e82c9cd84eaa127b50">ISD::SETUO</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355a89f893823745c8d91bb4d7d83e247cb6">PPC::PRED_UN</a>;
+<a name="l00584"></a>00584 <span class="comment">// These two are invalid for floating point. Assume we have int.</span>
+<a name="l00585"></a>00585 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355a46cd6e935d7b9cc679d9cb0cf025ae91">PPC::PRED_LT</a>;
+<a name="l00586"></a>00586 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>: <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1PPC.html#a14028f7fe73a11dabc6583510cc0a355a8cd4d49277068c1eab8d4d7c4835b817">PPC::PRED_GT</a>;
+<a name="l00587"></a>00587 }
+<a name="l00588"></a>00588 }
+<a name="l00589"></a>00589 <span class="comment"></span>
+<a name="l00590"></a>00590 <span class="comment">/// getCRIdxForSetCC - Return the index of the condition register field</span>
+<a name="l00591"></a>00591 <span class="comment">/// associated with the SetCC condition, and whether or not the field is</span>
+<a name="l00592"></a>00592 <span class="comment">/// treated as inverted. That is, lt = 0; ge = 0 inverted.</span>
+<a name="l00593"></a>00593 <span class="comment">///</span>
+<a name="l00594"></a>00594 <span class="comment">/// If this returns with Other != -1, then the returned comparison is an or of</span>
+<a name="l00595"></a>00595 <span class="comment">/// two simpler comparisons. In this case, Invert is guaranteed to be false.</span>
+<a name="l00596"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#aca6f8c9cd47f0e693ce01a97fb5fe7ce">00596</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">unsigned</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#aca6f8c9cd47f0e693ce01a97fb5fe7ce">getCRIdxForSetCC</a>(<a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> CC, <span class="keywordtype">bool</span> &Invert, <span class="keywordtype">int</span> &Other) {
+<a name="l00597"></a>00597 Invert = <span class="keyword">false</span>;
+<a name="l00598"></a>00598 Other = -1;
+<a name="l00599"></a>00599 <span class="keywordflow">switch</span> (CC) {
+<a name="l00600"></a>00600 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unknown condition!"</span>);
+<a name="l00601"></a>00601 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a20257a4d3833cf88afd42caeaed70dde">ISD::SETOLT</a>:
+<a name="l00602"></a>00602 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>: <span class="keywordflow">return</span> 0; <span class="comment">// Bit #0 = SETOLT</span>
+<a name="l00603"></a>00603 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a31d1e24e08b255d6aa290d67d16ce2c9">ISD::SETOGT</a>:
+<a name="l00604"></a>00604 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a5ad12b466e3a5900d0c307b301465d25">ISD::SETGT</a>: <span class="keywordflow">return</span> 1; <span class="comment">// Bit #1 = SETOGT</span>
+<a name="l00605"></a>00605 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a08c31033acfb9d6f0bc4a8a82cc26862">ISD::SETOEQ</a>:
+<a name="l00606"></a>00606 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a>: <span class="keywordflow">return</span> 2; <span class="comment">// Bit #2 = SETOEQ</span>
+<a name="l00607"></a>00607 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a48a334bbe606d5e82c9cd84eaa127b50">ISD::SETUO</a>: <span class="keywordflow">return</span> 3; <span class="comment">// Bit #3 = SETUO</span>
+<a name="l00608"></a>00608 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a9dff1dcbac65852b71473818c11869b1">ISD::SETUGE</a>:
+<a name="l00609"></a>00609 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a7f47862de23f7210f88ccf98ae1efbe4">ISD::SETGE</a>: Invert = <span class="keyword">true</span>; <span class="keywordflow">return</span> 0; <span class="comment">// !Bit #0 = SETUGE</span>
+<a name="l00610"></a>00610 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac538f0b432df970cbaaf6b81d777c6a7">ISD::SETULE</a>:
+<a name="l00611"></a>00611 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ab49f81c2ecbbff3d0fbe55dd46353774">ISD::SETLE</a>: Invert = <span class="keyword">true</span>; <span class="keywordflow">return</span> 1; <span class="comment">// !Bit #1 = SETULE</span>
+<a name="l00612"></a>00612 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0d1546187d4d526fcbdd43183689075e">ISD::SETUNE</a>:
+<a name="l00613"></a>00613 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>: Invert = <span class="keyword">true</span>; <span class="keywordflow">return</span> 2; <span class="comment">// !Bit #2 = SETUNE</span>
+<a name="l00614"></a>00614 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a71f916390487bb109d9968c72553eaf4">ISD::SETO</a>: Invert = <span class="keyword">true</span>; <span class="keywordflow">return</span> 3; <span class="comment">// !Bit #3 = SETO</span>
+<a name="l00615"></a>00615 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0deb50cd2f3f8e4a94eef4cdf769b848">ISD::SETUEQ</a>:
+<a name="l00616"></a>00616 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac7bb30d4918c1ee9dd208083154e109f">ISD::SETOGE</a>:
+<a name="l00617"></a>00617 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a1febf3bac2f3d7d98ec19f1ff5c385ea">ISD::SETOLE</a>:
+<a name="l00618"></a>00618 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a57c68bf7ef20bd558854a24d5b0c1e72">ISD::SETONE</a>:
+<a name="l00619"></a>00619 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Invalid branch code: should be expanded by legalize"</span>);
+<a name="l00620"></a>00620 <span class="comment">// These are invalid for floating point. Assume integer.</span>
+<a name="l00621"></a>00621 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>: <span class="keywordflow">return</span> 0;
+<a name="l00622"></a>00622 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>: <span class="keywordflow">return</span> 1;
+<a name="l00623"></a>00623 }
+<a name="l00624"></a>00624 }
+<a name="l00625"></a>00625
+<a name="l00626"></a>00626 <span class="comment">// getVCmpInst: return the vector compare instruction for the specified</span>
+<a name="l00627"></a>00627 <span class="comment">// vector type and condition code. Since this is for altivec specific code,</span>
+<a name="l00628"></a>00628 <span class="comment">// only support the altivec types (v16i8, v8i16, v4i32, and v4f32).</span>
+<a name="l00629"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#a825b6fe181b46ad47ca0960aaff725c9">00629</a> <span class="keyword">static</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#a825b6fe181b46ad47ca0960aaff725c9">getVCmpInst</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a> VecVT, <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> CC) {
+<a name="l00630"></a>00630 <span class="keywordflow">switch</span> (CC) {
+<a name="l00631"></a>00631 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a>:
+<a name="l00632"></a>00632 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0deb50cd2f3f8e4a94eef4cdf769b848">ISD::SETUEQ</a>:
+<a name="l00633"></a>00633 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>:
+<a name="l00634"></a>00634 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0d1546187d4d526fcbdd43183689075e">ISD::SETUNE</a>:
+<a name="l00635"></a>00635 <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>)
+<a name="l00636"></a>00636 <span class="keywordflow">return</span> PPC::VCMPEQUB;
+<a name="l00637"></a>00637 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>)
+<a name="l00638"></a>00638 <span class="keywordflow">return</span> PPC::VCMPEQUH;
+<a name="l00639"></a>00639 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>)
+<a name="l00640"></a>00640 <span class="keywordflow">return</span> PPC::VCMPEQUW;
+<a name="l00641"></a>00641 <span class="comment">// v4f32 != v4f32 could be translate to unordered not equal</span>
+<a name="l00642"></a>00642 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>)
+<a name="l00643"></a>00643 <span class="keywordflow">return</span> PPC::VCMPEQFP;
+<a name="l00644"></a>00644 <span class="keywordflow">break</span>;
+<a name="l00645"></a>00645 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>:
+<a name="l00646"></a>00646 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a5ad12b466e3a5900d0c307b301465d25">ISD::SETGT</a>:
+<a name="l00647"></a>00647 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ab49f81c2ecbbff3d0fbe55dd46353774">ISD::SETLE</a>:
+<a name="l00648"></a>00648 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a7f47862de23f7210f88ccf98ae1efbe4">ISD::SETGE</a>:
+<a name="l00649"></a>00649 <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>)
+<a name="l00650"></a>00650 <span class="keywordflow">return</span> PPC::VCMPGTSB;
+<a name="l00651"></a>00651 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>)
+<a name="l00652"></a>00652 <span class="keywordflow">return</span> PPC::VCMPGTSH;
+<a name="l00653"></a>00653 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>)
+<a name="l00654"></a>00654 <span class="keywordflow">return</span> PPC::VCMPGTSW;
+<a name="l00655"></a>00655 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>)
+<a name="l00656"></a>00656 <span class="keywordflow">return</span> PPC::VCMPGTFP;
+<a name="l00657"></a>00657 <span class="keywordflow">break</span>;
+<a name="l00658"></a>00658 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>:
+<a name="l00659"></a>00659 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>:
+<a name="l00660"></a>00660 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a9dff1dcbac65852b71473818c11869b1">ISD::SETUGE</a>:
+<a name="l00661"></a>00661 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac538f0b432df970cbaaf6b81d777c6a7">ISD::SETULE</a>:
+<a name="l00662"></a>00662 <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>)
+<a name="l00663"></a>00663 <span class="keywordflow">return</span> PPC::VCMPGTUB;
+<a name="l00664"></a>00664 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>)
+<a name="l00665"></a>00665 <span class="keywordflow">return</span> PPC::VCMPGTUH;
+<a name="l00666"></a>00666 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>)
+<a name="l00667"></a>00667 <span class="keywordflow">return</span> PPC::VCMPGTUW;
+<a name="l00668"></a>00668 <span class="keywordflow">break</span>;
+<a name="l00669"></a>00669 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a08c31033acfb9d6f0bc4a8a82cc26862">ISD::SETOEQ</a>:
+<a name="l00670"></a>00670 <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>)
+<a name="l00671"></a>00671 <span class="keywordflow">return</span> PPC::VCMPEQFP;
+<a name="l00672"></a>00672 <span class="keywordflow">break</span>;
+<a name="l00673"></a>00673 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a20257a4d3833cf88afd42caeaed70dde">ISD::SETOLT</a>:
+<a name="l00674"></a>00674 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a31d1e24e08b255d6aa290d67d16ce2c9">ISD::SETOGT</a>:
+<a name="l00675"></a>00675 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a1febf3bac2f3d7d98ec19f1ff5c385ea">ISD::SETOLE</a>:
+<a name="l00676"></a>00676 <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>)
+<a name="l00677"></a>00677 <span class="keywordflow">return</span> PPC::VCMPGTFP;
+<a name="l00678"></a>00678 <span class="keywordflow">break</span>;
+<a name="l00679"></a>00679 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac7bb30d4918c1ee9dd208083154e109f">ISD::SETOGE</a>:
+<a name="l00680"></a>00680 <span class="keywordflow">if</span> (VecVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>)
+<a name="l00681"></a>00681 <span class="keywordflow">return</span> PPC::VCMPGEFP;
+<a name="l00682"></a>00682 <span class="keywordflow">break</span>;
+<a name="l00683"></a>00683 <span class="keywordflow">default</span>:
+<a name="l00684"></a>00684 <span class="keywordflow">break</span>;
+<a name="l00685"></a>00685 }
+<a name="l00686"></a>00686 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Invalid integer vector compare condition"</span>);
+<a name="l00687"></a>00687 }
+<a name="l00688"></a>00688
+<a name="l00689"></a>00689 <span class="comment">// getVCmpEQInst: return the equal compare instruction for the specified vector</span>
+<a name="l00690"></a>00690 <span class="comment">// type. Since this is for altivec specific code, only support the altivec</span>
+<a name="l00691"></a>00691 <span class="comment">// types (v16i8, v8i16, v4i32, and v4f32).</span>
+<a name="l00692"></a><a class="code" href="PPCISelDAGToDAG_8cpp.html#a9571c787079adbc0085f03deb0828d1d">00692</a> <span class="keyword">static</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> <a class="code" href="PPCISelDAGToDAG_8cpp.html#a9571c787079adbc0085f03deb0828d1d">getVCmpEQInst</a>(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a> VecVT) {
+<a name="l00693"></a>00693 <span class="keywordflow">switch</span> (VecVT) {
+<a name="l00694"></a>00694 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>:
+<a name="l00695"></a>00695 <span class="keywordflow">return</span> PPC::VCMPEQUB;
+<a name="l00696"></a>00696 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>:
+<a name="l00697"></a>00697 <span class="keywordflow">return</span> PPC::VCMPEQUH;
+<a name="l00698"></a>00698 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>:
+<a name="l00699"></a>00699 <span class="keywordflow">return</span> PPC::VCMPEQUW;
+<a name="l00700"></a>00700 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l00701"></a>00701 <span class="keywordflow">return</span> PPC::VCMPEQFP;
+<a name="l00702"></a>00702 <span class="keywordflow">default</span>:
+<a name="l00703"></a>00703 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Invalid integer vector compare condition"</span>);
+<a name="l00704"></a>00704 }
+<a name="l00705"></a>00705 }
+<a name="l00706"></a>00706
+<a name="l00707"></a>00707
+<a name="l00708"></a>00708 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *PPCDAGToDAGISel::SelectSETCC(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l00709"></a>00709 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l00710"></a>00710 <span class="keywordtype">unsigned</span> Imm;
+<a name="l00711"></a>00711 <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> CC = cast<CondCodeSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2))-><span class="keyword">get</span>();
+<a name="l00712"></a>00712 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
+<a name="l00713"></a>00713 <span class="keywordtype">bool</span> isPPC64 = (PtrVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l00714"></a>00714
+<a name="l00715"></a>00715 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Imm)) {
+<a name="l00716"></a>00716 <span class="comment">// We can codegen setcc op, imm very efficiently compared to a brcond.</span>
+<a name="l00717"></a>00717 <span class="comment">// Check for those cases here.</span>
+<a name="l00718"></a>00718 <span class="comment">// setcc op, 0</span>
+<a name="l00719"></a>00719 <span class="keywordflow">if</span> (Imm == 0) {
+<a name="l00720"></a>00720 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l00721"></a>00721 <span class="keywordflow">switch</span> (CC) {
+<a name="l00722"></a>00722 <span class="keywordflow">default</span>: <span class="keywordflow">break</span>;
+<a name="l00723"></a>00723 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a>: {
+<a name="l00724"></a>00724 Op = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::CNTLZW, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Op), 0);
+<a name="l00725"></a>00725 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
+<a name="l00726"></a>00726 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l00727"></a>00727 }
+<a name="l00728"></a>00728 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>: {
+<a name="l00729"></a>00729 <span class="keywordflow">if</span> (isPPC64) <span class="keywordflow">break</span>;
+<a name="l00730"></a>00730 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AD =
+<a name="l00731"></a>00731 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::ADDIC, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>,
+<a name="l00732"></a>00732 Op, getI32Imm(~0U)), 0);
+<a name="l00733"></a>00733 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::SUBFE, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, AD, Op,
+<a name="l00734"></a>00734 AD.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l00735"></a>00735 }
+<a name="l00736"></a>00736 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>: {
+<a name="l00737"></a>00737 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+<a name="l00738"></a>00738 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l00739"></a>00739 }
+<a name="l00740"></a>00740 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a5ad12b466e3a5900d0c307b301465d25">ISD::SETGT</a>: {
+<a name="l00741"></a>00741 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> T =
+<a name="l00742"></a>00742 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::NEG, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Op), 0);
+<a name="l00743"></a>00743 T = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::ANDC, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, T, Op), 0);
+<a name="l00744"></a>00744 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+<a name="l00745"></a>00745 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l00746"></a>00746 }
+<a name="l00747"></a>00747 }
+<a name="l00748"></a>00748 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Imm == ~0U) { <span class="comment">// setcc op, -1</span>
+<a name="l00749"></a>00749 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Op = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l00750"></a>00750 <span class="keywordflow">switch</span> (CC) {
+<a name="l00751"></a>00751 <span class="keywordflow">default</span>: <span class="keywordflow">break</span>;
+<a name="l00752"></a>00752 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a>:
+<a name="l00753"></a>00753 <span class="keywordflow">if</span> (isPPC64) <span class="keywordflow">break</span>;
+<a name="l00754"></a>00754 Op = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::ADDIC, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>,
+<a name="l00755"></a>00755 Op, getI32Imm(1)), 0);
+<a name="l00756"></a>00756 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::ADDZE, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l00757"></a>00757 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(<a class="code" href="LoopInfoImpl_8h.html#ab7b7f3fe4279386eae18cf924053d077">PPC::LI</a>, dl,
+<a name="l00758"></a>00758 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l00759"></a>00759 getI32Imm(0)), 0),
+<a name="l00760"></a>00760 Op.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l00761"></a>00761 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>: {
+<a name="l00762"></a>00762 <span class="keywordflow">if</span> (isPPC64) <span class="keywordflow">break</span>;
+<a name="l00763"></a>00763 Op = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::NOR, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Op, Op), 0);
+<a name="l00764"></a>00764 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>,
+<a name="l00765"></a>00765 Op, getI32Imm(~0U));
+<a name="l00766"></a>00766 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::SUBFE, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(AD, 0),
+<a name="l00767"></a>00767 Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(AD, 1));
+<a name="l00768"></a>00768 }
+<a name="l00769"></a>00769 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>: {
+<a name="l00770"></a>00770 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AD = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::ADDI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Op,
+<a name="l00771"></a>00771 getI32Imm(1)), 0);
+<a name="l00772"></a>00772 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> AN = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(<a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a865555c9f2e0458a7078486aa1b3254f">PPC::AND</a>, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, AD,
+<a name="l00773"></a>00773 Op), 0);
+<a name="l00774"></a>00774 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+<a name="l00775"></a>00775 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l00776"></a>00776 }
+<a name="l00777"></a>00777 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a5ad12b466e3a5900d0c307b301465d25">ISD::SETGT</a>: {
+<a name="l00778"></a>00778 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
+<a name="l00779"></a>00779 Op = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::RLWINM, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4),
+<a name="l00780"></a>00780 0);
+<a name="l00781"></a>00781 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::XORI, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Op,
+<a name="l00782"></a>00782 getI32Imm(1));
+<a name="l00783"></a>00783 }
+<a name="l00784"></a>00784 }
+<a name="l00785"></a>00785 }
+<a name="l00786"></a>00786 }
+<a name="l00787"></a>00787
+<a name="l00788"></a>00788 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> LHS = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l00789"></a>00789 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RHS = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l00790"></a>00790
+<a name="l00791"></a>00791 <span class="comment">// Altivec Vector compare instructions do not set any CR register by default and</span>
+<a name="l00792"></a>00792 <span class="comment">// vector compare operations return the same type as the operands.</span>
+<a name="l00793"></a>00793 <span class="keywordflow">if</span> (LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>().<a class="code" href="structllvm_1_1EVT.html#a73f7c824cad61a47c21bf6d652ae2fd7" title="isVector - Return true if this is a vector value type.">isVector</a>()) {
+<a name="l00794"></a>00794 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VecVT = LHS.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l00795"></a>00795 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50c">MVT::SimpleValueType</a> VT = VecVT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>;
+<a name="l00796"></a>00796 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> VCmpInst = <a class="code" href="PPCISelDAGToDAG_8cpp.html#a825b6fe181b46ad47ca0960aaff725c9">getVCmpInst</a>(VT, CC);
+<a name="l00797"></a>00797
+<a name="l00798"></a>00798 <span class="keywordflow">switch</span> (CC) {
+<a name="l00799"></a>00799 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ae2e6a5e32087b9f65bd51585a6a5afb4">ISD::SETEQ</a>:
+<a name="l00800"></a>00800 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a08c31033acfb9d6f0bc4a8a82cc26862">ISD::SETOEQ</a>:
+<a name="l00801"></a>00801 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0deb50cd2f3f8e4a94eef4cdf769b848">ISD::SETUEQ</a>:
+<a name="l00802"></a>00802 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
+<a name="l00803"></a>00803 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a>:
+<a name="l00804"></a>00804 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a57c68bf7ef20bd558854a24d5b0c1e72">ISD::SETONE</a>:
+<a name="l00805"></a>00805 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a0d1546187d4d526fcbdd43183689075e">ISD::SETUNE</a>: {
+<a name="l00806"></a>00806 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
+<a name="l00807"></a>00807 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::VNOR, VecVT, VCmp, VCmp);
+<a name="l00808"></a>00808 }
+<a name="l00809"></a>00809 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a6f05a09edb671910f85f8665981cbde9">ISD::SETLT</a>:
+<a name="l00810"></a>00810 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a20257a4d3833cf88afd42caeaed70dde">ISD::SETOLT</a>:
+<a name="l00811"></a>00811 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a473200f06bdd611fdbed43d908b84305">ISD::SETULT</a>:
+<a name="l00812"></a>00812 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, VCmpInst, VecVT, RHS, LHS);
+<a name="l00813"></a>00813 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a5ad12b466e3a5900d0c307b301465d25">ISD::SETGT</a>:
+<a name="l00814"></a>00814 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a31d1e24e08b255d6aa290d67d16ce2c9">ISD::SETOGT</a>:
+<a name="l00815"></a>00815 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a292be4a9782030bfad637581d25a5897">ISD::SETUGT</a>:
+<a name="l00816"></a>00816 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
+<a name="l00817"></a>00817 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a7f47862de23f7210f88ccf98ae1efbe4">ISD::SETGE</a>:
+<a name="l00818"></a>00818 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac7bb30d4918c1ee9dd208083154e109f">ISD::SETOGE</a>:
+<a name="l00819"></a>00819 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a9dff1dcbac65852b71473818c11869b1">ISD::SETUGE</a>: {
+<a name="l00820"></a>00820 <span class="comment">// Small optimization: Altivec provides a 'Vector Compare Greater Than</span>
+<a name="l00821"></a>00821 <span class="comment">// or Equal To' instruction (vcmpgefp), so in this case there is no</span>
+<a name="l00822"></a>00822 <span class="comment">// need for extra logic for the equal compare.</span>
+<a name="l00823"></a>00823 <span class="keywordflow">if</span> (VecVT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#ab1311d6d51755d404adc348ad4aeaaad" title="isFloatingPoint - Return true if this is a FP, or a vector FP type.">isFloatingPoint</a>()) {
+<a name="l00824"></a>00824 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
+<a name="l00825"></a>00825 } <span class="keywordflow">else</span> {
+<a name="l00826"></a>00826 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> VCmpGT(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
+<a name="l00827"></a>00827 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> VCmpEQInst = <a class="code" href="PPCISelDAGToDAG_8cpp.html#a9571c787079adbc0085f03deb0828d1d">getVCmpEQInst</a>(VT);
+<a name="l00828"></a>00828 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
+<a name="l00829"></a>00829 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpGT, VCmpEQ);
+<a name="l00830"></a>00830 }
+<a name="l00831"></a>00831 }
+<a name="l00832"></a>00832 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ab49f81c2ecbbff3d0fbe55dd46353774">ISD::SETLE</a>:
+<a name="l00833"></a>00833 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a1febf3bac2f3d7d98ec19f1ff5c385ea">ISD::SETOLE</a>:
+<a name="l00834"></a>00834 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07ac538f0b432df970cbaaf6b81d777c6a7">ISD::SETULE</a>: {
+<a name="l00835"></a>00835 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> VCmpLE(CurDAG->getMachineNode(VCmpInst, dl, VecVT, RHS, LHS), 0);
+<a name="l00836"></a>00836 <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> VCmpEQInst = <a class="code" href="PPCISelDAGToDAG_8cpp.html#a9571c787079adbc0085f03deb0828d1d">getVCmpEQInst</a>(VT);
+<a name="l00837"></a>00837 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> VCmpEQ(CurDAG->getMachineNode(VCmpEQInst, dl, VecVT, LHS, RHS), 0);
+<a name="l00838"></a>00838 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::VOR, VecVT, VCmpLE, VCmpEQ);
+<a name="l00839"></a>00839 }
+<a name="l00840"></a>00840 <span class="keywordflow">default</span>:
+<a name="l00841"></a>00841 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Invalid vector compare type: should be expanded by legalize"</span>);
+<a name="l00842"></a>00842 }
+<a name="l00843"></a>00843 }
+<a name="l00844"></a>00844
+<a name="l00845"></a>00845 <span class="keywordtype">bool</span> Inv;
+<a name="l00846"></a>00846 <span class="keywordtype">int</span> OtherCondIdx;
+<a name="l00847"></a>00847 <span class="keywordtype">unsigned</span> Idx = <a class="code" href="PPCISelDAGToDAG_8cpp.html#aca6f8c9cd47f0e693ce01a97fb5fe7ce">getCRIdxForSetCC</a>(CC, Inv, OtherCondIdx);
+<a name="l00848"></a>00848 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCReg = SelectCC(LHS, RHS, CC, dl);
+<a name="l00849"></a>00849 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> IntCR;
+<a name="l00850"></a>00850
+<a name="l00851"></a>00851 <span class="comment">// Force the ccreg into CR7.</span>
+<a name="l00852"></a>00852 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CR7Reg = CurDAG->getRegister(PPC::CR7, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00853"></a>00853
+<a name="l00854"></a>00854 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag(0, 0); <span class="comment">// Null incoming flag value.</span>
+<a name="l00855"></a>00855 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
+<a name="l00856"></a>00856 InFlag).getValue(1);
+<a name="l00857"></a>00857
+<a name="l00858"></a>00858 <span class="keywordflow">if</span> (PPCSubTarget.hasMFOCRF() && OtherCondIdx == -1)
+<a name="l00859"></a>00859 IntCR = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::MFOCRF, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, CR7Reg,
+<a name="l00860"></a>00860 CCReg), 0);
+<a name="l00861"></a>00861 <span class="keywordflow">else</span>
+<a name="l00862"></a>00862 IntCR = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::MFCRpseud, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l00863"></a>00863 CR7Reg, CCReg), 0);
+<a name="l00864"></a>00864
+<a name="l00865"></a>00865 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
+<a name="l00866"></a>00866 getI32Imm(31), getI32Imm(31) };
+<a name="l00867"></a>00867 <span class="keywordflow">if</span> (OtherCondIdx == -1 && !Inv)
+<a name="l00868"></a>00868 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l00869"></a>00869
+<a name="l00870"></a>00870 <span class="comment">// Get the specified bit.</span>
+<a name="l00871"></a>00871 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp =
+<a name="l00872"></a>00872 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::RLWINM, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4), 0);
+<a name="l00873"></a>00873 <span class="keywordflow">if</span> (Inv) {
+<a name="l00874"></a>00874 assert(OtherCondIdx == -1 && <span class="stringliteral">"Can't have split plus negation"</span>);
+<a name="l00875"></a>00875 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::XORI, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Tmp, getI32Imm(1));
+<a name="l00876"></a>00876 }
+<a name="l00877"></a>00877
+<a name="l00878"></a>00878 <span class="comment">// Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.</span>
+<a name="l00879"></a>00879 <span class="comment">// We already got the bit for the first part of the comparison (e.g. SETULE).</span>
+<a name="l00880"></a>00880
+<a name="l00881"></a>00881 <span class="comment">// Get the other bit of the comparison.</span>
+<a name="l00882"></a>00882 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
+<a name="l00883"></a>00883 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OtherCond =
+<a name="l00884"></a>00884 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::RLWINM, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4), 0);
+<a name="l00885"></a>00885
+<a name="l00886"></a>00886 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, <a class="code" href="X86ISelDAGToDAG_8cpp.html#afc4e10b4f2ab2d548ab80b30f3b712e9a96727447c0ad447987df1c6415aef074">PPC::OR</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Tmp, OtherCond);
+<a name="l00887"></a>00887 }
+<a name="l00888"></a>00888
+<a name="l00889"></a>00889
+<a name="l00890"></a>00890 <span class="comment">// Select - Convert the specified operand from a target-independent to a</span>
+<a name="l00891"></a>00891 <span class="comment">// target-specific node if it hasn't already been changed.</span>
+<a name="l00892"></a>00892 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="namespacellvm.html#af3ab12efdd6b4902d711e72b7a81f13b">PPCDAGToDAGISel::Select</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l00893"></a>00893 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l00894"></a>00894 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#a7ef138746b04be6d07091b9ba49d74da">isMachineOpcode</a>())
+<a name="l00895"></a>00895 <span class="keywordflow">return</span> NULL; <span class="comment">// Already selected.</span>
+<a name="l00896"></a>00896
+<a name="l00897"></a>00897 <span class="keywordflow">switch</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>()) {
+<a name="l00898"></a>00898 <span class="keywordflow">default</span>: <span class="keywordflow">break</span>;
+<a name="l00899"></a>00899
+<a name="l00900"></a>00900 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a>: {
+<a name="l00901"></a>00901 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>) {
+<a name="l00902"></a>00902 <span class="comment">// Get 64 bit value.</span>
+<a name="l00903"></a>00903 <a class="code" href="classint64__t.html">int64_t</a> Imm = cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00904"></a>00904 <span class="comment">// Assume no remaining bits.</span>
+<a name="l00905"></a>00905 <span class="keywordtype">unsigned</span> Remainder = 0;
+<a name="l00906"></a>00906 <span class="comment">// Assume no shift required.</span>
+<a name="l00907"></a>00907 <span class="keywordtype">unsigned</span> Shift = 0;
+<a name="l00908"></a>00908
+<a name="l00909"></a>00909 <span class="comment">// If it can't be represented as a 32 bit value.</span>
+<a name="l00910"></a>00910 <span class="keywordflow">if</span> (!<a class="code" href="namespacellvm.html#a9bf6430c1a0cf078ee3f9f520fa407f0">isInt<32></a>(Imm)) {
+<a name="l00911"></a>00911 Shift = <a class="code" href="namespacellvm.html#aeba092d2456a8e867b2d0fe430f4629e">CountTrailingZeros_64</a>(Imm);
+<a name="l00912"></a>00912 <a class="code" href="classint64__t.html">int64_t</a> ImmSh = <span class="keyword">static_cast<</span>uint64_t<span class="keyword">></span>(Imm) >> Shift;
+<a name="l00913"></a>00913
+<a name="l00914"></a>00914 <span class="comment">// If the shifted value fits 32 bits.</span>
+<a name="l00915"></a>00915 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#a9bf6430c1a0cf078ee3f9f520fa407f0">isInt<32></a>(ImmSh)) {
+<a name="l00916"></a>00916 <span class="comment">// Go with the shifted value.</span>
+<a name="l00917"></a>00917 Imm = ImmSh;
+<a name="l00918"></a>00918 } <span class="keywordflow">else</span> {
+<a name="l00919"></a>00919 <span class="comment">// Still stuck with a 64 bit value.</span>
+<a name="l00920"></a>00920 Remainder = Imm;
+<a name="l00921"></a>00921 Shift = 32;
+<a name="l00922"></a>00922 Imm >>= 32;
+<a name="l00923"></a>00923 }
+<a name="l00924"></a>00924 }
+<a name="l00925"></a>00925
+<a name="l00926"></a>00926 <span class="comment">// Intermediate operand.</span>
+<a name="l00927"></a>00927 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Result;
+<a name="l00928"></a>00928
+<a name="l00929"></a>00929 <span class="comment">// Handle first 32 bits.</span>
+<a name="l00930"></a>00930 <span class="keywordtype">unsigned</span> <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ab68a439987d870da623ed899fa47344c" title="Low address component (lower 16)">Lo</a> = Imm & 0xFFFF;
+<a name="l00931"></a>00931 <span class="keywordtype">unsigned</span> <a class="code" href="namespacellvm_1_1SPUISD.html#a317972e7ba7aa6aac9068bbf50de2f89ae3a56d8e7b43b7a68cbb0e7655a062cd" title="High address component (upper 16)">Hi</a> = (Imm >> 16) & 0xFFFF;
+<a name="l00932"></a>00932
+<a name="l00933"></a>00933 <span class="comment">// Simple value.</span>
+<a name="l00934"></a>00934 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#a3b9662928ee4d58fef185abfe20e8184">isInt<16></a>(Imm)) {
+<a name="l00935"></a>00935 <span class="comment">// Just the Lo bits.</span>
+<a name="l00936"></a>00936 Result = CurDAG->getMachineNode(PPC::LI8, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, getI32Imm(Lo));
+<a name="l00937"></a>00937 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Lo) {
+<a name="l00938"></a>00938 <span class="comment">// Handle the Hi bits.</span>
+<a name="l00939"></a>00939 <span class="keywordtype">unsigned</span> OpC = Hi ? PPC::LIS8 : PPC::LI8;
+<a name="l00940"></a>00940 Result = CurDAG->getMachineNode(OpC, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, getI32Imm(Hi));
+<a name="l00941"></a>00941 <span class="comment">// And Lo bits.</span>
+<a name="l00942"></a>00942 Result = CurDAG->getMachineNode(PPC::ORI8, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l00943"></a>00943 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Result, 0), getI32Imm(Lo));
+<a name="l00944"></a>00944 } <span class="keywordflow">else</span> {
+<a name="l00945"></a>00945 <span class="comment">// Just the Hi bits.</span>
+<a name="l00946"></a>00946 Result = CurDAG->getMachineNode(PPC::LIS8, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, getI32Imm(Hi));
+<a name="l00947"></a>00947 }
+<a name="l00948"></a>00948
+<a name="l00949"></a>00949 <span class="comment">// If no shift, we're done.</span>
+<a name="l00950"></a>00950 <span class="keywordflow">if</span> (!Shift) <span class="keywordflow">return</span> Result;
+<a name="l00951"></a>00951
+<a name="l00952"></a>00952 <span class="comment">// Shift for next step if the upper 32-bits were not zero.</span>
+<a name="l00953"></a>00953 <span class="keywordflow">if</span> (Imm) {
+<a name="l00954"></a>00954 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l00955"></a>00955 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Result, 0),
+<a name="l00956"></a>00956 getI32Imm(Shift),
+<a name="l00957"></a>00957 getI32Imm(63 - Shift));
+<a name="l00958"></a>00958 }
+<a name="l00959"></a>00959
+<a name="l00960"></a>00960 <span class="comment">// Add in the last bits as required.</span>
+<a name="l00961"></a>00961 <span class="keywordflow">if</span> ((Hi = (Remainder >> 16) & 0xFFFF)) {
+<a name="l00962"></a>00962 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l00963"></a>00963 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Result, 0), getI32Imm(Hi));
+<a name="l00964"></a>00964 }
+<a name="l00965"></a>00965 <span class="keywordflow">if</span> ((Lo = Remainder & 0xFFFF)) {
+<a name="l00966"></a>00966 Result = CurDAG->getMachineNode(PPC::ORI8, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,
+<a name="l00967"></a>00967 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Result, 0), getI32Imm(Lo));
+<a name="l00968"></a>00968 }
+<a name="l00969"></a>00969
+<a name="l00970"></a>00970 <span class="keywordflow">return</span> Result;
+<a name="l00971"></a>00971 }
+<a name="l00972"></a>00972 <span class="keywordflow">break</span>;
+<a name="l00973"></a>00973 }
+<a name="l00974"></a>00974
+<a name="l00975"></a>00975 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a0158ee47dfa868be5d28e2cbef70d5d0">ISD::SETCC</a>:
+<a name="l00976"></a>00976 <span class="keywordflow">return</span> SelectSETCC(N);
+<a name="l00977"></a>00977 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a9e4500d93af7f70fdff992d9d748559d">PPCISD::GlobalBaseReg</a>:
+<a name="l00978"></a>00978 <span class="keywordflow">return</span> getGlobalBaseReg();
+<a name="l00979"></a>00979
+<a name="l00980"></a>00980 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>: {
+<a name="l00981"></a>00981 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(N)->getIndex();
+<a name="l00982"></a>00982 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TFI = CurDAG->getTargetFrameIndex(FI, N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0));
+<a name="l00983"></a>00983 <span class="keywordtype">unsigned</span> Opc = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> ? PPC::ADDI : PPC::ADDI8;
+<a name="l00984"></a>00984 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#a52753947fce3a01b1c18dd4713c587e8">hasOneUse</a>())
+<a name="l00985"></a>00985 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opc, N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0), TFI,
+<a name="l00986"></a>00986 getSmallIPtrImm(0));
+<a name="l00987"></a>00987 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opc, dl, N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0), TFI,
+<a name="l00988"></a>00988 getSmallIPtrImm(0));
+<a name="l00989"></a>00989 }
+<a name="l00990"></a>00990
+<a name="l00991"></a>00991 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a1850fed22e97200319f85dd13fc7d798">PPCISD::MFCR</a>: {
+<a name="l00992"></a>00992 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l00993"></a>00993 <span class="comment">// Use MFOCRF if supported.</span>
+<a name="l00994"></a>00994 <span class="keywordflow">if</span> (PPCSubTarget.hasMFOCRF())
+<a name="l00995"></a>00995 <span class="keywordflow">return</span> CurDAG->getMachineNode(PPC::MFOCRF, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l00996"></a>00996 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), InFlag);
+<a name="l00997"></a>00997 <span class="keywordflow">else</span>
+<a name="l00998"></a>00998 <span class="keywordflow">return</span> CurDAG->getMachineNode(PPC::MFCRpseud, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l00999"></a>00999 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), InFlag);
+<a name="l01000"></a>01000 }
+<a name="l01001"></a>01001
+<a name="l01002"></a>01002 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1f61c2422057e10403b2f6003543c300">ISD::SDIV</a>: {
+<a name="l01003"></a>01003 <span class="comment">// FIXME: since this depends on the setting of the carry flag from the srawi</span>
+<a name="l01004"></a>01004 <span class="comment">// we should really be making notes about that for the scheduler.</span>
+<a name="l01005"></a>01005 <span class="comment">// FIXME: It sure would be nice if we could cheaply recognize the</span>
+<a name="l01006"></a>01006 <span class="comment">// srl/add/sra pattern the dag combiner will generate for this as</span>
+<a name="l01007"></a>01007 <span class="comment">// sra/addze rather than having to handle sdiv ourselves. oh well.</span>
+<a name="l01008"></a>01008 <span class="keywordtype">unsigned</span> Imm;
+<a name="l01009"></a>01009 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Imm)) {
+<a name="l01010"></a>01010 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l01011"></a>01011 <span class="keywordflow">if</span> ((<span class="keywordtype">signed</span>)Imm > 0 && <a class="code" href="namespacellvm.html#af4d1a918800291e75b01ce1447be0e83">isPowerOf2_32</a>(Imm)) {
+<a name="l01012"></a>01012 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op =
+<a name="l01013"></a>01013 CurDAG->getMachineNode(PPC::SRAWI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>,
+<a name="l01014"></a>01014 N0, getI32Imm(<a class="code" href="namespacellvm.html#a646986783f35e0fef8988f0f28d2589f">Log2_32</a>(Imm)));
+<a name="l01015"></a>01015 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::ADDZE, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l01016"></a>01016 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Op, 0), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Op, 1));
+<a name="l01017"></a>01017 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> ((<span class="keywordtype">signed</span>)Imm < 0 && <a class="code" href="namespacellvm.html#af4d1a918800291e75b01ce1447be0e83">isPowerOf2_32</a>(-Imm)) {
+<a name="l01018"></a>01018 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op =
+<a name="l01019"></a>01019 CurDAG->getMachineNode(PPC::SRAWI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>,
+<a name="l01020"></a>01020 N0, getI32Imm(<a class="code" href="namespacellvm.html#a646986783f35e0fef8988f0f28d2589f">Log2_32</a>(-Imm)));
+<a name="l01021"></a>01021 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PT =
+<a name="l01022"></a>01022 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(PPC::ADDZE, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l01023"></a>01023 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Op, 0), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Op, 1)),
+<a name="l01024"></a>01024 0);
+<a name="l01025"></a>01025 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::NEG, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, PT);
+<a name="l01026"></a>01026 }
+<a name="l01027"></a>01027 }
+<a name="l01028"></a>01028
+<a name="l01029"></a>01029 <span class="comment">// Other cases are autogenerated.</span>
+<a name="l01030"></a>01030 <span class="keywordflow">break</span>;
+<a name="l01031"></a>01031 }
+<a name="l01032"></a>01032
+<a name="l01033"></a>01033 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a>: {
+<a name="l01034"></a>01034 <span class="comment">// Handle preincrement loads.</span>
+<a name="l01035"></a>01035 <a class="code" href="classllvm_1_1LoadSDNode.html">LoadSDNode</a> *LD = cast<LoadSDNode>(N);
+<a name="l01036"></a>01036 <a class="code" href="structllvm_1_1EVT.html">EVT</a> LoadedVT = LD-><a class="code" href="classllvm_1_1MemSDNode.html#a7cead3a2a7771e61083bcc6959915a13" title="getMemoryVT - Return the type of the in-memory value.">getMemoryVT</a>();
+<a name="l01037"></a>01037
+<a name="l01038"></a>01038 <span class="comment">// Normal loads are handled by code generated from the .td file.</span>
+<a name="l01039"></a>01039 <span class="keywordflow">if</span> (LD-><a class="code" href="classllvm_1_1LSBaseSDNode.html#a76f8f644c33a885eaff35f94c39d5048">getAddressingMode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>)
+<a name="l01040"></a>01040 <span class="keywordflow">break</span>;
+<a name="l01041"></a>01041
+<a name="l01042"></a>01042 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Offset = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>();
+<a name="l01043"></a>01043 <span class="keywordflow">if</span> (isa<ConstantSDNode>(Offset) ||
+<a name="l01044"></a>01044 Offset.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a>) {
+<a name="l01045"></a>01045
+<a name="l01046"></a>01046 <span class="keywordtype">unsigned</span> Opcode;
+<a name="l01047"></a>01047 <span class="keywordtype">bool</span> isSExt = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#af15fb8b2d4c9f295bdcf85a1eb506702">getExtensionType</a>() == <a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a>;
+<a name="l01048"></a>01048 <span class="keywordflow">if</span> (LD-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) != <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>) {
+<a name="l01049"></a>01049 <span class="comment">// Handle PPC32 integer and normal FP loads.</span>
+<a name="l01050"></a>01050 assert((!isSExt || LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>) && <span class="stringliteral">"Invalid sext update load"</span>);
+<a name="l01051"></a>01051 <span class="keywordflow">switch</span> (LoadedVT.getSimpleVT().SimpleTy) {
+<a name="l01052"></a>01052 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Invalid PPC load type!"</span>);
+<a name="l01053"></a>01053 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>: Opcode = PPC::LFDU; <span class="keywordflow">break</span>;
+<a name="l01054"></a>01054 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>: Opcode = PPC::LFSU; <span class="keywordflow">break</span>;
+<a name="l01055"></a>01055 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>: Opcode = PPC::LWZU; <span class="keywordflow">break</span>;
+<a name="l01056"></a>01056 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; <span class="keywordflow">break</span>;
+<a name="l01057"></a>01057 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>:
+<a name="l01058"></a>01058 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>: Opcode = PPC::LBZU; <span class="keywordflow">break</span>;
+<a name="l01059"></a>01059 }
+<a name="l01060"></a>01060 } <span class="keywordflow">else</span> {
+<a name="l01061"></a>01061 assert(LD-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> && <span class="stringliteral">"Unknown load result type!"</span>);
+<a name="l01062"></a>01062 assert((!isSExt || LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>) && <span class="stringliteral">"Invalid sext update load"</span>);
+<a name="l01063"></a>01063 <span class="keywordflow">switch</span> (LoadedVT.getSimpleVT().SimpleTy) {
+<a name="l01064"></a>01064 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Invalid PPC load type!"</span>);
+<a name="l01065"></a>01065 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>: Opcode = PPC::LDU; <span class="keywordflow">break</span>;
+<a name="l01066"></a>01066 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>: Opcode = PPC::LWZU8; <span class="keywordflow">break</span>;
+<a name="l01067"></a>01067 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; <span class="keywordflow">break</span>;
+<a name="l01068"></a>01068 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>:
+<a name="l01069"></a>01069 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>: Opcode = PPC::LBZU8; <span class="keywordflow">break</span>;
+<a name="l01070"></a>01070 }
+<a name="l01071"></a>01071 }
+<a name="l01072"></a>01072
+<a name="l01073"></a>01073 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = LD-><a class="code" href="classllvm_1_1MemSDNode.html#ae3cb6fbf8c8cb79e10ac61bd98c85211">getChain</a>();
+<a name="l01074"></a>01074 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Base = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#a3ded48ce66b58b7e7e143991df5dbfae">getBasePtr</a>();
+<a name="l01075"></a>01075 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Offset, Base, Chain };
+<a name="l01076"></a>01076 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opcode, dl, LD-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0),
+<a name="l01077"></a>01077 PPCLowering.getPointerTy(),
+<a name="l01078"></a>01078 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Ops, 3);
+<a name="l01079"></a>01079 } <span class="keywordflow">else</span> {
+<a name="l01080"></a>01080 <span class="keywordtype">unsigned</span> Opcode;
+<a name="l01081"></a>01081 <span class="keywordtype">bool</span> isSExt = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#af15fb8b2d4c9f295bdcf85a1eb506702">getExtensionType</a>() == <a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a>;
+<a name="l01082"></a>01082 <span class="keywordflow">if</span> (LD-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) != <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>) {
+<a name="l01083"></a>01083 <span class="comment">// Handle PPC32 integer and normal FP loads.</span>
+<a name="l01084"></a>01084 assert((!isSExt || LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>) && <span class="stringliteral">"Invalid sext update load"</span>);
+<a name="l01085"></a>01085 <span class="keywordflow">switch</span> (LoadedVT.getSimpleVT().SimpleTy) {
+<a name="l01086"></a>01086 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Invalid PPC load type!"</span>);
+<a name="l01087"></a>01087 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>: Opcode = PPC::LFDUX; <span class="keywordflow">break</span>;
+<a name="l01088"></a>01088 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>: Opcode = PPC::LFSUX; <span class="keywordflow">break</span>;
+<a name="l01089"></a>01089 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>: Opcode = PPC::LWZUX; <span class="keywordflow">break</span>;
+<a name="l01090"></a>01090 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; <span class="keywordflow">break</span>;
+<a name="l01091"></a>01091 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>:
+<a name="l01092"></a>01092 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>: Opcode = PPC::LBZUX; <span class="keywordflow">break</span>;
+<a name="l01093"></a>01093 }
+<a name="l01094"></a>01094 } <span class="keywordflow">else</span> {
+<a name="l01095"></a>01095 assert(LD-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a> && <span class="stringliteral">"Unknown load result type!"</span>);
+<a name="l01096"></a>01096 assert((!isSExt || LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a> || LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>) &&
+<a name="l01097"></a>01097 <span class="stringliteral">"Invalid sext update load"</span>);
+<a name="l01098"></a>01098 <span class="keywordflow">switch</span> (LoadedVT.getSimpleVT().SimpleTy) {
+<a name="l01099"></a>01099 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Invalid PPC load type!"</span>);
+<a name="l01100"></a>01100 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>: Opcode = PPC::LDUX; <span class="keywordflow">break</span>;
+<a name="l01101"></a>01101 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; <span class="keywordflow">break</span>;
+<a name="l01102"></a>01102 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; <span class="keywordflow">break</span>;
+<a name="l01103"></a>01103 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>:
+<a name="l01104"></a>01104 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>: Opcode = PPC::LBZUX8; <span class="keywordflow">break</span>;
+<a name="l01105"></a>01105 }
+<a name="l01106"></a>01106 }
+<a name="l01107"></a>01107
+<a name="l01108"></a>01108 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = LD-><a class="code" href="classllvm_1_1MemSDNode.html#ae3cb6fbf8c8cb79e10ac61bd98c85211">getChain</a>();
+<a name="l01109"></a>01109 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Base = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#a3ded48ce66b58b7e7e143991df5dbfae">getBasePtr</a>();
+<a name="l01110"></a>01110 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Offset, Base, Chain };
+<a name="l01111"></a>01111 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opcode, dl, LD-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0),
+<a name="l01112"></a>01112 PPCLowering.getPointerTy(),
+<a name="l01113"></a>01113 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Ops, 3);
+<a name="l01114"></a>01114 }
+<a name="l01115"></a>01115 }
+<a name="l01116"></a>01116
+<a name="l01117"></a>01117 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>: {
+<a name="l01118"></a>01118 <span class="keywordtype">unsigned</span> Imm, Imm2, SH, MB, ME;
+<a name="l01119"></a>01119 uint64_t <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933ac5de5ce82d03ee1b2f9c10ddcaecf6bc">Imm64</a>;
+<a name="l01120"></a>01120
+<a name="l01121"></a>01121 <span class="comment">// If this is an and of a value rotated between 0 and 31 bits and then and'd</span>
+<a name="l01122"></a>01122 <span class="comment">// with a mask, emit rlwinm</span>
+<a name="l01123"></a>01123 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Imm) &&
+<a name="l01124"></a>01124 isRotateAndMask(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm, <span class="keyword">false</span>, SH, MB, ME)) {
+<a name="l01125"></a>01125 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01126"></a>01126 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+<a name="l01127"></a>01127 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l01128"></a>01128 }
+<a name="l01129"></a>01129 <span class="comment">// If this is just a masked value where the input is not handled above, and</span>
+<a name="l01130"></a>01130 <span class="comment">// is not a rotate-left (handled by a pattern in the .td file), emit rlwinm</span>
+<a name="l01131"></a>01131 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Imm) &&
+<a name="l01132"></a>01132 <a class="code" href="InstCombineAndOrXor_8cpp.html#add947a35dd442e049fda602d9dc9cd20">isRunOfOnes</a>(Imm, MB, ME) &&
+<a name="l01133"></a>01133 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ae8f8f81d8e8d7a557d67622c05786f1d">ISD::ROTL</a>) {
+<a name="l01134"></a>01134 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l01135"></a>01135 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
+<a name="l01136"></a>01136 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l01137"></a>01137 }
+<a name="l01138"></a>01138 <span class="comment">// If this is a 64-bit zero-extension mask, emit rldicl.</span>
+<a name="l01139"></a>01139 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#a7312dc1e31cba7889c13ff9ada91ff15">isInt64Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933ac5de5ce82d03ee1b2f9c10ddcaecf6bc">Imm64</a>) &&
+<a name="l01140"></a>01140 <a class="code" href="namespacellvm.html#a57733d62331de1e4bad496b6408e8f7f">isMask_64</a>(Imm64)) {
+<a name="l01141"></a>01141 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l01142"></a>01142 MB = 64 - <a class="code" href="namespacellvm.html#a8da28d982a3c20fa6e57d94df3059f03">CountTrailingOnes_64</a>(Imm64);
+<a name="l01143"></a>01143 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Val, getI32Imm(0), getI32Imm(MB) };
+<a name="l01144"></a>01144 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLDICL, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, Ops, 3);
+<a name="l01145"></a>01145 }
+<a name="l01146"></a>01146 <span class="comment">// AND X, 0 -> 0, not "rlwinm 32".</span>
+<a name="l01147"></a>01147 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Imm) && (Imm == 0)) {
+<a name="l01148"></a>01148 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1));
+<a name="l01149"></a>01149 <span class="keywordflow">return</span> NULL;
+<a name="l01150"></a>01150 }
+<a name="l01151"></a>01151 <span class="comment">// ISD::OR doesn't get all the bitfield insertion fun.</span>
+<a name="l01152"></a>01152 <span class="comment">// (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert</span>
+<a name="l01153"></a>01153 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Imm) &&
+<a name="l01154"></a>01154 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a> &&
+<a name="l01155"></a>01155 <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), Imm2)) {
+<a name="l01156"></a>01156 <span class="keywordtype">unsigned</span> MB, ME;
+<a name="l01157"></a>01157 Imm = ~(Imm^Imm2);
+<a name="l01158"></a>01158 <span class="keywordflow">if</span> (<a class="code" href="InstCombineAndOrXor_8cpp.html#add947a35dd442e049fda602d9dc9cd20">isRunOfOnes</a>(Imm, MB, ME)) {
+<a name="l01159"></a>01159 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0),
+<a name="l01160"></a>01160 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1),
+<a name="l01161"></a>01161 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
+<a name="l01162"></a>01162 <span class="keywordflow">return</span> CurDAG->getMachineNode(PPC::RLWIMI, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 5);
+<a name="l01163"></a>01163 }
+<a name="l01164"></a>01164 }
+<a name="l01165"></a>01165
+<a name="l01166"></a>01166 <span class="comment">// Other cases are autogenerated.</span>
+<a name="l01167"></a>01167 <span class="keywordflow">break</span>;
+<a name="l01168"></a>01168 }
+<a name="l01169"></a>01169 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a>:
+<a name="l01170"></a>01170 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>)
+<a name="l01171"></a>01171 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> = SelectBitfieldInsert(N))
+<a name="l01172"></a>01172 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>;
+<a name="l01173"></a>01173
+<a name="l01174"></a>01174 <span class="comment">// Other cases are autogenerated.</span>
+<a name="l01175"></a>01175 <span class="keywordflow">break</span>;
+<a name="l01176"></a>01176 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a>: {
+<a name="l01177"></a>01177 <span class="keywordtype">unsigned</span> Imm, SH, MB, ME;
+<a name="l01178"></a>01178 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">isOpcWithIntImmediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, Imm) &&
+<a name="l01179"></a>01179 isRotateAndMask(N, Imm, <span class="keyword">true</span>, SH, MB, ME)) {
+<a name="l01180"></a>01180 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0),
+<a name="l01181"></a>01181 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+<a name="l01182"></a>01182 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l01183"></a>01183 }
+<a name="l01184"></a>01184
+<a name="l01185"></a>01185 <span class="comment">// Other cases are autogenerated.</span>
+<a name="l01186"></a>01186 <span class="keywordflow">break</span>;
+<a name="l01187"></a>01187 }
+<a name="l01188"></a>01188 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>: {
+<a name="l01189"></a>01189 <span class="keywordtype">unsigned</span> Imm, SH, MB, ME;
+<a name="l01190"></a>01190 <span class="keywordflow">if</span> (<a class="code" href="PPCISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">isOpcWithIntImmediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, Imm) &&
+<a name="l01191"></a>01191 isRotateAndMask(N, Imm, <span class="keyword">true</span>, SH, MB, ME)) {
+<a name="l01192"></a>01192 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0),
+<a name="l01193"></a>01193 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
+<a name="l01194"></a>01194 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::RLWINM, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 4);
+<a name="l01195"></a>01195 }
+<a name="l01196"></a>01196
+<a name="l01197"></a>01197 <span class="comment">// Other cases are autogenerated.</span>
+<a name="l01198"></a>01198 <span class="keywordflow">break</span>;
+<a name="l01199"></a>01199 }
+<a name="l01200"></a>01200 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a99ad6b342b7457df56b91d24e66016b3">ISD::SELECT_CC</a>: {
+<a name="l01201"></a>01201 <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> CC = cast<CondCodeSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(4))-><span class="keyword">get</span>();
+<a name="l01202"></a>01202 <a class="code" href="structllvm_1_1EVT.html">EVT</a> PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
+<a name="l01203"></a>01203 <span class="keywordtype">bool</span> isPPC64 = (PtrVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>);
+<a name="l01204"></a>01204
+<a name="l01205"></a>01205 <span class="comment">// Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc</span>
+<a name="l01206"></a>01206 <span class="keywordflow">if</span> (!isPPC64)
+<a name="l01207"></a>01207 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *N1C = dyn_cast<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1)))
+<a name="l01208"></a>01208 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *N2C = dyn_cast<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2)))
+<a name="l01209"></a>01209 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *N3C = dyn_cast<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3)))
+<a name="l01210"></a>01210 <span class="keywordflow">if</span> (N1C->isNullValue() && N3C->isNullValue() &&
+<a name="l01211"></a>01211 N2C->getZExtValue() == 1ULL && CC == <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07a2887cc8b39915a25180f4bca0026a15e">ISD::SETNE</a> &&
+<a name="l01212"></a>01212 <span class="comment">// FIXME: Implement this optzn for PPC64.</span>
+<a name="l01213"></a>01213 N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>) {
+<a name="l01214"></a>01214 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Tmp =
+<a name="l01215"></a>01215 CurDAG->getMachineNode(PPC::ADDIC, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>,
+<a name="l01216"></a>01216 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), getI32Imm(~0U));
+<a name="l01217"></a>01217 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::SUBFE, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l01218"></a>01218 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Tmp, 0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0),
+<a name="l01219"></a>01219 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Tmp, 1));
+<a name="l01220"></a>01220 }
+<a name="l01221"></a>01221
+<a name="l01222"></a>01222 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCReg = SelectCC(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, dl);
+<a name="l01223"></a>01223 <span class="keywordtype">unsigned</span> BROpc = <a class="code" href="PPCISelDAGToDAG_8cpp.html#ac60b36afeca1158879e59a32e1a53ecd">getPredicateForSetCC</a>(CC);
+<a name="l01224"></a>01224
+<a name="l01225"></a>01225 <span class="keywordtype">unsigned</span> SelectCCOp;
+<a name="l01226"></a>01226 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>)
+<a name="l01227"></a>01227 SelectCCOp = PPC::SELECT_CC_I4;
+<a name="l01228"></a>01228 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>)
+<a name="l01229"></a>01229 SelectCCOp = PPC::SELECT_CC_I8;
+<a name="l01230"></a>01230 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>)
+<a name="l01231"></a>01231 SelectCCOp = PPC::SELECT_CC_F4;
+<a name="l01232"></a>01232 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>)
+<a name="l01233"></a>01233 SelectCCOp = PPC::SELECT_CC_F8;
+<a name="l01234"></a>01234 <span class="keywordflow">else</span>
+<a name="l01235"></a>01235 SelectCCOp = PPC::SELECT_CC_VRRC;
+<a name="l01236"></a>01236
+<a name="l01237"></a>01237 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { CCReg, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3),
+<a name="l01238"></a>01238 getI32Imm(BROpc) };
+<a name="l01239"></a>01239 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, SelectCCOp, N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0), Ops, 4);
+<a name="l01240"></a>01240 }
+<a name="l01241"></a>01241 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66a0992940624286ed6bc85cd7163501613">PPCISD::COND_BRANCH</a>: {
+<a name="l01242"></a>01242 <span class="comment">// Op #0 is the Chain.</span>
+<a name="l01243"></a>01243 <span class="comment">// Op #1 is the PPC::PRED_* number.</span>
+<a name="l01244"></a>01244 <span class="comment">// Op #2 is the CR#</span>
+<a name="l01245"></a>01245 <span class="comment">// Op #3 is the Dest MBB</span>
+<a name="l01246"></a>01246 <span class="comment">// Op #4 is the Flag.</span>
+<a name="l01247"></a>01247 <span class="comment">// Prevent PPC::PRED_* from being selected into LI.</span>
+<a name="l01248"></a>01248 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred =
+<a name="l01249"></a>01249 getI32Imm(cast<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1))->getZExtValue());
+<a name="l01250"></a>01250 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { Pred, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3),
+<a name="l01251"></a>01251 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(4) };
+<a name="l01252"></a>01252 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::BCC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Ops, 5);
+<a name="l01253"></a>01253 }
+<a name="l01254"></a>01254 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a6d5e322b263f0d5ea4204efafc1d78bb">ISD::BR_CC</a>: {
+<a name="l01255"></a>01255 <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">ISD::CondCode</a> CC = cast<CondCodeSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1))-><span class="keyword">get</span>();
+<a name="l01256"></a>01256 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">CondCode</a> = SelectCC(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3), <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, dl);
+<a name="l01257"></a>01257 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { getI32Imm(<a class="code" href="PPCISelDAGToDAG_8cpp.html#ac60b36afeca1158879e59a32e1a53ecd">getPredicateForSetCC</a>(CC)), <a class="code" href="namespacellvm_1_1ISD.html#ac3c3cf58d6d631af6a172457304d3d07">CondCode</a>,
+<a name="l01258"></a>01258 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(4), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0) };
+<a name="l01259"></a>01259 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, PPC::BCC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Ops, 4);
+<a name="l01260"></a>01260 }
+<a name="l01261"></a>01261 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a716765ad6ce5be71f987cd2097b1cdbf">ISD::BRIND</a>: {
+<a name="l01262"></a>01262 <span class="comment">// FIXME: Should custom lower this.</span>
+<a name="l01263"></a>01263 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l01264"></a>01264 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="classllvm_1_1Target.html">Target</a> = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l01265"></a>01265 <span class="keywordtype">unsigned</span> Opc = Target.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> ? <a class="code" href="namespacellvm_1_1PPCISD.html#a69ad64696d1df3be05f01dfb67f5bc66aa48a0d892596a0da3cf4a82c6ff5a91f">PPC::MTCTR</a> : PPC::MTCTR8;
+<a name="l01266"></a>01266 <span class="keywordtype">unsigned</span> Reg = Target.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>() == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> ? PPC::BCTR : PPC::BCTR8;
+<a name="l01267"></a>01267 Chain = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(Opc, dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>, Target,
+<a name="l01268"></a>01268 Chain), 0);
+<a name="l01269"></a>01269 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Reg, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Chain);
+<a name="l01270"></a>01270 }
+<a name="l01271"></a>01271 }
+<a name="l01272"></a>01272
+<a name="l01273"></a>01273 <span class="keywordflow">return</span> SelectCode(N);
+<a name="l01274"></a>01274 }
+<a name="l01275"></a>01275
+<a name="l01276"></a>01276
+<a name="l01277"></a>01277 <span class="comment"></span>
+<a name="l01278"></a>01278 <span class="comment">/// createPPCISelDag - This pass converts a legalized DAG into a</span>
+<a name="l01279"></a>01279 <span class="comment">/// PowerPC-specific DAG, ready for instruction scheduling.</span>
+<a name="l01280"></a>01280 <span class="comment">///</span>
+<a name="l01281"></a><a class="code" href="namespacellvm.html#a6df8f371187e3eda575eae096cbc2f7c">01281</a> <span class="comment"></span><a class="code" href="classllvm_1_1FunctionPass.html">FunctionPass</a> *<a class="code" href="namespacellvm.html#a6df8f371187e3eda575eae096cbc2f7c">llvm::createPPCISelDag</a>(<a class="code" href="classllvm_1_1PPCTargetMachine.html">PPCTargetMachine</a> &TM) {
+<a name="l01282"></a>01282 <span class="keywordflow">return</span> <span class="keyword">new</span> PPCDAGToDAGISel(TM);
+<a name="l01283"></a>01283 }
+<a name="l01284"></a>01284
+</pre></div></div>
+</div>
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+align="middle" border="0"/>1.7.5.1</a><br>
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