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Tanya Lattner
tonic at nondot.org
Thu Dec 20 22:58:17 PST 2012
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+<div class="title">ScheduleDAGInstrs.h</div> </div>
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+<div class="contents">
+<a href="ScheduleDAGInstrs_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file implements the ScheduleDAGInstrs class, which implements</span>
+<a name="l00011"></a>00011 <span class="comment">// scheduling for a MachineInstr-based dependency graph.</span>
+<a name="l00012"></a>00012 <span class="comment">//</span>
+<a name="l00013"></a>00013 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00014"></a>00014
+<a name="l00015"></a>00015 <span class="preprocessor">#ifndef SCHEDULEDAGINSTRS_H</span>
+<a name="l00016"></a>00016 <span class="preprocessor"></span><span class="preprocessor">#define SCHEDULEDAGINSTRS_H</span>
+<a name="l00017"></a>00017 <span class="preprocessor"></span>
+<a name="l00018"></a>00018 <span class="preprocessor">#include "<a class="code" href="MachineDominators_8h.html">llvm/CodeGen/MachineDominators.h</a>"</span>
+<a name="l00019"></a>00019 <span class="preprocessor">#include "<a class="code" href="MachineLoopInfo_8h.html">llvm/CodeGen/MachineLoopInfo.h</a>"</span>
+<a name="l00020"></a>00020 <span class="preprocessor">#include "<a class="code" href="ScheduleDAG_8h.html">llvm/CodeGen/ScheduleDAG.h</a>"</span>
+<a name="l00021"></a>00021 <span class="preprocessor">#include "<a class="code" href="TargetSchedule_8h.html">llvm/CodeGen/TargetSchedule.h</a>"</span>
+<a name="l00022"></a>00022 <span class="preprocessor">#include "<a class="code" href="Compiler_8h.html">llvm/Support/Compiler.h</a>"</span>
+<a name="l00023"></a>00023 <span class="preprocessor">#include "<a class="code" href="TargetRegisterInfo_8h.html">llvm/Target/TargetRegisterInfo.h</a>"</span>
+<a name="l00024"></a>00024 <span class="preprocessor">#include "<a class="code" href="SmallSet_8h.html">llvm/ADT/SmallSet.h</a>"</span>
+<a name="l00025"></a>00025 <span class="preprocessor">#include "<a class="code" href="SparseSet_8h.html">llvm/ADT/SparseSet.h</a>"</span>
+<a name="l00026"></a>00026 <span class="preprocessor">#include <map></span>
+<a name="l00027"></a>00027
+<a name="l00028"></a>00028 <span class="keyword">namespace </span>llvm {
+<a name="l00029"></a>00029 <span class="keyword">class </span>MachineLoopInfo;
+<a name="l00030"></a>00030 <span class="keyword">class </span>MachineDominatorTree;
+<a name="l00031"></a>00031 <span class="keyword">class </span>LiveIntervals;
+<a name="l00032"></a>00032 <span class="keyword">class </span>RegPressureTracker;
+<a name="l00033"></a>00033 <span class="comment"></span>
+<a name="l00034"></a>00034 <span class="comment"> /// An individual mapping from virtual register number to SUnit.</span>
+<a name="l00035"></a><a class="code" href="structllvm_1_1VReg2SUnit.html">00035</a> <span class="comment"></span> <span class="keyword">struct </span><a class="code" href="structllvm_1_1VReg2SUnit.html" title="An individual mapping from virtual register number to SUnit.">VReg2SUnit</a> {
+<a name="l00036"></a><a class="code" href="structllvm_1_1VReg2SUnit.html#a419258ce1004e465d7ac330fa721ab77">00036</a> <span class="keywordtype">unsigned</span> <a class="code" href="structllvm_1_1VReg2SUnit.html#a419258ce1004e465d7ac330fa721ab77">VirtReg</a>;
+<a name="l00037"></a><a class="code" href="structllvm_1_1VReg2SUnit.html#a62cea84ba15a90f1f6c497f16d8eeda3">00037</a> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *<a class="code" href="structllvm_1_1VReg2SUnit.html#a62cea84ba15a90f1f6c497f16d8eeda3">SU</a>;
+<a name="l00038"></a>00038
+<a name="l00039"></a><a class="code" href="structllvm_1_1VReg2SUnit.html#ae059bbf3cf99bd7c6ce60344d9e66ee0">00039</a> <a class="code" href="structllvm_1_1VReg2SUnit.html#ae059bbf3cf99bd7c6ce60344d9e66ee0">VReg2SUnit</a>(<span class="keywordtype">unsigned</span> reg, <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *su): <a class="code" href="structllvm_1_1VReg2SUnit.html#a419258ce1004e465d7ac330fa721ab77">VirtReg</a>(reg), <a class="code" href="structllvm_1_1VReg2SUnit.html#a62cea84ba15a90f1f6c497f16d8eeda3">SU</a>(su) {}
+<a name="l00040"></a>00040
+<a name="l00041"></a><a class="code" href="structllvm_1_1VReg2SUnit.html#ab5f749243df16c2d399b84f4de4d3eec">00041</a> <span class="keywordtype">unsigned</span> <a class="code" href="structllvm_1_1VReg2SUnit.html#ab5f749243df16c2d399b84f4de4d3eec">getSparseSetIndex</a>()<span class="keyword"> const </span>{
+<a name="l00042"></a>00042 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html#aa0f7275b32d79810c71102ca390273f3">TargetRegisterInfo::virtReg2Index</a>(<a class="code" href="structllvm_1_1VReg2SUnit.html#a419258ce1004e465d7ac330fa721ab77">VirtReg</a>);
+<a name="l00043"></a>00043 }
+<a name="l00044"></a>00044 };
+<a name="l00045"></a>00045 <span class="comment"></span>
+<a name="l00046"></a>00046 <span class="comment"> /// Record a physical register access.</span>
+<a name="l00047"></a>00047 <span class="comment"> /// For non data-dependent uses, OpIdx == -1.</span>
+<a name="l00048"></a><a class="code" href="structllvm_1_1PhysRegSUOper.html">00048</a> <span class="comment"></span> <span class="keyword">struct </span><a class="code" href="structllvm_1_1PhysRegSUOper.html">PhysRegSUOper</a> {
+<a name="l00049"></a><a class="code" href="structllvm_1_1PhysRegSUOper.html#a36313119b2c51cd23a72a56123e20bba">00049</a> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *<a class="code" href="structllvm_1_1PhysRegSUOper.html#a36313119b2c51cd23a72a56123e20bba">SU</a>;
+<a name="l00050"></a><a class="code" href="structllvm_1_1PhysRegSUOper.html#a315b06a83e904cae88da78235abfb78a">00050</a> <span class="keywordtype">int</span> <a class="code" href="structllvm_1_1PhysRegSUOper.html#a315b06a83e904cae88da78235abfb78a">OpIdx</a>;
+<a name="l00051"></a>00051
+<a name="l00052"></a><a class="code" href="structllvm_1_1PhysRegSUOper.html#a02369e7df4992b93087f3701763800f6">00052</a> <a class="code" href="structllvm_1_1PhysRegSUOper.html#a02369e7df4992b93087f3701763800f6">PhysRegSUOper</a>(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *su, <span class="keywordtype">int</span> op): <a class="code" href="structllvm_1_1PhysRegSUOper.html#a36313119b2c51cd23a72a56123e20bba">SU</a>(su), <a class="code" href="structllvm_1_1PhysRegSUOper.html#a315b06a83e904cae88da78235abfb78a">OpIdx</a>(op) {}
+<a name="l00053"></a>00053 };
+<a name="l00054"></a>00054 <span class="comment"></span>
+<a name="l00055"></a>00055 <span class="comment"> /// Combine a SparseSet with a 1x1 vector to track physical registers.</span>
+<a name="l00056"></a>00056 <span class="comment"> /// The SparseSet allows iterating over the (few) live registers for quickly</span>
+<a name="l00057"></a>00057 <span class="comment"> /// comparing against a regmask or clearing the set.</span>
+<a name="l00058"></a>00058 <span class="comment"> ///</span>
+<a name="l00059"></a>00059 <span class="comment"> /// Storage for the map is allocated once for the pass. The map can be</span>
+<a name="l00060"></a>00060 <span class="comment"> /// cleared between scheduling regions without freeing unused entries.</span>
+<a name="l00061"></a><a class="code" href="classllvm_1_1Reg2SUnitsMap.html">00061</a> <span class="comment"></span> <span class="keyword">class </span><a class="code" href="classllvm_1_1Reg2SUnitsMap.html">Reg2SUnitsMap</a> {
+<a name="l00062"></a>00062 <a class="code" href="classllvm_1_1SparseSet.html">SparseSet<unsigned></a> PhysRegSet;
+<a name="l00063"></a>00063 std::vector<std::vector<PhysRegSUOper> > SUnits;
+<a name="l00064"></a>00064 <span class="keyword">public</span>:
+<a name="l00065"></a><a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a75a7b9e4512ce3e955d10e1ba18d53cd">00065</a> <span class="keyword">typedef</span> <a class="code" href="classllvm_1_1SparseSet.html">SparseSet<unsigned>::const_iterator</a> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a75a7b9e4512ce3e955d10e1ba18d53cd">const_iterator</a>;
+<a name="l00066"></a>00066
+<a name="l00067"></a>00067 <span class="comment">// Allow iteration over register numbers (keys) in the map. If needed, we</span>
+<a name="l00068"></a>00068 <span class="comment">// can provide an iterator over SUnits (values) as well.</span>
+<a name="l00069"></a><a class="code" href="classllvm_1_1Reg2SUnitsMap.html#af337d6d042431ad3425f3187e4895a29">00069</a> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a75a7b9e4512ce3e955d10e1ba18d53cd">const_iterator</a> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#af337d6d042431ad3425f3187e4895a29">reg_begin</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> PhysRegSet.<a class="code" href="classllvm_1_1SparseSet.html#adf89ae764788137664ba65549e42b047">begin</a>(); }
+<a name="l00070"></a><a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a4cb152c1f4bb31477f7db6fbff66c68d">00070</a> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a75a7b9e4512ce3e955d10e1ba18d53cd">const_iterator</a> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a4cb152c1f4bb31477f7db6fbff66c68d">reg_end</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> PhysRegSet.<a class="code" href="classllvm_1_1SparseSet.html#a337ac3a574df74649d67cac686aaf580">end</a>(); }
+<a name="l00071"></a>00071 <span class="comment"></span>
+<a name="l00072"></a>00072 <span class="comment"> /// Initialize the map with the number of registers.</span>
+<a name="l00073"></a>00073 <span class="comment"> /// If the map is already large enough, no allocation occurs.</span>
+<a name="l00074"></a>00074 <span class="comment"> /// For simplicity we expect the map to be empty().</span>
+<a name="l00075"></a>00075 <span class="comment"></span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#ac45d3b179980776d67e8b73129e8de3c" title="Initialize the map with the number of registers.">setRegLimit</a>(<span class="keywordtype">unsigned</span> Limit);
+<a name="l00076"></a>00076 <span class="comment"></span>
+<a name="l00077"></a>00077 <span class="comment"> /// Returns true if the map is empty.</span>
+<a name="l00078"></a><a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a3a7dca96d6cd2cb8d51a372ba5fcb9e4">00078</a> <span class="comment"></span> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a3a7dca96d6cd2cb8d51a372ba5fcb9e4" title="Returns true if the map is empty.">empty</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> PhysRegSet.<a class="code" href="classllvm_1_1SparseSet.html#a33ce23f0739f7b36a3c462d7b6d9ae84">empty</a>(); }
+<a name="l00079"></a>00079 <span class="comment"></span>
+<a name="l00080"></a>00080 <span class="comment"> /// Clear the map without deallocating storage.</span>
+<a name="l00081"></a>00081 <span class="comment"></span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a2e1b2e5ff1549dc83559a1cf5a2ad9ee" title="Clear the map without deallocating storage.">clear</a>();
+<a name="l00082"></a>00082
+<a name="l00083"></a><a class="code" href="classllvm_1_1Reg2SUnitsMap.html#ad0f0e5a78b826c8e69b8d2974765d5dd">00083</a> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#ad0f0e5a78b826c8e69b8d2974765d5dd">contains</a>(<span class="keywordtype">unsigned</span> <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>)<span class="keyword"> const </span>{ <span class="keywordflow">return</span> PhysRegSet.<a class="code" href="classllvm_1_1SparseSet.html#a5196d77298bdf036bbf71935769c2f5e">count</a>(Reg); }
+<a name="l00084"></a>00084 <span class="comment"></span>
+<a name="l00085"></a>00085 <span class="comment"> /// If this register is mapped, return its existing SUnits vector.</span>
+<a name="l00086"></a>00086 <span class="comment"> /// Otherwise map the register and return an empty SUnits vector.</span>
+<a name="l00087"></a><a class="code" href="classllvm_1_1Reg2SUnitsMap.html#adfdc2569c0a038d4c129ed78d31f044e">00087</a> <span class="comment"></span> std::vector<PhysRegSUOper> &<a class="code" href="classllvm_1_1Reg2SUnitsMap.html#adfdc2569c0a038d4c129ed78d31f044e">operator[]</a>(<span class="keywordtype">unsigned</span> <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>) {
+<a name="l00088"></a>00088 <span class="keywordtype">bool</span> New = PhysRegSet.<a class="code" href="classllvm_1_1SparseSet.html#a1a4055576fc0e9afc07647fe6dae8b0d">insert</a>(Reg).second;
+<a name="l00089"></a>00089 assert((!New || SUnits[Reg].<a class="code" href="classllvm_1_1Reg2SUnitsMap.html#a3a7dca96d6cd2cb8d51a372ba5fcb9e4" title="Returns true if the map is empty.">empty</a>()) && <span class="stringliteral">"stale SUnits vector"</span>);
+<a name="l00090"></a>00090 (void)New;
+<a name="l00091"></a>00091 <span class="keywordflow">return</span> SUnits[<a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>];
+<a name="l00092"></a>00092 }
+<a name="l00093"></a>00093 <span class="comment"></span>
+<a name="l00094"></a>00094 <span class="comment"> /// Erase an existing element without freeing memory.</span>
+<a name="l00095"></a><a class="code" href="classllvm_1_1Reg2SUnitsMap.html#aa78354fe4df44c18b65b7d454b8ccb75">00095</a> <span class="comment"></span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html#aa78354fe4df44c18b65b7d454b8ccb75" title="Erase an existing element without freeing memory.">erase</a>(<span class="keywordtype">unsigned</span> <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>) {
+<a name="l00096"></a>00096 PhysRegSet.<a class="code" href="classllvm_1_1SparseSet.html#a5a00f6afdfec487d3165d29e57452b32">erase</a>(Reg);
+<a name="l00097"></a>00097 SUnits[<a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>].clear();
+<a name="l00098"></a>00098 }
+<a name="l00099"></a>00099 };
+<a name="l00100"></a>00100 <span class="comment"></span>
+<a name="l00101"></a>00101 <span class="comment"> /// Use SparseSet as a SparseMap by relying on the fact that it never</span>
+<a name="l00102"></a>00102 <span class="comment"> /// compares ValueT's, only unsigned keys. This allows the set to be cleared</span>
+<a name="l00103"></a>00103 <span class="comment"> /// between scheduling regions in constant time as long as ValueT does not</span>
+<a name="l00104"></a>00104 <span class="comment"> /// require a destructor.</span>
+<a name="l00105"></a><a class="code" href="namespacellvm.html#af1236ab2574debb281ea6e38b2ee5a3a">00105</a> <span class="comment"></span> <span class="keyword">typedef</span> <a class="code" href="classllvm_1_1SparseSet.html">SparseSet<VReg2SUnit, VirtReg2IndexFunctor></a> <a class="code" href="namespacellvm.html#af1236ab2574debb281ea6e38b2ee5a3a">VReg2SUnitMap</a>;
+<a name="l00106"></a>00106 <span class="comment"></span>
+<a name="l00107"></a>00107 <span class="comment"> /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of</span>
+<a name="l00108"></a>00108 <span class="comment"> /// MachineInstrs.</span>
+<a name="l00109"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html">00109</a> <span class="comment"></span> <span class="keyword">class </span><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html">ScheduleDAGInstrs</a> : <span class="keyword">public</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> {
+<a name="l00110"></a>00110 <span class="keyword">protected</span>:
+<a name="l00111"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a1a23f5e657727a730e585ad461d914d8">00111</a> <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineLoopInfo.html">MachineLoopInfo</a> &<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a1a23f5e657727a730e585ad461d914d8">MLI</a>;
+<a name="l00112"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ab805a4eee0a4f76e28dd11bcc86b1083">00112</a> <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineDominatorTree.html">MachineDominatorTree</a> &<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ab805a4eee0a4f76e28dd11bcc86b1083">MDT</a>;
+<a name="l00113"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a48dac2c15614f61bd7cb73fe322099fa">00113</a> <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a48dac2c15614f61bd7cb73fe322099fa">MFI</a>;
+<a name="l00114"></a>00114 <span class="comment"></span>
+<a name="l00115"></a>00115 <span class="comment"> /// Live Intervals provides reaching defs in preRA scheduling.</span>
+<a name="l00116"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a81f901b06e024f4f2f50e1831c0d4b9e">00116</a> <span class="comment"></span> <a class="code" href="classllvm_1_1LiveIntervals.html">LiveIntervals</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a81f901b06e024f4f2f50e1831c0d4b9e" title="Live Intervals provides reaching defs in preRA scheduling.">LIS</a>;
+<a name="l00117"></a>00117 <span class="comment"></span>
+<a name="l00118"></a>00118 <span class="comment"> /// TargetSchedModel provides an interface to the machine model.</span>
+<a name="l00119"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#abb11b650b88a61630eba2a1b2eaa6fd0">00119</a> <span class="comment"></span> <a class="code" href="classllvm_1_1TargetSchedModel.html" title="Provide an instruction scheduling machine model to CodeGen passes.">TargetSchedModel</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#abb11b650b88a61630eba2a1b2eaa6fd0" title="TargetSchedModel provides an interface to the machine model.">SchedModel</a>;
+<a name="l00120"></a>00120 <span class="comment"></span>
+<a name="l00121"></a>00121 <span class="comment"> /// isPostRA flag indicates vregs cannot be present.</span>
+<a name="l00122"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a73edb004de8911374552b25481e9e9c3">00122</a> <span class="comment"></span> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a73edb004de8911374552b25481e9e9c3" title="isPostRA flag indicates vregs cannot be present.">IsPostRA</a>;
+<a name="l00123"></a>00123 <span class="comment"></span>
+<a name="l00124"></a>00124 <span class="comment"> /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using</span>
+<a name="l00125"></a>00125 <span class="comment"> /// the def-side latency only.</span>
+<a name="l00126"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae0ca516c44b9cd0b3d2b67232020cd3f">00126</a> <span class="comment"></span> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae0ca516c44b9cd0b3d2b67232020cd3f">UnitLatencies</a>;
+<a name="l00127"></a>00127 <span class="comment"></span>
+<a name="l00128"></a>00128 <span class="comment"> /// The standard DAG builder does not normally include terminators as DAG</span>
+<a name="l00129"></a>00129 <span class="comment"> /// nodes because it does not create the necessary dependencies to prevent</span>
+<a name="l00130"></a>00130 <span class="comment"> /// reordering. A specialized scheduler can overide</span>
+<a name="l00131"></a>00131 <span class="comment"> /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate</span>
+<a name="l00132"></a>00132 <span class="comment"> /// it has taken responsibility for scheduling the terminator correctly.</span>
+<a name="l00133"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a2ad332011e2040d133de24f33cf3f4cd">00133</a> <span class="comment"></span> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a2ad332011e2040d133de24f33cf3f4cd">CanHandleTerminators</a>;
+<a name="l00134"></a>00134 <span class="comment"></span>
+<a name="l00135"></a>00135 <span class="comment"> /// State specific to the current scheduling region.</span>
+<a name="l00136"></a>00136 <span class="comment"> /// ------------------------------------------------</span>
+<a name="l00137"></a>00137 <span class="comment"></span><span class="comment"></span>
+<a name="l00138"></a>00138 <span class="comment"> /// The block in which to insert instructions</span>
+<a name="l00139"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a254403f7804208ade3cb68086201cb7a">00139</a> <span class="comment"></span> <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a254403f7804208ade3cb68086201cb7a" title="The block in which to insert instructions.">BB</a>;
+<a name="l00140"></a>00140 <span class="comment"></span>
+<a name="l00141"></a>00141 <span class="comment"> /// The beginning of the range to be scheduled.</span>
+<a name="l00142"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae81ad8ece7681af658742f6d4e2fcfb1">00142</a> <span class="comment"></span> <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae81ad8ece7681af658742f6d4e2fcfb1" title="The beginning of the range to be scheduled.">RegionBegin</a>;
+<a name="l00143"></a>00143 <span class="comment"></span>
+<a name="l00144"></a>00144 <span class="comment"> /// The end of the range to be scheduled.</span>
+<a name="l00145"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a3f74b283acf0dfb537bc387e49344f04">00145</a> <span class="comment"></span> <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a3f74b283acf0dfb537bc387e49344f04" title="The end of the range to be scheduled.">RegionEnd</a>;
+<a name="l00146"></a>00146 <span class="comment"></span>
+<a name="l00147"></a>00147 <span class="comment"> /// The index in BB of RegionEnd.</span>
+<a name="l00148"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a4cc541e7d76b4d82b86a351a19addd32">00148</a> <span class="comment"></span> <span class="keywordtype">unsigned</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a4cc541e7d76b4d82b86a351a19addd32" title="The index in BB of RegionEnd.">EndIndex</a>;
+<a name="l00149"></a>00149 <span class="comment"></span>
+<a name="l00150"></a>00150 <span class="comment"> /// After calling BuildSchedGraph, each machine instruction in the current</span>
+<a name="l00151"></a>00151 <span class="comment"> /// scheduling region is mapped to an SUnit.</span>
+<a name="l00152"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a077eef2c61ca462db1800cc506092d38">00152</a> <span class="comment"></span> <a class="code" href="classllvm_1_1DenseMap.html">DenseMap<MachineInstr*, SUnit*></a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a077eef2c61ca462db1800cc506092d38">MISUnitMap</a>;
+<a name="l00153"></a>00153 <span class="comment"></span>
+<a name="l00154"></a>00154 <span class="comment"> /// State internal to DAG building.</span>
+<a name="l00155"></a>00155 <span class="comment"> /// -------------------------------</span>
+<a name="l00156"></a>00156 <span class="comment"></span><span class="comment"></span>
+<a name="l00157"></a>00157 <span class="comment"> /// Defs, Uses - Remember where defs and uses of each register are as we</span>
+<a name="l00158"></a>00158 <span class="comment"> /// iterate upward through the instructions. This is allocated here instead</span>
+<a name="l00159"></a>00159 <span class="comment"> /// of inside BuildSchedGraph to avoid the need for it to be initialized and</span>
+<a name="l00160"></a>00160 <span class="comment"> /// destructed for each block.</span>
+<a name="l00161"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae384109023f32441ff89f13b79be6b89">00161</a> <span class="comment"></span> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html">Reg2SUnitsMap</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae384109023f32441ff89f13b79be6b89">Defs</a>;
+<a name="l00162"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#af0b2bf4940e563082d1d2bf8a9e5521f">00162</a> <a class="code" href="classllvm_1_1Reg2SUnitsMap.html">Reg2SUnitsMap</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#af0b2bf4940e563082d1d2bf8a9e5521f">Uses</a>;
+<a name="l00163"></a>00163 <span class="comment"></span>
+<a name="l00164"></a>00164 <span class="comment"> /// Track the last instructon in this region defining each virtual register.</span>
+<a name="l00165"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a5b7f785c0a719640a922fece8a550100">00165</a> <span class="comment"></span> <a class="code" href="classllvm_1_1SparseSet.html">VReg2SUnitMap</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a5b7f785c0a719640a922fece8a550100" title="Track the last instructon in this region defining each virtual register.">VRegDefs</a>;
+<a name="l00166"></a>00166 <span class="comment"></span>
+<a name="l00167"></a>00167 <span class="comment"> /// PendingLoads - Remember where unknown loads are after the most recent</span>
+<a name="l00168"></a>00168 <span class="comment"> /// unknown store, as we iterate. As with Defs and Uses, this is here</span>
+<a name="l00169"></a>00169 <span class="comment"> /// to minimize construction/destruction.</span>
+<a name="l00170"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a4afc086f7471b060731e7fbf248958f4">00170</a> <span class="comment"></span> std::vector<SUnit *> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a4afc086f7471b060731e7fbf248958f4">PendingLoads</a>;
+<a name="l00171"></a>00171 <span class="comment"></span>
+<a name="l00172"></a>00172 <span class="comment"> /// DbgValues - Remember instruction that precedes DBG_VALUE.</span>
+<a name="l00173"></a>00173 <span class="comment"> /// These are generated by buildSchedGraph but persist so they can be</span>
+<a name="l00174"></a>00174 <span class="comment"> /// referenced when emitting the final schedule.</span>
+<a name="l00175"></a>00175 <span class="comment"></span> <span class="keyword">typedef</span> std::vector<std::pair<MachineInstr *, MachineInstr *> >
+<a name="l00176"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a5c8f93623f55c06341ca6b954a3dbebe">00176</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a5c8f93623f55c06341ca6b954a3dbebe">DbgValueVector</a>;
+<a name="l00177"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6837fb2c08f4c8c986a4689a37ca93cf">00177</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a5c8f93623f55c06341ca6b954a3dbebe">DbgValueVector</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6837fb2c08f4c8c986a4689a37ca93cf">DbgValues</a>;
+<a name="l00178"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a25ae020b571d18d34d03097d91ca0f40">00178</a> <a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a25ae020b571d18d34d03097d91ca0f40">FirstDbgValue</a>;
+<a name="l00179"></a>00179
+<a name="l00180"></a>00180 <span class="keyword">public</span>:
+<a name="l00181"></a>00181 <span class="keyword">explicit</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a383a4964b5cee6adc7fa5017c771d939">ScheduleDAGInstrs</a>(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &mf,
+<a name="l00182"></a>00182 <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineLoopInfo.html">MachineLoopInfo</a> &mli,
+<a name="l00183"></a>00183 <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineDominatorTree.html">MachineDominatorTree</a> &mdt,
+<a name="l00184"></a>00184 <span class="keywordtype">bool</span> IsPostRAFlag,
+<a name="l00185"></a>00185 <a class="code" href="classllvm_1_1LiveIntervals.html">LiveIntervals</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a81f901b06e024f4f2f50e1831c0d4b9e" title="Live Intervals provides reaching defs in preRA scheduling.">LIS</a> = 0);
+<a name="l00186"></a>00186
+<a name="l00187"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae5699f6d46c8153c84b71e21a9259e9e">00187</a> <span class="keyword">virtual</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae5699f6d46c8153c84b71e21a9259e9e">~ScheduleDAGInstrs</a>() {}
+<a name="l00188"></a>00188 <span class="comment"></span>
+<a name="l00189"></a>00189 <span class="comment"> /// \brief Get the machine model for instruction scheduling.</span>
+<a name="l00190"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ab077d62392fe288ad041b43622d93346">00190</a> <span class="comment"></span> <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetSchedModel.html" title="Provide an instruction scheduling machine model to CodeGen passes.">TargetSchedModel</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ab077d62392fe288ad041b43622d93346" title="Get the machine model for instruction scheduling.">getSchedModel</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> &<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#abb11b650b88a61630eba2a1b2eaa6fd0" title="TargetSchedModel provides an interface to the machine model.">SchedModel</a>; }
+<a name="l00191"></a>00191 <span class="comment"></span>
+<a name="l00192"></a>00192 <span class="comment"> /// \brief Resolve and cache a resolved scheduling class for an SUnit.</span>
+<a name="l00193"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6717374178b6677be5b2f5d227d312cf">00193</a> <span class="comment"></span> <span class="keyword">const</span> <a class="code" href="structllvm_1_1MCSchedClassDesc.html">MCSchedClassDesc</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6717374178b6677be5b2f5d227d312cf" title="Resolve and cache a resolved scheduling class for an SUnit.">getSchedClass</a>(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU)<span class="keyword"> const </span>{
+<a name="l00194"></a>00194 <span class="keywordflow">if</span> (!SU-><a class="code" href="classllvm_1_1SUnit.html#a2b2c6049e5141829267f4f9193b475d4">SchedClass</a>)
+<a name="l00195"></a>00195 SU-><a class="code" href="classllvm_1_1SUnit.html#a2b2c6049e5141829267f4f9193b475d4">SchedClass</a> = <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#abb11b650b88a61630eba2a1b2eaa6fd0" title="TargetSchedModel provides an interface to the machine model.">SchedModel</a>.<a class="code" href="classllvm_1_1TargetSchedModel.html#a615cad8f2751cc7fcc8115bc24c7f646" title="Return the MCSchedClassDesc for this instruction.">resolveSchedClass</a>(SU-><a class="code" href="classllvm_1_1SUnit.html#adb119d63d924841b0523d67dfdd1bf61">getInstr</a>());
+<a name="l00196"></a>00196 <span class="keywordflow">return</span> SU-><a class="code" href="classllvm_1_1SUnit.html#a2b2c6049e5141829267f4f9193b475d4">SchedClass</a>;
+<a name="l00197"></a>00197 }
+<a name="l00198"></a>00198 <span class="comment"></span>
+<a name="l00199"></a>00199 <span class="comment"> /// begin - Return an iterator to the top of the current scheduling region.</span>
+<a name="l00200"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#aeb9c314de586393b2cb695733eeafc6c">00200</a> <span class="comment"></span> <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#aeb9c314de586393b2cb695733eeafc6c" title="begin - Return an iterator to the top of the current scheduling region.">begin</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae81ad8ece7681af658742f6d4e2fcfb1" title="The beginning of the range to be scheduled.">RegionBegin</a>; }
+<a name="l00201"></a>00201 <span class="comment"></span>
+<a name="l00202"></a>00202 <span class="comment"> /// end - Return an iterator to the bottom of the current scheduling region.</span>
+<a name="l00203"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#aa1a4554243ad6d8f52e7d12a74f0cded">00203</a> <span class="comment"></span> <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#aa1a4554243ad6d8f52e7d12a74f0cded" title="end - Return an iterator to the bottom of the current scheduling region.">end</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a3f74b283acf0dfb537bc387e49344f04" title="The end of the range to be scheduled.">RegionEnd</a>; }
+<a name="l00204"></a>00204 <span class="comment"></span>
+<a name="l00205"></a>00205 <span class="comment"> /// newSUnit - Creates a new SUnit and return a ptr to it.</span>
+<a name="l00206"></a>00206 <span class="comment"></span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6c497ec4b863f7d59aa3678740331c8e" title="newSUnit - Creates a new SUnit and return a ptr to it.">newSUnit</a>(<a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>);
+<a name="l00207"></a>00207 <span class="comment"></span>
+<a name="l00208"></a>00208 <span class="comment"> /// getSUnit - Return an existing SUnit for this MI, or NULL.</span>
+<a name="l00209"></a>00209 <span class="comment"></span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6cf6c94d54730c618ac5f86d2140d032" title="getSUnit - Return an existing SUnit for this MI, or NULL.">getSUnit</a>(<a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>) <span class="keyword">const</span>;
+<a name="l00210"></a>00210 <span class="comment"></span>
+<a name="l00211"></a>00211 <span class="comment"> /// startBlock - Prepare to perform scheduling in the given block.</span>
+<a name="l00212"></a>00212 <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a2822215b7634783aece96ef695a72f1d" title="startBlock - Prepare to perform scheduling in the given block.">startBlock</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a254403f7804208ade3cb68086201cb7a" title="The block in which to insert instructions.">BB</a>);
+<a name="l00213"></a>00213 <span class="comment"></span>
+<a name="l00214"></a>00214 <span class="comment"> /// finishBlock - Clean up after scheduling in the given block.</span>
+<a name="l00215"></a>00215 <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a1f9a4461e2c9ac06b97f55554f836d66" title="finishBlock - Clean up after scheduling in the given block.">finishBlock</a>();
+<a name="l00216"></a>00216 <span class="comment"></span>
+<a name="l00217"></a>00217 <span class="comment"> /// Initialize the scheduler state for the next scheduling region.</span>
+<a name="l00218"></a>00218 <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#aa6cc1d405d81319279a556d58ba6facd" title="Initialize the scheduler state for the next scheduling region.">enterRegion</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> *bb,
+<a name="l00219"></a>00219 <a class="code" href="classllvm_1_1MachineBasicBlock_1_1bundle__iterator.html">MachineBasicBlock::iterator</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#aeb9c314de586393b2cb695733eeafc6c" title="begin - Return an iterator to the top of the current scheduling region.">begin</a>,
+<a name="l00220"></a>00220 <a class="code" href="classllvm_1_1MachineBasicBlock_1_1bundle__iterator.html">MachineBasicBlock::iterator</a> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#aa1a4554243ad6d8f52e7d12a74f0cded" title="end - Return an iterator to the bottom of the current scheduling region.">end</a>,
+<a name="l00221"></a>00221 <span class="keywordtype">unsigned</span> endcount);
+<a name="l00222"></a>00222 <span class="comment"></span>
+<a name="l00223"></a>00223 <span class="comment"> /// Notify that the scheduler has finished scheduling the current region.</span>
+<a name="l00224"></a>00224 <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#abc5a5c32ac78a99ee2633dbbeec20397" title="Notify that the scheduler has finished scheduling the current region.">exitRegion</a>();
+<a name="l00225"></a>00225 <span class="comment"></span>
+<a name="l00226"></a>00226 <span class="comment"> /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are</span>
+<a name="l00227"></a>00227 <span class="comment"> /// input.</span>
+<a name="l00228"></a>00228 <span class="comment"></span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a10370f5f63c62051d18f1e541cc04029">buildSchedGraph</a>(<a class="code" href="classllvm_1_1AliasAnalysis.html">AliasAnalysis</a> *AA, <a class="code" href="classllvm_1_1RegPressureTracker.html">RegPressureTracker</a> *RPTracker = 0);
+<a name="l00229"></a>00229 <span class="comment"></span>
+<a name="l00230"></a>00230 <span class="comment"> /// addSchedBarrierDeps - Add dependencies from instructions in the current</span>
+<a name="l00231"></a>00231 <span class="comment"> /// list of instructions being scheduled to scheduling barrier. We want to</span>
+<a name="l00232"></a>00232 <span class="comment"> /// make sure instructions which define registers that are either used by</span>
+<a name="l00233"></a>00233 <span class="comment"> /// the terminator or are live-out are properly scheduled. This is</span>
+<a name="l00234"></a>00234 <span class="comment"> /// especially important when the definition latency of the return value(s)</span>
+<a name="l00235"></a>00235 <span class="comment"> /// are too high to be hidden by the branch or when the liveout registers</span>
+<a name="l00236"></a>00236 <span class="comment"> /// used by instructions in the fallthrough block.</span>
+<a name="l00237"></a>00237 <span class="comment"></span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ae8625c1e6c9bc82f2eaef39d3fff65a8">addSchedBarrierDeps</a>();
+<a name="l00238"></a>00238 <span class="comment"></span>
+<a name="l00239"></a>00239 <span class="comment"> /// schedule - Order nodes according to selected style, filling</span>
+<a name="l00240"></a>00240 <span class="comment"> /// in the Sequence member.</span>
+<a name="l00241"></a>00241 <span class="comment"> ///</span>
+<a name="l00242"></a>00242 <span class="comment"> /// Typically, a scheduling algorithm will implement schedule() without</span>
+<a name="l00243"></a>00243 <span class="comment"> /// overriding enterRegion() or exitRegion().</span>
+<a name="l00244"></a>00244 <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#ac0cecc651db330128468e08794794f5c">schedule</a>() = 0;
+<a name="l00245"></a>00245 <span class="comment"></span>
+<a name="l00246"></a>00246 <span class="comment"> /// finalizeSchedule - Allow targets to perform final scheduling actions at</span>
+<a name="l00247"></a>00247 <span class="comment"> /// the level of the whole MachineFunction. By default does nothing.</span>
+<a name="l00248"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a7c30ee6cdef3f4784c192654dcb9bab0">00248</a> <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a7c30ee6cdef3f4784c192654dcb9bab0">finalizeSchedule</a>() {}
+<a name="l00249"></a>00249
+<a name="l00250"></a>00250 <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#acf537095fbdef2feb908f3a2c001d362">dumpNode</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU) <span class="keyword">const</span>;
+<a name="l00251"></a>00251 <span class="comment"></span>
+<a name="l00252"></a>00252 <span class="comment"> /// Return a label for a DAG node that points to an instruction.</span>
+<a name="l00253"></a>00253 <span class="comment"></span> <span class="keyword">virtual</span> std::string <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a27b5f5078e00df5e0692ddfa17b9a342" title="Return a label for a DAG node that points to an instruction.">getGraphNodeLabel</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU) <span class="keyword">const</span>;
+<a name="l00254"></a>00254 <span class="comment"></span>
+<a name="l00255"></a>00255 <span class="comment"> /// Return a label for the region of code covered by the DAG.</span>
+<a name="l00256"></a>00256 <span class="comment"></span> <span class="keyword">virtual</span> std::string <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a29baa8c4f3d0f32140fae1c1a5b9c100" title="Return a label for the region of code covered by the DAG.">getDAGName</a>() <span class="keyword">const</span>;
+<a name="l00257"></a>00257
+<a name="l00258"></a>00258 <span class="keyword">protected</span>:
+<a name="l00259"></a>00259 <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a705a0975de8335b0b6bdbbae165e8f5c">initSUnits</a>();
+<a name="l00260"></a>00260 <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a56fbc3f460289602ce8a51538ebc1e26">addPhysRegDataDeps</a>(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU, <span class="keywordtype">unsigned</span> OperIdx);
+<a name="l00261"></a>00261 <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a2e9425c046cf742bfbb9ebb96466d8e5">addPhysRegDeps</a>(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU, <span class="keywordtype">unsigned</span> OperIdx);
+<a name="l00262"></a>00262 <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a10acc9310a21d9a8191d3d84916bdffb">addVRegDefDeps</a>(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU, <span class="keywordtype">unsigned</span> OperIdx);
+<a name="l00263"></a>00263 <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a0f958ee7dc9902af4093fe8fabbabd6e">addVRegUseDeps</a>(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU, <span class="keywordtype">unsigned</span> OperIdx);
+<a name="l00264"></a>00264 };
+<a name="l00265"></a>00265 <span class="comment"></span>
+<a name="l00266"></a>00266 <span class="comment"> /// newSUnit - Creates a new SUnit and return a ptr to it.</span>
+<a name="l00267"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6c497ec4b863f7d59aa3678740331c8e">00267</a> <span class="comment"></span> <span class="keyword">inline</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6c497ec4b863f7d59aa3678740331c8e" title="newSUnit - Creates a new SUnit and return a ptr to it.">ScheduleDAGInstrs::newSUnit</a>(<a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>) {
+<a name="l00268"></a>00268 <span class="preprocessor">#ifndef NDEBUG</span>
+<a name="l00269"></a>00269 <span class="preprocessor"></span> <span class="keyword">const</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *Addr = <a class="code" href="classllvm_1_1ScheduleDAG.html#a3d5aacd5fc7d6a739ce913974ed1e53d">SUnits</a>.empty() ? 0 : &<a class="code" href="classllvm_1_1ScheduleDAG.html#a3d5aacd5fc7d6a739ce913974ed1e53d">SUnits</a>[0];
+<a name="l00270"></a>00270 <span class="preprocessor">#endif</span>
+<a name="l00271"></a>00271 <span class="preprocessor"></span> <a class="code" href="classllvm_1_1ScheduleDAG.html#a3d5aacd5fc7d6a739ce913974ed1e53d">SUnits</a>.push_back(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a>(MI, (<span class="keywordtype">unsigned</span>)<a class="code" href="classllvm_1_1ScheduleDAG.html#a3d5aacd5fc7d6a739ce913974ed1e53d">SUnits</a>.size()));
+<a name="l00272"></a>00272 assert((Addr == 0 || Addr == &<a class="code" href="classllvm_1_1ScheduleDAG.html#a3d5aacd5fc7d6a739ce913974ed1e53d">SUnits</a>[0]) &&
+<a name="l00273"></a>00273 <span class="stringliteral">"SUnits std::vector reallocated on the fly!"</span>);
+<a name="l00274"></a>00274 <a class="code" href="classllvm_1_1ScheduleDAG.html#a3d5aacd5fc7d6a739ce913974ed1e53d">SUnits</a>.back().OrigNode = &<a class="code" href="classllvm_1_1ScheduleDAG.html#a3d5aacd5fc7d6a739ce913974ed1e53d">SUnits</a>.back();
+<a name="l00275"></a>00275 <span class="keywordflow">return</span> &<a class="code" href="classllvm_1_1ScheduleDAG.html#a3d5aacd5fc7d6a739ce913974ed1e53d">SUnits</a>.back();
+<a name="l00276"></a>00276 }
+<a name="l00277"></a>00277 <span class="comment"></span>
+<a name="l00278"></a>00278 <span class="comment"> /// getSUnit - Return an existing SUnit for this MI, or NULL.</span>
+<a name="l00279"></a><a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6cf6c94d54730c618ac5f86d2140d032">00279</a> <span class="comment"></span> <span class="keyword">inline</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *<a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a6cf6c94d54730c618ac5f86d2140d032" title="getSUnit - Return an existing SUnit for this MI, or NULL.">ScheduleDAGInstrs::getSUnit</a>(<a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>)<span class="keyword"> const </span>{
+<a name="l00280"></a>00280 <a class="code" href="classllvm_1_1DenseMap.html">DenseMap<MachineInstr*, SUnit*>::const_iterator</a> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> = <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a077eef2c61ca462db1800cc506092d38">MISUnitMap</a>.<a class="code" href="classllvm_1_1DenseMapBase.html#a21cf94357e53cd1069aba475266fdb63">find</a>(MI);
+<a name="l00281"></a>00281 <span class="keywordflow">if</span> (I == <a class="code" href="classllvm_1_1ScheduleDAGInstrs.html#a077eef2c61ca462db1800cc506092d38">MISUnitMap</a>.<a class="code" href="classllvm_1_1DenseMapBase.html#a321e37d79af8b4287f8a1dcf9aff9c01">end</a>())
+<a name="l00282"></a>00282 <span class="keywordflow">return</span> 0;
+<a name="l00283"></a>00283 <span class="keywordflow">return</span> I->second;
+<a name="l00284"></a>00284 }
+<a name="l00285"></a>00285 } <span class="comment">// namespace llvm</span>
+<a name="l00286"></a>00286
+<a name="l00287"></a>00287 <span class="preprocessor">#endif</span>
+</pre></div></div>
+</div>
+<hr>
+<p class="footer">
+Generated on Fri Dec 21 2012 00:37:31 for <a href="http://llvm.org/">LLVM</a> by
+<a href="http://www.doxygen.org"><img src="doxygen.png" alt="Doxygen"
+align="middle" border="0"/>1.7.5.1</a><br>
+Copyright © 2003-2012 University of Illinois at Urbana-Champaign.
+All Rights Reserved.</p>
+
+<hr>
+<!--#include virtual="/attrib.incl" -->
+
+</body>
+</html>
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URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.2/docs/doxygen/html/ScheduleDAGPrinter_8cpp__incl.dot?rev=170845&view=auto
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--- www-releases/trunk/3.2/docs/doxygen/html/ScheduleDAGPrinter_8cpp_source.html (added)
+++ www-releases/trunk/3.2/docs/doxygen/html/ScheduleDAGPrinter_8cpp_source.html Fri Dec 21 00:57:24 2012
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+<title>LLVM: ScheduleDAGPrinter.cpp Source File</title>
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+ <li class="navelem"><a class="el" href="dir_74e9364f374e99e3aeab4fae4e196292.html">lib</a> </li>
+ <li class="navelem"><a class="el" href="dir_f2244d21cf8bec63d11bfc1ad661d96f.html">CodeGen</a> </li>
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+<div class="title">ScheduleDAGPrinter.cpp</div> </div>
+</div>
+<div class="contents">
+<a href="ScheduleDAGPrinter_8cpp.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//===-- ScheduleDAGPrinter.cpp - Implement ScheduleDAG::viewGraph() -------===//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This implements the ScheduleDAG::viewGraph method.</span>
+<a name="l00011"></a>00011 <span class="comment">//</span>
+<a name="l00012"></a>00012 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00013"></a>00013
+<a name="l00014"></a>00014 <span class="preprocessor">#include "<a class="code" href="Constants_8h.html">llvm/Constants.h</a>"</span>
+<a name="l00015"></a>00015 <span class="preprocessor">#include "<a class="code" href="Writer_8h.html">llvm/Assembly/Writer.h</a>"</span>
+<a name="l00016"></a>00016 <span class="preprocessor">#include "<a class="code" href="ScheduleDAG_8h.html">llvm/CodeGen/ScheduleDAG.h</a>"</span>
+<a name="l00017"></a>00017 <span class="preprocessor">#include "<a class="code" href="MachineConstantPool_8h.html">llvm/CodeGen/MachineConstantPool.h</a>"</span>
+<a name="l00018"></a>00018 <span class="preprocessor">#include "<a class="code" href="MachineFunction_8h.html">llvm/CodeGen/MachineFunction.h</a>"</span>
+<a name="l00019"></a>00019 <span class="preprocessor">#include "<a class="code" href="MachineModuleInfo_8h.html">llvm/CodeGen/MachineModuleInfo.h</a>"</span>
+<a name="l00020"></a>00020 <span class="preprocessor">#include "<a class="code" href="TargetRegisterInfo_8h.html">llvm/Target/TargetRegisterInfo.h</a>"</span>
+<a name="l00021"></a>00021 <span class="preprocessor">#include "<a class="code" href="Target_2TargetMachine_8h.html">llvm/Target/TargetMachine.h</a>"</span>
+<a name="l00022"></a>00022 <span class="preprocessor">#include "<a class="code" href="Debug_8h.html">llvm/Support/Debug.h</a>"</span>
+<a name="l00023"></a>00023 <span class="preprocessor">#include "<a class="code" href="GraphWriter_8h.html">llvm/Support/GraphWriter.h</a>"</span>
+<a name="l00024"></a>00024 <span class="preprocessor">#include "<a class="code" href="raw__ostream_8h.html">llvm/Support/raw_ostream.h</a>"</span>
+<a name="l00025"></a>00025 <span class="preprocessor">#include "<a class="code" href="DenseSet_8h.html">llvm/ADT/DenseSet.h</a>"</span>
+<a name="l00026"></a>00026 <span class="preprocessor">#include "<a class="code" href="StringExtras_8h.html">llvm/ADT/StringExtras.h</a>"</span>
+<a name="l00027"></a>00027 <span class="preprocessor">#include <fstream></span>
+<a name="l00028"></a>00028 <span class="keyword">using namespace </span>llvm;
+<a name="l00029"></a>00029
+<a name="l00030"></a>00030 <span class="keyword">namespace </span>llvm {
+<a name="l00031"></a>00031 <span class="keyword">template</span><>
+<a name="l00032"></a><a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html">00032</a> <span class="keyword">struct </span><a class="code" href="structllvm_1_1DOTGraphTraits.html">DOTGraphTraits</a><<a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a>*> : <span class="keyword">public</span> <a class="code" href="structllvm_1_1DefaultDOTGraphTraits.html">DefaultDOTGraphTraits</a> {
+<a name="l00033"></a>00033
+<a name="l00034"></a><a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#a4c062906740223f04ca96ab5e852f983">00034</a> <a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#a4c062906740223f04ca96ab5e852f983">DOTGraphTraits</a> (<span class="keywordtype">bool</span> isSimple=<span class="keyword">false</span>) : <a class="code" href="structllvm_1_1DefaultDOTGraphTraits.html">DefaultDOTGraphTraits</a>(isSimple) {}
+<a name="l00035"></a>00035
+<a name="l00036"></a><a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#aa7330a0ffb33a84500a35ce74a559f69">00036</a> <span class="keyword">static</span> std::string <a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#aa7330a0ffb33a84500a35ce74a559f69">getGraphName</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *G) {
+<a name="l00037"></a>00037 <span class="keywordflow">return</span> G-><a class="code" href="classllvm_1_1ScheduleDAG.html#a5a3d3d075a208011a24a0918b58d7daa">MF</a>.<a class="code" href="classllvm_1_1MachineFunction.html#ae215c5c2aecd18c4e68a94187d9cdbf1">getName</a>();
+<a name="l00038"></a>00038 }
+<a name="l00039"></a>00039
+<a name="l00040"></a><a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#a7bbad0bee8894c5c7597ad676cb921ee">00040</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#a7bbad0bee8894c5c7597ad676cb921ee">renderGraphFromBottomUp</a>() {
+<a name="l00041"></a>00041 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00042"></a>00042 }
+<a name="l00043"></a>00043
+<a name="l00044"></a><a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#a6d87ae7ee52521af20051832715ab7f4">00044</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> hasNodeAddressLabel(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *Node,
+<a name="l00045"></a>00045 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *Graph) {
+<a name="l00046"></a>00046 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00047"></a>00047 }
+<a name="l00048"></a>00048 <span class="comment"></span>
+<a name="l00049"></a>00049 <span class="comment"> /// If you want to override the dot attributes printed for a particular</span>
+<a name="l00050"></a>00050 <span class="comment"> /// edge, override this method.</span>
+<a name="l00051"></a><a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#a2d4a3be8f43bead468907b95fba29837">00051</a> <span class="comment"></span> <span class="keyword">static</span> std::string getEdgeAttributes(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *Node,
+<a name="l00052"></a>00052 <a class="code" href="classllvm_1_1SUnitIterator.html">SUnitIterator</a> EI,
+<a name="l00053"></a>00053 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *Graph) {
+<a name="l00054"></a>00054 <span class="keywordflow">if</span> (EI.<a class="code" href="classllvm_1_1SUnitIterator.html#a4be93b75190a68d91960b833832f591f">isArtificialDep</a>())
+<a name="l00055"></a>00055 <span class="keywordflow">return</span> <span class="stringliteral">"color=cyan,style=dashed"</span>;
+<a name="l00056"></a>00056 <span class="keywordflow">if</span> (EI.<a class="code" href="classllvm_1_1SUnitIterator.html#af58adcf012cbcd71cf32c9d50f180c2b" title="isCtrlDep - Test if this is not an SDep::Data dependence.">isCtrlDep</a>())
+<a name="l00057"></a>00057 <span class="keywordflow">return</span> <span class="stringliteral">"color=blue,style=dashed"</span>;
+<a name="l00058"></a>00058 <span class="keywordflow">return</span> <span class="stringliteral">""</span>;
+<a name="l00059"></a>00059 }
+<a name="l00060"></a>00060
+<a name="l00061"></a>00061
+<a name="l00062"></a>00062 std::string getNodeLabel(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *Node, <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *Graph);
+<a name="l00063"></a><a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#a0af913c67e3a0ba5f5756489230c823c">00063</a> <span class="keyword">static</span> std::string getNodeAttributes(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *N,
+<a name="l00064"></a>00064 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *Graph) {
+<a name="l00065"></a>00065 <span class="keywordflow">return</span> <span class="stringliteral">"shape=Mrecord"</span>;
+<a name="l00066"></a>00066 }
+<a name="l00067"></a>00067
+<a name="l00068"></a><a class="code" href="structllvm_1_1DOTGraphTraits_3_01ScheduleDAG_01_5_01_4.html#a5b336bc7481ef590d4619ebfb1dda1d2">00068</a> <span class="keyword">static</span> <span class="keywordtype">void</span> addCustomGraphFeatures(<a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *G,
+<a name="l00069"></a>00069 <a class="code" href="classllvm_1_1GraphWriter.html">GraphWriter<ScheduleDAG*></a> &GW) {
+<a name="l00070"></a>00070 <span class="keywordflow">return</span> G-><a class="code" href="classllvm_1_1ScheduleDAG.html#aba5cd5884386aa82ed66ebd4b44b8fbc">addCustomGraphFeatures</a>(GW);
+<a name="l00071"></a>00071 }
+<a name="l00072"></a>00072 };
+<a name="l00073"></a>00073 }
+<a name="l00074"></a>00074
+<a name="l00075"></a>00075 std::string <a class="code" href="structllvm_1_1DefaultDOTGraphTraits.html#a748e27397b601b36da4ff8689fe1d231">DOTGraphTraits<ScheduleDAG*>::getNodeLabel</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU,
+<a name="l00076"></a>00076 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *G) {
+<a name="l00077"></a>00077 <span class="keywordflow">return</span> G-><a class="code" href="classllvm_1_1ScheduleDAG.html#a2a6534084b1d6332aeb1cf22cba39c2a">getGraphNodeLabel</a>(SU);
+<a name="l00078"></a>00078 }
+<a name="l00079"></a>00079 <span class="comment"></span>
+<a name="l00080"></a>00080 <span class="comment">/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG</span>
+<a name="l00081"></a>00081 <span class="comment">/// rendered using 'dot'.</span>
+<a name="l00082"></a>00082 <span class="comment">///</span>
+<a name="l00083"></a><a class="code" href="classllvm_1_1ScheduleDAG.html#a209b615edbcad3e1a7afd7411ce4eae2">00083</a> <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAG.html#a7e726201ecf499acd7f87ac1d4ff610e" title="Out-of-line implementation with no arguments is handy for gdb.">ScheduleDAG::viewGraph</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1Twine.html">Twine</a> &<a class="code" href="namespacellvm_1_1GraphProgram.html#a0ad4685976f8c4d4a697a53fbe05d10b">Name</a>, <span class="keyword">const</span> <a class="code" href="classllvm_1_1Twine.html">Twine</a> &Title) {
+<a name="l00084"></a>00084 <span class="comment">// This code is only for debugging!</span>
+<a name="l00085"></a>00085 <span class="preprocessor">#ifndef NDEBUG</span>
+<a name="l00086"></a>00086 <span class="preprocessor"></span> <a class="code" href="namespacellvm.html#ab8635363d4287c93f64c55ad5567fcf0">ViewGraph</a>(<span class="keyword">this</span>, Name, <span class="keyword">false</span>, Title);
+<a name="l00087"></a>00087 <span class="preprocessor">#else</span>
+<a name="l00088"></a>00088 <span class="preprocessor"></span> <a class="code" href="namespacellvm.html#ab8e34eca3b0817ef7a127913fbf6d9e4">errs</a>() << <span class="stringliteral">"ScheduleDAG::viewGraph is only available in debug builds on "</span>
+<a name="l00089"></a>00089 << <span class="stringliteral">"systems with Graphviz or gv!\n"</span>;
+<a name="l00090"></a>00090 <span class="preprocessor">#endif // NDEBUG</span>
+<a name="l00091"></a>00091 <span class="preprocessor"></span>}
+<a name="l00092"></a>00092 <span class="comment"></span>
+<a name="l00093"></a>00093 <span class="comment">/// Out-of-line implementation with no arguments is handy for gdb.</span>
+<a name="l00094"></a><a class="code" href="classllvm_1_1ScheduleDAG.html#a7e726201ecf499acd7f87ac1d4ff610e">00094</a> <span class="comment"></span><span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScheduleDAG.html#a7e726201ecf499acd7f87ac1d4ff610e" title="Out-of-line implementation with no arguments is handy for gdb.">ScheduleDAG::viewGraph</a>() {
+<a name="l00095"></a>00095 <a class="code" href="classllvm_1_1ScheduleDAG.html#a7e726201ecf499acd7f87ac1d4ff610e" title="Out-of-line implementation with no arguments is handy for gdb.">viewGraph</a>(<a class="code" href="classllvm_1_1ScheduleDAG.html#a36e088128012e4d48af65feb75f84c5c" title="getDAGLabel - Return a label for the region of code covered by the DAG.">getDAGName</a>(), <span class="stringliteral">"Scheduling-Units Graph for "</span> + <a class="code" href="classllvm_1_1ScheduleDAG.html#a36e088128012e4d48af65feb75f84c5c" title="getDAGLabel - Return a label for the region of code covered by the DAG.">getDAGName</a>());
+<a name="l00096"></a>00096 }
+</pre></div></div>
+</div>
+<hr>
+<p class="footer">
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+<div class="title">ScheduleDAGRRList.cpp File Reference</div> </div>
+</div>
+<div class="contents">
+<div class="textblock"><code>#include "<a class="el" href="ScheduleDAGSDNodes_8h_source.html">ScheduleDAGSDNodes.h</a>"</code><br/>
+<code>#include "<a class="el" href="InlineAsm_8h_source.html">llvm/InlineAsm.h</a>"</code><br/>
+<code>#include "<a class="el" href="SchedulerRegistry_8h_source.html">llvm/CodeGen/SchedulerRegistry.h</a>"</code><br/>
+<code>#include "<a class="el" href="SelectionDAGISel_8h_source.html">llvm/CodeGen/SelectionDAGISel.h</a>"</code><br/>
+<code>#include "<a class="el" href="ScheduleHazardRecognizer_8h_source.html">llvm/CodeGen/ScheduleHazardRecognizer.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetRegisterInfo_8h_source.html">llvm/Target/TargetRegisterInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="DataLayout_8h_source.html">llvm/DataLayout.h</a>"</code><br/>
+<code>#include "<a class="el" href="Target_2TargetMachine_8h_source.html">llvm/Target/TargetMachine.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetInstrInfo_8h_source.html">llvm/Target/TargetInstrInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetLowering_8h_source.html">llvm/Target/TargetLowering.h</a>"</code><br/>
+<code>#include "<a class="el" href="SmallSet_8h_source.html">llvm/ADT/SmallSet.h</a>"</code><br/>
+<code>#include "<a class="el" href="Statistic_8h_source.html">llvm/ADT/Statistic.h</a>"</code><br/>
+<code>#include "<a class="el" href="STLExtras_8h_source.html">llvm/ADT/STLExtras.h</a>"</code><br/>
+<code>#include "<a class="el" href="Debug_8h_source.html">llvm/Support/Debug.h</a>"</code><br/>
+<code>#include "<a class="el" href="ErrorHandling_8h_source.html">llvm/Support/ErrorHandling.h</a>"</code><br/>
+<code>#include "<a class="el" href="raw__ostream_8h_source.html">llvm/Support/raw_ostream.h</a>"</code><br/>
+<code>#include <climits></code><br/>
+</div><div class="textblock"><div class="dynheader">
+Include dependency graph for ScheduleDAGRRList.cpp:</div>
+<div class="dyncontent">
+<div class="center"><img src="ScheduleDAGRRList_8cpp__incl.png" border="0" usemap="#ScheduleDAGRRList_8cpp" alt=""/></div>
+<!-- MAP 0 -->
+</div>
+</div>
+<p><a href="ScheduleDAGRRList_8cpp_source.html">Go to the source code of this file.</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#ad78e062f62e0d6e453941fb4ca843e4d">DEBUG_TYPE</a> "pre-RA-sched"</td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#aa87be6582ac4eb720bef4f470b961fa7">STATISTIC</a> (NumBacktracks,"Number of times scheduler backtracked")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a94495d11764770cad6f4aee2dc4d5ff2">STATISTIC</a> (NumUnfolds,"Number of nodes unfolded")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a44f1fe729677cf1e43d92b5be08aabb4">STATISTIC</a> (NumDups,"Number of duplicated nodes")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a7650464deed5bf68b5f07faac00a780a">STATISTIC</a> (NumPRCopies,"Number of physical register copies")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a75eb4d99ebf26777f16034567505166b">GetCostForDef</a> (const <a class="el" href="classllvm_1_1ScheduleDAGSDNodes_1_1RegDefIter.html">ScheduleDAGSDNodes::RegDefIter</a> &RegDefPos, const <a class="el" href="classllvm_1_1TargetLowering.html">TargetLowering</a> *TLI, const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII, const <a class="el" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI, <a class="el" href="classunsigned.html">unsigned</a> &RegClass, <a class="el" href="classunsigned.html">unsigned</a> &Cost, const <a class="el" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a1bf4053dbca77629ac65f4039a774fae">IsChainDependent</a> (<a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *Outer, <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *Inner, <a class="el" href="classunsigned.html">unsigned</a> NestLevel, const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a8b52e2dd5ab911c1f8d335fbd16e7efc">FindCallSeqStart</a> (<a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="el" href="classunsigned.html">unsigned</a> &NestLevel, <a class="el" href="classunsigned.html">unsigned</a> &MaxNest, const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a420129a3b8db368bc6768ddb7293255d">resetVRegCycle</a> (<a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#aa405be8f26bc0ffcd089589d15327400">isOperandOf</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU, <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *N)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="structllvm_1_1EVT.html">EVT</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a82b61d7e5d7b593cf7c07af84805448a">getPhysicalRegisterVT</a> (<a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>, const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a17664e0274603fb0fded2fda75d5c473">CheckForLiveRegDef</a> (<a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU, <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>, std::vector< <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * > &LiveRegDefs, <a class="el" href="classllvm_1_1SmallSet.html">SmallSet</a>< <a class="el" href="classunsigned.html">unsigned</a>, 4 > &RegAdded, <a class="el" href="classllvm_1_1SmallVector.html">SmallVector</a>< <a class="el" href="classunsigned.html">unsigned</a>, 4 > &LRegs, const <a class="el" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a9b850a4c5f419dab6cd4068676e3e838">CheckForLiveRegDefMasked</a> (<a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU, const uint32_t *RegMask, std::vector< <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * > &LiveRegDefs, <a class="el" href="classllvm_1_1SmallSet.html">SmallSet</a>< <a class="el" href="classunsigned.html">unsigned</a>, 4 > &RegAdded, <a class="el" href="classllvm_1_1SmallVector.html">SmallVector</a>< <a class="el" href="classunsigned.html">unsigned</a>, 4 > &LRegs)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static const uint32_t * </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#aef20d4ef80e5b83336663bd196754e33">getNodeRegMask</a> (const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *N)</td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight">getNodeRegMask - Returns the register mask attached to an SDNode, if any. <a href="#aef20d4ef80e5b83336663bd196754e33"></a><br/></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#ac49ea8879ebf41e521f4f48838e17b6c">checkSpecialNodes</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *left, const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *right)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classunsigned.html">unsigned</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#af1dbaf0e42fc61259e10468caeb7f4b5">CalcNodeSethiUllmanNumber</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU, std::vector< <a class="el" href="classunsigned.html">unsigned</a> > &SUNumbers)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classunsigned.html">unsigned</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#addc8ecda6f7aec38ce2769862c04eb0f">closestSucc</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classunsigned.html">unsigned</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#af07e92d835d198619f6f5c1afd59bd8a">calcMaxScratches</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a16fdb3e37daf197199709a37540402d0">hasOnlyLiveInOpers</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a22c99596004378b139e9ab48fae048dc">hasOnlyLiveOutUses</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a91d04d52105b5c8ba8626a9a64bffc61">initVRegCycle</a> (<a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#ae9a23658447d6c412d2a47f78b465016">hasVRegCycleUse</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a8127bf55bc75e880ae5830edbebf065d">BUHasStall</a> (<a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU, int Height, RegReductionPQBase *SPQ)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static int </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#af872650583e3ccb09205d6a9832026b2">BUCompareLatency</a> (<a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *left, <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *right, <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> checkPref, RegReductionPQBase *SPQ)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a7c9777fccc67ab82fb3d6067611ba1c2">BURRSort</a> (<a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *left, <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *right, RegReductionPQBase *SPQ)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a07e9d7ff453553fd3e5e64c9d93d5d07">canEnableCoalescing</a> (<a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a533e8228c87838f5c738d087a8512fa1">canClobberReachingPhysRegUse</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *DepSU, const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU, ScheduleDAGRRList *scheduleDAG, const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII, const <a class="el" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a6a91ff524836d3fca6cabe37c8fb7dc5">canClobberPhysRegDefs</a> (const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SuccSU, const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> *SU, const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> *TII, const <a class="el" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI)</td></tr>
+<tr><td colspan="2"><h2><a name="var-members"></a>
+Variables</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#aa0d79047118f41e38751305ccce2b928">burrListDAGScheduler</a> ("list-burr","Bottom-up register reduction list scheduling", createBURRListDAGScheduler)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#ab095f9317d3e38ae6d2850d421827bef">sourceListDAGScheduler</a> ("source","Similar to list-burr but schedules in source ""order when possible", createSourceListDAGScheduler)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a12de4541484874827ac7bbe4c4ef2f31">hybridListDAGScheduler</a> ("list-hybrid","Bottom-up register pressure aware list scheduling ""which tries to balance latency and register pressure", createHybridListDAGScheduler)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#ac7bc435596a05626cb965a74b49ee0b8">ILPListDAGScheduler</a> ("list-ilp","Bottom-up register pressure aware list scheduling ""which tries to balance ILP and register pressure", createILPListDAGScheduler)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#aba9f86f38dcf5ed3a21d4d0574c468eb">DisableSchedCycles</a> ("disable-sched-cycles", cl::Hidden, cl::init(<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable cycle-level precision during preRA scheduling"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a8e3abf3dd5834c82a26255b17ff13aa4">DisableSchedRegPressure</a> ("disable-sched-reg-pressure", cl::Hidden, cl::init(<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable regpressure priority in sched=list-ilp"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a03c324c0df33f17173f929db182c106f">DisableSchedLiveUses</a> ("disable-sched-live-uses", cl::Hidden, cl::init(<a class="el" href="LoopSimplify_8cpp.html#a13f020c6a40eb04f1b4f9ddfbb004ce0">true</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable live use priority in sched=list-ilp"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#ad459318e5f05feb310655a5a52ddcf07">DisableSchedVRegCycle</a> ("disable-sched-vrcycle", cl::Hidden, cl::init(<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable virtual register cycle interference checks"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#af49b96c6cca1c8f1378366ab5c4e2efb">DisableSchedPhysRegJoin</a> ("disable-sched-physreg-join", cl::Hidden, cl::init(<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable physreg def-use affinity"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#add5a6e8aa23b184657052b6b1747cb22">DisableSchedStalls</a> ("disable-sched-stalls", cl::Hidden, cl::init(<a class="el" href="LoopSimplify_8cpp.html#a13f020c6a40eb04f1b4f9ddfbb004ce0">true</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable no-stall priority in sched=list-ilp"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#af309d3baca21a07e883cb8e6daa1fccc">DisableSchedCriticalPath</a> ("disable-sched-critical-path", cl::Hidden, cl::init(<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable critical path priority in sched=list-ilp"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a5d782823a03fa1138d9f5b427721c868">DisableSchedHeight</a> ("disable-sched-height", cl::Hidden, cl::init(<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable scheduled-height priority in sched=list-ilp"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a3710fd8a30c5e1ac35c80af278dd1677">Disable2AddrHack</a> ("disable-2addr-hack", cl::Hidden, cl::init(true), cl::desc("Disable scheduler's two-address hack"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< int > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a3b70fc7083c7c1b618e5ead164f0a579">MaxReorderWindow</a> ("max-sched-reorder", cl::Hidden, cl::init(6), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Number of <a class="el" href="SimplifyInstructions_8cpp.html#afbf38da490ab8cea559fee0c9081db06">instructions</a> to allow ahead of the critical path ""in sched=list-ilp"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="classunsigned.html">unsigned</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="ScheduleDAGRRList_8cpp.html#a6b893be58b99aa6a21d18351761159f0">AvgIPC</a> ("sched-avg-ipc", cl::Hidden, cl::init(1), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Average inst/cycle whan no target itinerary exists."))</td></tr>
+</table>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="ad78e062f62e0d6e453941fb4ca843e4d"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DEBUG_TYPE" ref="ad78e062f62e0d6e453941fb4ca843e4d" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define DEBUG_TYPE "pre-RA-sched"</td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l00018">18</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="af872650583e3ccb09205d6a9832026b2"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::BUCompareLatency" ref="af872650583e3ccb09205d6a9832026b2" args="(SUnit *left, SUnit *right, bool checkPref, RegReductionPQBase *SPQ)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int BUCompareLatency </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>left</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>right</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td>
+ <td class="paramname"><em>checkPref</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">RegReductionPQBase * </td>
+ <td class="paramname"><em>SPQ</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02306">2306</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02296">BUHasStall()</a>, <a class="el" href="Debug_8cpp_source.html#l00101">llvm::dbgs()</a>, <a class="el" href="Debug_8h_source.html#l00097">DEBUG</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00384">llvm::SUnit::getDepth()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00392">llvm::SUnit::getHeight()</a>, <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02276">hasVRegCycleUse()</a>, <a class="el" href="TargetLowering_8h_source.html#l00066">llvm::Sched::ILP</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00271">llvm::SUnit::Latency</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00264">llvm::SUnit::NodeNum</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00285">llvm::SUnit::SchedulingPref</a>.</p>
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02357">BURRSort()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a8127bf55bc75e880ae5830edbebf065d"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::BUHasStall" ref="a8127bf55bc75e880ae5830edbebf065d" args="(SUnit *SU, int Height, RegReductionPQBase *SPQ)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> BUHasStall </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">int </td>
+ <td class="paramname"><em>Height</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">RegReductionPQBase * </td>
+ <td class="paramname"><em>SPQ</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02296">2296</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="ScheduleHazardRecognizer_8h_source.html#l00038">llvm::ScheduleHazardRecognizer::NoHazard</a>.</p>
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02306">BUCompareLatency()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a7c9777fccc67ab82fb3d6067611ba1c2"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::BURRSort" ref="a7c9777fccc67ab82fb3d6067611ba1c2" args="(SUnit *left, SUnit *right, RegReductionPQBase *SPQ)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> BURRSort </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>left</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>right</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">RegReductionPQBase * </td>
+ <td class="paramname"><em>SPQ</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02357">2357</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02306">BUCompareLatency()</a>, <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02174">calcMaxScratches()</a>, <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02155">closestSucc()</a>, <a class="el" href="Debug_8cpp_source.html#l00101">llvm::dbgs()</a>, <a class="el" href="Debug_8h_source.html#l00097">DEBUG</a>, <a class="el" href="ScheduleDAGRRList_8cpp.html#aba9f86f38dcf5ed3a21d4d0574c468eb">DisableSchedCycles</a>, <a class="el" href="ScheduleDAGRRList_8cpp.html#af49b96c6cca1c8f1378366ab5c4e2efb">DisableSchedPhysRegJoin</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00384">llvm::SUnit::getDepth()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00392">llvm::SUnit::getHeight()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00349">llvm::SUnit::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00589">llvm::SDNode::getNumValues()</a>, <a class="el" href="Sche
duleDAG_8h_source.html#l00277">llvm::SUnit::hasPhysRegDefs</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00273">llvm::SUnit::isCall</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00274">llvm::SUnit::isCallOp</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00264">llvm::SUnit::NodeNum</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00265">llvm::SUnit::NodeQueueId</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="af07e92d835d198619f6f5c1afd59bd8a"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::calcMaxScratches" ref="af07e92d835d198619f6f5c1afd59bd8a" args="(const SUnit *SU)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="classunsigned.html">unsigned</a> calcMaxScratches </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>calcMaxScratches - Returns an cost estimate of the worse case requirement for scratch registers, i.e. number of data dependencies. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02174">2174</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00256">llvm::SUnit::Preds</a>.</p>
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02357">BURRSort()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="af1dbaf0e42fc61259e10468caeb7f4b5"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::CalcNodeSethiUllmanNumber" ref="af1dbaf0e42fc61259e10468caeb7f4b5" args="(const SUnit *SU, std::vector< unsigned > &SUNumbers)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="classunsigned.html">unsigned</a> CalcNodeSethiUllmanNumber </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">std::vector< <a class="el" href="classunsigned.html">unsigned</a> > & </td>
+ <td class="paramname"><em>SUNumbers</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>CalcNodeSethiUllmanNumber - Compute Sethi Ullman number. Smaller number is the higher priority. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l01804">1804</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00264">llvm::SUnit::NodeNum</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00256">llvm::SUnit::Preds</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a6a91ff524836d3fca6cabe37c8fb7dc5"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::canClobberPhysRegDefs" ref="a6a91ff524836d3fca6cabe37c8fb7dc5" args="(const SUnit *SuccSU, const SUnit *SU, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> canClobberPhysRegDefs </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SuccSU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> * </td>
+ <td class="paramname"><em>TII</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> * </td>
+ <td class="paramname"><em>TRI</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>canClobberPhysRegDefs - True if SU would clobber one of SuccSU's physical register defs. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02708">2708</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="MachineOperand_8h_source.html#l00458">llvm::MachineOperand::clobbersPhysReg()</a>, <a class="el" href="MCInstrInfo_8h_source.html#l00048">llvm::MCInstrInfo::get()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00554">llvm::SDNode::getGluedNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00383">llvm::SDNode::getMachineOpcode()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00349">llvm::SUnit::getNode()</a>, <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l01222">getNodeRegMask()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00589">llvm::SDNode::getNumValues()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00593">llvm::SDNode::getValueType()</a>, <a class="el" href="ValueTypes_8h_source.html#l00100">llvm::MVT::Glue</a>, <a class="el" href="SelectionDAG_8cpp_source.html#l05852">llvm::SDNode::hasAnyUseOfValue()</a>, <a class="el" href="ValueTypes_8h_source.html#l00038">llvm::MVT:
:Other</a>, and <a class="el" href="TargetRegisterInfo_8h_source.html#l00366">llvm::TargetRegisterInfo::regsOverlap()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a533e8228c87838f5c738d087a8512fa1"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::canClobberReachingPhysRegUse" ref="a533e8228c87838f5c738d087a8512fa1" args="(const SUnit *DepSU, const SUnit *SU, ScheduleDAGRRList *scheduleDAG, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> canClobberReachingPhysRegUse </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>DepSU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">ScheduleDAGRRList * </td>
+ <td class="paramname"><em>scheduleDAG</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> * </td>
+ <td class="paramname"><em>TII</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> * </td>
+ <td class="paramname"><em>TRI</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>canClobberReachingPhysRegUse - True if SU would clobber one of it's successor's explicit physregs whose definition can reach DepSU. i.e. DepSU should not be scheduled above SU. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02671">2671</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="MachineOperand_8h_source.html#l00458">llvm::MachineOperand::clobbersPhysReg()</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="MCInstrInfo_8h_source.html#l00048">llvm::MCInstrInfo::get()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00383">llvm::SDNode::getMachineOpcode()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00349">llvm::SUnit::getNode()</a>, <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l01222">getNodeRegMask()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00256">llvm::SUnit::Preds</a>, <a class="el" href="TargetRegisterInfo_8h_source.html#l00366">llvm::TargetRegisterInfo::regsOverlap()</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00257">llvm::SUnit::Succs</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a07e9d7ff453553fd3e5e64c9d93d5d07"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::canEnableCoalescing" ref="a07e9d7ff453553fd3e5e64c9d93d5d07" args="(SUnit *SU)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> canEnableCoalescing </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02544">2544</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="ISDOpcodes_8h_source.html#l00158">llvm::ISD::CopyToReg</a>, <a class="el" href="TargetOpcodes_8h_source.html#l00041">llvm::TargetOpcode::EXTRACT_SUBREG</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00349">llvm::SUnit::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>, <a class="el" href="TargetOpcodes_8h_source.html#l00049">llvm::TargetOpcode::INSERT_SUBREG</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00266">llvm::SUnit::NumPreds</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00267">llvm::SUnit::NumSuccs</a>, <a class="el" href="TargetOpcodes_8h_source.html#l00058">llvm::TargetOpcode::SUBREG_TO_REG</a>, and <a class="el" href="ISDOpcodes_8h_source.html#l00050">llvm::ISD::TokenFactor</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a17664e0274603fb0fded2fda75d5c473"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::CheckForLiveRegDef" ref="a17664e0274603fb0fded2fda75d5c473" args="(SUnit *SU, unsigned Reg, std::vector< SUnit * > &LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVector< unsigned, 4 > &LRegs, const TargetRegisterInfo *TRI)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CheckForLiveRegDef </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>Reg</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">std::vector< <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * > & </td>
+ <td class="paramname"><em>LiveRegDefs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallSet.html">SmallSet</a>< <a class="el" href="classunsigned.html">unsigned</a>, 4 > & </td>
+ <td class="paramname"><em>RegAdded</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallVector.html">SmallVector</a>< <a class="el" href="classunsigned.html">unsigned</a>, 4 > & </td>
+ <td class="paramname"><em>LRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> * </td>
+ <td class="paramname"><em>TRI</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>CheckForLiveRegDef - Return true and update live register vector if the specified register def of the specified SUnit clobbers any "live" registers. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l01185">1185</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallSet_8h_source.html#l00058">llvm::SmallSet< T, N, C >::insert()</a>, <a class="el" href="MCRegisterInfo_8h_source.html#l00207">llvm::MCRegisterInfo::DiffListIterator::isValid()</a>, and <a class="el" href="SmallVector_8h_source.html#l00231">llvm::SmallVectorTemplateBase< T, isPodLike >::push_back()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a9b850a4c5f419dab6cd4068676e3e838"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::CheckForLiveRegDefMasked" ref="a9b850a4c5f419dab6cd4068676e3e838" args="(SUnit *SU, const uint32_t *RegMask, std::vector< SUnit * > &LiveRegDefs, SmallSet< unsigned, 4 > &RegAdded, SmallVector< unsigned, 4 > &LRegs)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CheckForLiveRegDefMasked </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const uint32_t * </td>
+ <td class="paramname"><em>RegMask</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">std::vector< <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * > & </td>
+ <td class="paramname"><em>LiveRegDefs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallSet.html">SmallSet</a>< <a class="el" href="classunsigned.html">unsigned</a>, 4 > & </td>
+ <td class="paramname"><em>RegAdded</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallVector.html">SmallVector</a>< <a class="el" href="classunsigned.html">unsigned</a>, 4 > & </td>
+ <td class="paramname"><em>LRegs</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>CheckForLiveRegDefMasked - Check for any live physregs that are clobbered by RegMask, and add them to LRegs. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l01207">1207</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="MachineOperand_8h_source.html#l00458">llvm::MachineOperand::clobbersPhysReg()</a>, <a class="el" href="SmallSet_8h_source.html#l00058">llvm::SmallSet< T, N, C >::insert()</a>, and <a class="el" href="SmallVector_8h_source.html#l00231">llvm::SmallVectorTemplateBase< T, isPodLike >::push_back()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ac49ea8879ebf41e521f4f48838e17b6c"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::checkSpecialNodes" ref="ac49ea8879ebf41e521f4f48838e17b6c" args="(const SUnit *left, const SUnit *right)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int checkSpecialNodes </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>left</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>right</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l01793">1793</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="ScheduleDAG_8h_source.html#l00283">llvm::SUnit::isScheduleLow</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="addc8ecda6f7aec38ce2769862c04eb0f"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::closestSucc" ref="addc8ecda6f7aec38ce2769862c04eb0f" args="(const SUnit *SU)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="classunsigned.html">unsigned</a> closestSucc </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>closestSucc - Returns the scheduled cycle of the successor which is closest to the current cycle. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02155">2155</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00158">llvm::ISD::CopyToReg</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00257">llvm::SUnit::Succs</a>.</p>
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02357">BURRSort()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a8b52e2dd5ab911c1f8d335fbd16e7efc"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::FindCallSeqStart" ref="a8b52e2dd5ab911c1f8d335fbd16e7efc" args="(SDNode *N, unsigned &NestLevel, unsigned &MaxNest, const TargetInstrInfo *TII)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="classllvm_1_1SDNode.html">SDNode</a>* FindCallSeqStart </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>NestLevel</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MaxNest</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> * </td>
+ <td class="paramname"><em>TII</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>FindCallSeqStart - Starting from the (lowered) CALLSEQ_END node, locate the corresponding (lowered) CALLSEQ_BEGIN node.</p>
+<p>NestLevel and MaxNested are used in recursion to indcate the current level of nesting of CALLSEQ_BEGIN and CALLSEQ_END pairs, as well as the maximum level seen so far.</p>
+<p>TODO: It would be better to give CALLSEQ_END an explicit operand to point to the corresponding CALLSEQ_BEGIN to avoid needing to search for it. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l00438">438</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="ISDOpcodes_8h_source.html#l00045">llvm::ISD::EntryToken</a>, <a class="el" href="TargetInstrInfo_8h_source.html#l00105">llvm::TargetInstrInfo::getCallFrameDestroyOpcode()</a>, <a class="el" href="TargetInstrInfo_8h_source.html#l00104">llvm::TargetInstrInfo::getCallFrameSetupOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00383">llvm::SDNode::getMachineOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">llvm::SDValue::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00532">llvm::SDNode::getNumOperands()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00774">llvm::SDValue::getValueType()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00378">llvm::SDNode::isMachineOpcode()</a>,
<a class="el" href="ValueTypes_8h_source.html#l00038">llvm::MVT::Other</a>, and <a class="el" href="ISDOpcodes_8h_source.html#l00050">llvm::ISD::TokenFactor</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a75eb4d99ebf26777f16034567505166b"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::GetCostForDef" ref="a75eb4d99ebf26777f16034567505166b" args="(const ScheduleDAGSDNodes::RegDefIter &RegDefPos, const TargetLowering *TLI, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, unsigned &RegClass, unsigned &Cost, const MachineFunction &MF)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void GetCostForDef </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1ScheduleDAGSDNodes_1_1RegDefIter.html">ScheduleDAGSDNodes::RegDefIter</a> & </td>
+ <td class="paramname"><em>RegDefPos</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetLowering.html">TargetLowering</a> * </td>
+ <td class="paramname"><em>TLI</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> * </td>
+ <td class="paramname"><em>TII</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> * </td>
+ <td class="paramname"><em>TRI</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>RegClass</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>Cost</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1MachineFunction.html">MachineFunction</a> & </td>
+ <td class="paramname"><em>MF</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>GetCostForDef - Looks up the register class and cost for a given definition. Typically this just means looking up the representative register class, but for untyped values (MVT::Untyped) it means inspecting the node's opcode to determine what register class is being generated. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l00265">265</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="MCInstrInfo_8h_source.html#l00048">llvm::MCInstrInfo::get()</a>, <a class="el" href="TargetRegisterInfo_8h_source.html#l00052">llvm::TargetRegisterClass::getID()</a>, <a class="el" href="ScheduleDAGSDNodes_8h_source.html#l00153">llvm::ScheduleDAGSDNodes::RegDefIter::GetIdx()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00383">llvm::SDNode::getMachineOpcode()</a>, <a class="el" href="ScheduleDAGSDNodes_8h_source.html#l00149">llvm::ScheduleDAGSDNodes::RegDefIter::GetNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="TargetInstrInfo_8cpp_source.html#l00034">llvm::TargetInstrInfo::getRegClass()</a>, <a class="el" href="TargetRegisterInfo_8h_source.html#l00546">llvm::TargetRegisterInfo::getRegClass()</a>, <a class="el" href="TargetLowering_8h_source.html#l00250">llvm::TargetLowering::getRepRegClassCostFor()</a>, <a class="el" href="TargetLowering_8h_source.htm
l#l00242">llvm::TargetLowering::getRepRegClassFor()</a>, <a class="el" href="ScheduleDAGSDNodes_8h_source.html#l00144">llvm::ScheduleDAGSDNodes::RegDefIter::GetValue()</a>, <a class="el" href="TargetOpcodes_8h_source.html#l00081">llvm::TargetOpcode::REG_SEQUENCE</a>, and <a class="el" href="ValueTypes_8h_source.html#l00104">llvm::MVT::Untyped</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="aef20d4ef80e5b83336663bd196754e33"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::getNodeRegMask" ref="aef20d4ef80e5b83336663bd196754e33" args="(const SDNode *N)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static const uint32_t* getNodeRegMask </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>getNodeRegMask - Returns the register mask attached to an SDNode, if any. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l01222">1222</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">llvm::SDValue::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00532">llvm::SDNode::getNumOperands()</a>, and <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>.</p>
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02708">canClobberPhysRegDefs()</a>, and <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02671">canClobberReachingPhysRegUse()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a82b61d7e5d7b593cf7c07af84805448a"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::getPhysicalRegisterVT" ref="a82b61d7e5d7b593cf7c07af84805448a" args="(SDNode *N, unsigned Reg, const TargetInstrInfo *TII)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="structllvm_1_1EVT.html">EVT</a> getPhysicalRegisterVT </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>Reg</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> * </td>
+ <td class="paramname"><em>TII</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>getPhysicalRegisterVT - Returns the ValueType of the physical register definition of the specified node. FIXME: Move to SelectionDAG? </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l01170">1170</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="MCInstrInfo_8h_source.html#l00048">llvm::MCInstrInfo::get()</a>, <a class="el" href="MCInstrDesc_8h_source.html#l00481">llvm::MCInstrDesc::getImplicitDefs()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00383">llvm::SDNode::getMachineOpcode()</a>, <a class="el" href="MCInstrDesc_8h_source.html#l00177">llvm::MCInstrDesc::getNumDefs()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00593">llvm::SDNode::getValueType()</a>, and <a class="el" href="MCInstrDesc_8h_source.html#l00144">llvm::MCInstrDesc::ImplicitDefs</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a16fdb3e37daf197199709a37540402d0"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::hasOnlyLiveInOpers" ref="a16fdb3e37daf197199709a37540402d0" args="(const SUnit *SU)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> hasOnlyLiveInOpers </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>hasOnlyLiveInOpers - Return true if SU has only value predecessors that are CopyFromReg from a virtual register. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02186">2186</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00163">llvm::ISD::CopyFromReg</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00349">llvm::SUnit::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="MipsDisassembler_8cpp_source.html#l00330">getReg()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, <a class="el" href="TargetRegisterInfo_8h_source.html#l00284">llvm::TargetRegisterInfo::isVirtualRegister()</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00256">llvm::SUnit::Preds</a>.</p>
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02238">initVRegCycle()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a22c99596004378b139e9ab48fae048dc"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::hasOnlyLiveOutUses" ref="a22c99596004378b139e9ab48fae048dc" args="(const SUnit *SU)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> hasOnlyLiveOutUses </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>hasOnlyLiveOutUses - Return true if SU has only value successors that are CopyToReg to a virtual register. This SU def is probably a liveout and it has no other use. It should be scheduled closer to the terminator. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02209">2209</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00158">llvm::ISD::CopyToReg</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00349">llvm::SUnit::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="MipsDisassembler_8cpp_source.html#l00330">getReg()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, <a class="el" href="TargetRegisterInfo_8h_source.html#l00284">llvm::TargetRegisterInfo::isVirtualRegister()</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00257">llvm::SUnit::Succs</a>.</p>
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02238">initVRegCycle()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ae9a23658447d6c412d2a47f78b465016"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::hasVRegCycleUse" ref="ae9a23658447d6c412d2a47f78b465016" args="(const SUnit *SU)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> hasVRegCycleUse </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02276">2276</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00163">llvm::ISD::CopyFromReg</a>, <a class="el" href="Debug_8cpp_source.html#l00101">llvm::dbgs()</a>, <a class="el" href="Debug_8h_source.html#l00097">DEBUG</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00272">llvm::SUnit::isVRegCycle</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00264">llvm::SUnit::NodeNum</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00256">llvm::SUnit::Preds</a>.</p>
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02306">BUCompareLatency()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a91d04d52105b5c8ba8626a9a64bffc61"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::initVRegCycle" ref="a91d04d52105b5c8ba8626a9a64bffc61" args="(SUnit *SU)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void initVRegCycle </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02238">2238</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="Debug_8cpp_source.html#l00101">llvm::dbgs()</a>, <a class="el" href="Debug_8h_source.html#l00097">DEBUG</a>, <a class="el" href="ScheduleDAGRRList_8cpp.html#ad459318e5f05feb310655a5a52ddcf07">DisableSchedVRegCycle</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02186">hasOnlyLiveInOpers()</a>, <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02209">hasOnlyLiveOutUses()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00272">llvm::SUnit::isVRegCycle</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00264">llvm::SUnit::NodeNum</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00256">llvm::SUnit::
Preds</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a1bf4053dbca77629ac65f4039a774fae"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::IsChainDependent" ref="a1bf4053dbca77629ac65f4039a774fae" args="(SDNode *Outer, SDNode *Inner, unsigned NestLevel, const TargetInstrInfo *TII)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> IsChainDependent </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>Outer</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>Inner</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>NestLevel</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> * </td>
+ <td class="paramname"><em>TII</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>IsChainDependent - Test if Outer is reachable from Inner through chain dependencies. </p>
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l00387">387</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="ISDOpcodes_8h_source.html#l00045">llvm::ISD::EntryToken</a>, <a class="el" href="TargetInstrInfo_8h_source.html#l00105">llvm::TargetInstrInfo::getCallFrameDestroyOpcode()</a>, <a class="el" href="TargetInstrInfo_8h_source.html#l00104">llvm::TargetInstrInfo::getCallFrameSetupOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00383">llvm::SDNode::getMachineOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">llvm::SDValue::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00532">llvm::SDNode::getNumOperands()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00774">llvm::SDValue::getValueType()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00378">llvm::SDNode::isMachineOpcode()</a>,
<a class="el" href="ValueTypes_8h_source.html#l00038">llvm::MVT::Other</a>, and <a class="el" href="ISDOpcodes_8h_source.html#l00050">llvm::ISD::TokenFactor</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="aa405be8f26bc0ffcd089589d15327400"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::isOperandOf" ref="aa405be8f26bc0ffcd089589d15327400" args="(const SUnit *SU, SDNode *N)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> isOperandOf </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l00905">905</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGNodes_8h_source.html#l00554">llvm::SDNode::getGluedNode()</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00349">llvm::SUnit::getNode()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a420129a3b8db368bc6768ddb7293255d"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::resetVRegCycle" ref="a420129a3b8db368bc6768ddb7293255d" args="(SUnit *SU)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void resetVRegCycle </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SUnit.html">SUnit</a> * </td>
+ <td class="paramname"><em>SU</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02258">2258</a> of file <a class="el" href="ScheduleDAGRRList_8cpp_source.html">ScheduleDAGRRList.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00163">llvm::ISD::CopyFromReg</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00349">llvm::SUnit::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, <a class="el" href="ScheduleDAG_8h_source.html#l00272">llvm::SUnit::isVRegCycle</a>, and <a class="el" href="ScheduleDAG_8h_source.html#l00256">llvm::SUnit::Preds</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="aa87be6582ac4eb720bef4f470b961fa7"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::STATISTIC" ref="aa87be6582ac4eb720bef4f470b961fa7" args="(NumBacktracks,"Number of times scheduler backtracked")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumBacktracks </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of times scheduler backtracked" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a94495d11764770cad6f4aee2dc4d5ff2"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::STATISTIC" ref="a94495d11764770cad6f4aee2dc4d5ff2" args="(NumUnfolds,"Number of nodes unfolded")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumUnfolds </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of nodes unfolded" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
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+
+</div>
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+ <td>(</td>
+ <td class="paramtype">NumDups </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of duplicated nodes" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a7650464deed5bf68b5f07faac00a780a"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::STATISTIC" ref="a7650464deed5bf68b5f07faac00a780a" args="(NumPRCopies,"Number of physical register copies")" -->
+<div class="memitem">
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of physical register copies" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<hr/><h2>Variable Documentation</h2>
+<a class="anchor" id="a6b893be58b99aa6a21d18351761159f0"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::AvgIPC" ref="a6b893be58b99aa6a21d18351761159f0" args="("sched-avg-ipc", cl::Hidden, cl::init(1), cl::desc("Average inst/cycle whan no target itinerary exists."))" -->
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+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="aa0d79047118f41e38751305ccce2b928"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::burrListDAGScheduler" ref="aa0d79047118f41e38751305ccce2b928" args="("list-burr","Bottom-up register reduction list scheduling", createBURRListDAGScheduler)" -->
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+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a3710fd8a30c5e1ac35c80af278dd1677"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::Disable2AddrHack" ref="a3710fd8a30c5e1ac35c80af278dd1677" args="("disable-2addr-hack", cl::Hidden, cl::init(true), cl::desc("Disable scheduler's two-address hack"))" -->
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+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af309d3baca21a07e883cb8e6daa1fccc"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DisableSchedCriticalPath" ref="af309d3baca21a07e883cb8e6daa1fccc" args="("disable-sched-critical-path", cl::Hidden, cl::init(false), cl::desc("Disable critical path priority in sched=list-ilp"))" -->
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+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="aba9f86f38dcf5ed3a21d4d0574c468eb"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DisableSchedCycles" ref="aba9f86f38dcf5ed3a21d4d0574c468eb" args="("disable-sched-cycles", cl::Hidden, cl::init(false), cl::desc("Disable cycle-level precision during preRA scheduling"))" -->
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+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02357">BURRSort()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a5d782823a03fa1138d9f5b427721c868"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DisableSchedHeight" ref="a5d782823a03fa1138d9f5b427721c868" args="("disable-sched-height", cl::Hidden, cl::init(false), cl::desc("Disable scheduled-height priority in sched=list-ilp"))" -->
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+
+</div>
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+<a class="anchor" id="a03c324c0df33f17173f929db182c106f"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DisableSchedLiveUses" ref="a03c324c0df33f17173f929db182c106f" args="("disable-sched-live-uses", cl::Hidden, cl::init(true), cl::desc("Disable live use priority in sched=list-ilp"))" -->
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+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="ScheduleDAGRRList_8cpp.html#a03c324c0df33f17173f929db182c106f">DisableSchedLiveUses</a>("disable-sched-live-uses", cl::Hidden, cl::init(<a class="el" href="LoopSimplify_8cpp.html#a13f020c6a40eb04f1b4f9ddfbb004ce0">true</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable live use priority in sched=list-ilp"))<code> [static]</code></td>
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+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af49b96c6cca1c8f1378366ab5c4e2efb"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DisableSchedPhysRegJoin" ref="af49b96c6cca1c8f1378366ab5c4e2efb" args="("disable-sched-physreg-join", cl::Hidden, cl::init(false), cl::desc("Disable physreg def-use affinity"))" -->
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+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="ScheduleDAGRRList_8cpp.html#af49b96c6cca1c8f1378366ab5c4e2efb">DisableSchedPhysRegJoin</a>("disable-sched-physreg-join", cl::Hidden, cl::init(<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable physreg def-use affinity"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02357">BURRSort()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a8e3abf3dd5834c82a26255b17ff13aa4"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DisableSchedRegPressure" ref="a8e3abf3dd5834c82a26255b17ff13aa4" args="("disable-sched-reg-pressure", cl::Hidden, cl::init(false), cl::desc("Disable regpressure priority in sched=list-ilp"))" -->
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+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="add5a6e8aa23b184657052b6b1747cb22"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DisableSchedStalls" ref="add5a6e8aa23b184657052b6b1747cb22" args="("disable-sched-stalls", cl::Hidden, cl::init(true), cl::desc("Disable no-stall priority in sched=list-ilp"))" -->
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+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ad459318e5f05feb310655a5a52ddcf07"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::DisableSchedVRegCycle" ref="ad459318e5f05feb310655a5a52ddcf07" args="("disable-sched-vrcycle", cl::Hidden, cl::init(false), cl::desc("Disable virtual register cycle interference checks"))" -->
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+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="ScheduleDAGRRList_8cpp.html#ad459318e5f05feb310655a5a52ddcf07">DisableSchedVRegCycle</a>("disable-sched-vrcycle", cl::Hidden, cl::init(<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Disable virtual register cycle interference checks"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Referenced by <a class="el" href="ScheduleDAGRRList_8cpp_source.html#l02238">initVRegCycle()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a12de4541484874827ac7bbe4c4ef2f31"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::hybridListDAGScheduler" ref="a12de4541484874827ac7bbe4c4ef2f31" args="("list-hybrid","Bottom-up register pressure aware list scheduling ""which tries to balance latency and register pressure", createHybridListDAGScheduler)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> <a class="el" href="ScheduleDAGRRList_8cpp.html#a12de4541484874827ac7bbe4c4ef2f31">hybridListDAGScheduler</a>("list-hybrid","Bottom-up register pressure aware list scheduling ""which tries to balance latency and register pressure", createHybridListDAGScheduler)<code> [static]</code></td>
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+<a class="anchor" id="ac7bc435596a05626cb965a74b49ee0b8"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::ILPListDAGScheduler" ref="ac7bc435596a05626cb965a74b49ee0b8" args="("list-ilp","Bottom-up register pressure aware list scheduling ""which tries to balance ILP and register pressure", createILPListDAGScheduler)" -->
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+<div class="memproto">
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+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> <a class="el" href="ScheduleDAGRRList_8cpp.html#ac7bc435596a05626cb965a74b49ee0b8">ILPListDAGScheduler</a>("list-ilp","Bottom-up register pressure aware list scheduling ""which tries to balance ILP and register pressure", createILPListDAGScheduler)<code> [static]</code></td>
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+<a class="anchor" id="a3b70fc7083c7c1b618e5ead164f0a579"></a><!-- doxytag: member="ScheduleDAGRRList.cpp::MaxReorderWindow" ref="a3b70fc7083c7c1b618e5ead164f0a579" args="("max-sched-reorder", cl::Hidden, cl::init(6), cl::desc("Number of instructions to allow ahead of the critical path ""in sched=list-ilp"))" -->
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+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><int> <a class="el" href="ScheduleDAGRRList_8cpp.html#a3b70fc7083c7c1b618e5ead164f0a579">MaxReorderWindow</a>("max-sched-reorder", cl::Hidden, cl::init(6), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Number of <a class="el" href="SimplifyInstructions_8cpp.html#afbf38da490ab8cea559fee0c9081db06">instructions</a> to allow ahead of the critical path ""in sched=list-ilp"))<code> [static]</code></td>
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+<div class="memitem">
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+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> <a class="el" href="ScheduleDAGRRList_8cpp.html#ab095f9317d3e38ae6d2850d421827bef">sourceListDAGScheduler</a>("source","Similar to list-burr but schedules in source ""order when possible", createSourceListDAGScheduler)<code> [static]</code></td>
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+</div>
+<div class="memdoc">
+
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+<hr>
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+Generated on Fri Dec 21 2012 00:39:40 for <a href="http://llvm.org/">LLVM</a> by
+<a href="http://www.doxygen.org"><img src="doxygen.png" alt="Doxygen"
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+<meta name="keywords" content="LLVM,Low Level Virtual Machine,C++,doxygen,API,documentation"/>
+<meta name="description" content="C++ source code API documentation for LLVM."/>
+<title>LLVM: SchedulerRegistry.h Source File</title>
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+<p class="title">LLVM API Documentation</p>
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+ <li class="navelem"><a class="el" href="dir_b41d254693bea6e92988e5bb1ad97e02.html">llvm-3.2.src</a> </li>
+ <li class="navelem"><a class="el" href="dir_25acc6571c4e3a053ee4203146b47a61.html">include</a> </li>
+ <li class="navelem"><a class="el" href="dir_fd2d7b5ce83b1c1657cd6600d8cb39fa.html">llvm</a> </li>
+ <li class="navelem"><a class="el" href="dir_33f9015af551a3c03ac5a968f2023d57.html">CodeGen</a> </li>
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+ <div class="headertitle">
+<div class="title">SchedulerRegistry.h</div> </div>
+</div>
+<div class="contents">
+<a href="SchedulerRegistry_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file contains the implementation for instruction scheduler function</span>
+<a name="l00011"></a>00011 <span class="comment">// pass registry (RegisterScheduler).</span>
+<a name="l00012"></a>00012 <span class="comment">//</span>
+<a name="l00013"></a>00013 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00014"></a>00014
+<a name="l00015"></a>00015 <span class="preprocessor">#ifndef LLVM_CODEGENSCHEDULERREGISTRY_H</span>
+<a name="l00016"></a>00016 <span class="preprocessor"></span><span class="preprocessor">#define LLVM_CODEGENSCHEDULERREGISTRY_H</span>
+<a name="l00017"></a>00017 <span class="preprocessor"></span>
+<a name="l00018"></a>00018 <span class="preprocessor">#include "<a class="code" href="MachinePassRegistry_8h.html">llvm/CodeGen/MachinePassRegistry.h</a>"</span>
+<a name="l00019"></a>00019 <span class="preprocessor">#include "<a class="code" href="Target_2TargetMachine_8h.html">llvm/Target/TargetMachine.h</a>"</span>
+<a name="l00020"></a>00020
+<a name="l00021"></a>00021 <span class="keyword">namespace </span>llvm {
+<a name="l00022"></a>00022
+<a name="l00023"></a>00023 <span class="comment">//===----------------------------------------------------------------------===//</span><span class="comment"></span>
+<a name="l00024"></a>00024 <span class="comment">///</span>
+<a name="l00025"></a>00025 <span class="comment">/// RegisterScheduler class - Track the registration of instruction schedulers.</span>
+<a name="l00026"></a>00026 <span class="comment">///</span>
+<a name="l00027"></a>00027 <span class="comment"></span><span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00028"></a>00028
+<a name="l00029"></a>00029 <span class="keyword">class </span>SelectionDAGISel;
+<a name="l00030"></a>00030 <span class="keyword">class </span>ScheduleDAGSDNodes;
+<a name="l00031"></a>00031 <span class="keyword">class </span>SelectionDAG;
+<a name="l00032"></a>00032 <span class="keyword">class </span>MachineBasicBlock;
+<a name="l00033"></a>00033
+<a name="l00034"></a><a class="code" href="classllvm_1_1RegisterScheduler.html">00034</a> <span class="keyword">class </span><a class="code" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> : <span class="keyword">public</span> <a class="code" href="classllvm_1_1MachinePassRegistryNode.html">MachinePassRegistryNode</a> {
+<a name="l00035"></a>00035 <span class="keyword">public</span>:
+<a name="l00036"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#a360361b84089ef7c4103152b3c02a40e">00036</a> <span class="keyword">typedef</span> <a class="code" href="classllvm_1_1ScheduleDAGSDNodes.html">ScheduleDAGSDNodes</a> *(*FunctionPassCtor)(<a class="code" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a>*,
+<a name="l00037"></a>00037 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a>);
+<a name="l00038"></a>00038
+<a name="l00039"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#a85302ad32727bfe3c808a9ca17a3dd46">00039</a> <span class="keyword">static</span> <a class="code" href="classllvm_1_1MachinePassRegistry.html">MachinePassRegistry</a> <a class="code" href="classllvm_1_1RegisterScheduler.html#a85302ad32727bfe3c808a9ca17a3dd46">Registry</a>;
+<a name="l00040"></a>00040
+<a name="l00041"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#aa896a0f8a4e3c9084fd9bd98577ef34b">00041</a> <a class="code" href="classllvm_1_1RegisterScheduler.html#aa896a0f8a4e3c9084fd9bd98577ef34b">RegisterScheduler</a>(<span class="keyword">const</span> <span class="keywordtype">char</span> *N, <span class="keyword">const</span> <span class="keywordtype">char</span> *D, <a class="code" href="classllvm_1_1RegisterScheduler.html#a360361b84089ef7c4103152b3c02a40e">FunctionPassCtor</a> <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">C</a>)
+<a name="l00042"></a>00042 : <a class="code" href="classllvm_1_1MachinePassRegistryNode.html">MachinePassRegistryNode</a>(N, D, (<a class="code" href="namespacellvm.html#aea14d5990874fd48048ae77ae39d404e">MachinePassCtor</a>)C)
+<a name="l00043"></a>00043 { <a class="code" href="classllvm_1_1Registry.html">Registry</a>.Add(<span class="keyword">this</span>); }
+<a name="l00044"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#a15382ff57fe459b11d1c08073177622c">00044</a> <a class="code" href="classllvm_1_1RegisterScheduler.html#a15382ff57fe459b11d1c08073177622c">~RegisterScheduler</a>() { <a class="code" href="classllvm_1_1Registry.html">Registry</a>.Remove(<span class="keyword">this</span>); }
+<a name="l00045"></a>00045
+<a name="l00046"></a>00046
+<a name="l00047"></a>00047 <span class="comment">// Accessors.</span>
+<a name="l00048"></a>00048 <span class="comment">//</span>
+<a name="l00049"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#ac3f0ec7cb89340df3f2ef65a02391beb">00049</a> <a class="code" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> *<a class="code" href="classllvm_1_1RegisterScheduler.html#ac3f0ec7cb89340df3f2ef65a02391beb">getNext</a>()<span class="keyword"> const </span>{
+<a name="l00050"></a>00050 <span class="keywordflow">return</span> (<a class="code" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> *)<a class="code" href="classllvm_1_1RegisterScheduler.html#ac3f0ec7cb89340df3f2ef65a02391beb">MachinePassRegistryNode::getNext</a>();
+<a name="l00051"></a>00051 }
+<a name="l00052"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#a92057c04fb62ff768231d099ebaebaf7">00052</a> <span class="keyword">static</span> <a class="code" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> *<a class="code" href="classllvm_1_1RegisterScheduler.html#a92057c04fb62ff768231d099ebaebaf7">getList</a>() {
+<a name="l00053"></a>00053 <span class="keywordflow">return</span> (<a class="code" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> *)<a class="code" href="classllvm_1_1Registry.html">Registry</a>.getList();
+<a name="l00054"></a>00054 }
+<a name="l00055"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#ac22e4155a7381e68c1180117fea35c75">00055</a> <span class="keyword">static</span> <a class="code" href="classllvm_1_1RegisterScheduler.html#a360361b84089ef7c4103152b3c02a40e">FunctionPassCtor</a> <a class="code" href="classllvm_1_1RegisterScheduler.html#ac22e4155a7381e68c1180117fea35c75">getDefault</a>() {
+<a name="l00056"></a>00056 <span class="keywordflow">return</span> (<a class="code" href="classllvm_1_1RegisterScheduler.html#a360361b84089ef7c4103152b3c02a40e">FunctionPassCtor</a>)<a class="code" href="classllvm_1_1Registry.html">Registry</a>.getDefault();
+<a name="l00057"></a>00057 }
+<a name="l00058"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#a40bdb2b1f28b916e0fdcd93453fdfd73">00058</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1RegisterScheduler.html#a40bdb2b1f28b916e0fdcd93453fdfd73">setDefault</a>(<a class="code" href="classllvm_1_1RegisterScheduler.html#a360361b84089ef7c4103152b3c02a40e">FunctionPassCtor</a> <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">C</a>) {
+<a name="l00059"></a>00059 <a class="code" href="classllvm_1_1Registry.html">Registry</a>.setDefault((<a class="code" href="namespacellvm.html#aea14d5990874fd48048ae77ae39d404e">MachinePassCtor</a>)C);
+<a name="l00060"></a>00060 }
+<a name="l00061"></a><a class="code" href="classllvm_1_1RegisterScheduler.html#a94aaef3099ad34ebc53a1f1efc5e89ab">00061</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1RegisterScheduler.html#a94aaef3099ad34ebc53a1f1efc5e89ab">setListener</a>(<a class="code" href="classllvm_1_1MachinePassRegistryListener.html">MachinePassRegistryListener</a> *L) {
+<a name="l00062"></a>00062 <a class="code" href="classllvm_1_1Registry.html">Registry</a>.setListener(L);
+<a name="l00063"></a>00063 }
+<a name="l00064"></a>00064 };
+<a name="l00065"></a>00065 <span class="comment"></span>
+<a name="l00066"></a>00066 <span class="comment">/// createBURRListDAGScheduler - This creates a bottom up register usage</span>
+<a name="l00067"></a>00067 <span class="comment">/// reduction list scheduler.</span>
+<a name="l00068"></a>00068 <span class="comment"></span>ScheduleDAGSDNodes *<a class="code" href="namespacellvm.html#a0cc3c89b31edd11c4e42b6980efcc621">createBURRListDAGScheduler</a>(SelectionDAGISel *IS,
+<a name="l00069"></a>00069 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a> OptLevel);
+<a name="l00070"></a>00070 <span class="comment"></span>
+<a name="l00071"></a>00071 <span class="comment">/// createBURRListDAGScheduler - This creates a bottom up list scheduler that</span>
+<a name="l00072"></a>00072 <span class="comment">/// schedules nodes in source code order when possible.</span>
+<a name="l00073"></a>00073 <span class="comment"></span>ScheduleDAGSDNodes *<a class="code" href="namespacellvm.html#a55abb3ae6bc55ca30625f7a0e28949da">createSourceListDAGScheduler</a>(SelectionDAGISel *IS,
+<a name="l00074"></a>00074 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a> OptLevel);
+<a name="l00075"></a>00075 <span class="comment"></span>
+<a name="l00076"></a>00076 <span class="comment">/// createHybridListDAGScheduler - This creates a bottom up register pressure</span>
+<a name="l00077"></a>00077 <span class="comment">/// aware list scheduler that make use of latency information to avoid stalls</span>
+<a name="l00078"></a>00078 <span class="comment">/// for long latency instructions in low register pressure mode. In high</span>
+<a name="l00079"></a>00079 <span class="comment">/// register pressure mode it schedules to reduce register pressure.</span>
+<a name="l00080"></a>00080 <span class="comment"></span>ScheduleDAGSDNodes *<a class="code" href="namespacellvm.html#acdd401526bdfe6509b2a4aeeb3fbfade">createHybridListDAGScheduler</a>(SelectionDAGISel *IS,
+<a name="l00081"></a>00081 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a>);
+<a name="l00082"></a>00082 <span class="comment"></span>
+<a name="l00083"></a>00083 <span class="comment">/// createILPListDAGScheduler - This creates a bottom up register pressure</span>
+<a name="l00084"></a>00084 <span class="comment">/// aware list scheduler that tries to increase instruction level parallelism</span>
+<a name="l00085"></a>00085 <span class="comment">/// in low register pressure mode. In high register pressure mode it schedules</span>
+<a name="l00086"></a>00086 <span class="comment">/// to reduce register pressure.</span>
+<a name="l00087"></a>00087 <span class="comment"></span>ScheduleDAGSDNodes *<a class="code" href="namespacellvm.html#a19e072bf547248dcd953436ada780ecf">createILPListDAGScheduler</a>(SelectionDAGISel *IS,
+<a name="l00088"></a>00088 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a>);
+<a name="l00089"></a>00089 <span class="comment"></span>
+<a name="l00090"></a>00090 <span class="comment">/// createFastDAGScheduler - This creates a "fast" scheduler.</span>
+<a name="l00091"></a>00091 <span class="comment">///</span>
+<a name="l00092"></a>00092 <span class="comment"></span>ScheduleDAGSDNodes *<a class="code" href="namespacellvm.html#a7eb2ed900a1862a7b7fb2cb0699c6268">createFastDAGScheduler</a>(SelectionDAGISel *IS,
+<a name="l00093"></a>00093 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a> OptLevel);
+<a name="l00094"></a>00094 <span class="comment"></span>
+<a name="l00095"></a>00095 <span class="comment">/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down</span>
+<a name="l00096"></a>00096 <span class="comment">/// DFA driven list scheduler with clustering heuristic to control</span>
+<a name="l00097"></a>00097 <span class="comment">/// register pressure.</span>
+<a name="l00098"></a>00098 <span class="comment"></span>ScheduleDAGSDNodes *<a class="code" href="namespacellvm.html#ac4bf48adb22d4bb44adff9014d0991c9" title="createVLIWDAGScheduler - This creates a top-down list scheduler.">createVLIWDAGScheduler</a>(SelectionDAGISel *IS,
+<a name="l00099"></a>00099 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a> OptLevel);<span class="comment"></span>
+<a name="l00100"></a>00100 <span class="comment">/// createDefaultScheduler - This creates an instruction scheduler appropriate</span>
+<a name="l00101"></a>00101 <span class="comment">/// for the target.</span>
+<a name="l00102"></a>00102 <span class="comment"></span>ScheduleDAGSDNodes *<a class="code" href="namespacellvm.html#a84ca2cbce84944d7c7436be1e81fdc1e">createDefaultScheduler</a>(SelectionDAGISel *IS,
+<a name="l00103"></a>00103 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a> OptLevel);
+<a name="l00104"></a>00104 <span class="comment"></span>
+<a name="l00105"></a>00105 <span class="comment">/// createDAGLinearizer - This creates a "no-scheduling" scheduler which</span>
+<a name="l00106"></a>00106 <span class="comment">/// linearize the DAG using topological order.</span>
+<a name="l00107"></a>00107 <span class="comment"></span>ScheduleDAGSDNodes *<a class="code" href="namespacellvm.html#a3fefd2387b35e834be66f8119254b588">createDAGLinearizer</a>(SelectionDAGISel *IS,
+<a name="l00108"></a>00108 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a> OptLevel);
+<a name="l00109"></a>00109
+<a name="l00110"></a>00110 } <span class="comment">// end namespace llvm</span>
+<a name="l00111"></a>00111
+<a name="l00112"></a>00112 <span class="preprocessor">#endif</span>
+</pre></div></div>
+</div>
+<hr>
+<p class="footer">
+Generated on Fri Dec 21 2012 00:37:32 for <a href="http://llvm.org/">LLVM</a> by
+<a href="http://www.doxygen.org"><img src="doxygen.png" alt="Doxygen"
+align="middle" border="0"/>1.7.5.1</a><br>
+Copyright © 2003-2012 University of Illinois at Urbana-Champaign.
+All Rights Reserved.</p>
+
+<hr>
+<!--#include virtual="/attrib.incl" -->
+
+</body>
+</html>
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--- www-releases/trunk/3.2/docs/doxygen/html/ScopedHashTable_8h_source.html (added)
+++ www-releases/trunk/3.2/docs/doxygen/html/ScopedHashTable_8h_source.html Fri Dec 21 00:57:24 2012
@@ -0,0 +1,312 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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+<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"/>
+<meta name="keywords" content="LLVM,Low Level Virtual Machine,C++,doxygen,API,documentation"/>
+<meta name="description" content="C++ source code API documentation for LLVM."/>
+<title>LLVM: ScopedHashTable.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head><body>
+<p class="title">LLVM API Documentation</p>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>File Members</span></a></li>
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+ <li class="navelem"><a class="el" href="dir_b41d254693bea6e92988e5bb1ad97e02.html">llvm-3.2.src</a> </li>
+ <li class="navelem"><a class="el" href="dir_25acc6571c4e3a053ee4203146b47a61.html">include</a> </li>
+ <li class="navelem"><a class="el" href="dir_fd2d7b5ce83b1c1657cd6600d8cb39fa.html">llvm</a> </li>
+ <li class="navelem"><a class="el" href="dir_5760af5717174facf3d4fa63878994a9.html">ADT</a> </li>
+ </ul>
+ </div>
+</div>
+<div class="header">
+ <div class="headertitle">
+<div class="title">ScopedHashTable.h</div> </div>
+</div>
+<div class="contents">
+<a href="ScopedHashTable_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//===- ScopedHashTable.h - A simple scoped hash table ---------------------===//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file implements an efficient scoped hash table, which is useful for</span>
+<a name="l00011"></a>00011 <span class="comment">// things like dominator-based optimizations. This allows clients to do things</span>
+<a name="l00012"></a>00012 <span class="comment">// like this:</span>
+<a name="l00013"></a>00013 <span class="comment">//</span>
+<a name="l00014"></a>00014 <span class="comment">// ScopedHashTable<int, int> HT;</span>
+<a name="l00015"></a>00015 <span class="comment">// {</span>
+<a name="l00016"></a>00016 <span class="comment">// ScopedHashTableScope<int, int> Scope1(HT);</span>
+<a name="l00017"></a>00017 <span class="comment">// HT.insert(0, 0);</span>
+<a name="l00018"></a>00018 <span class="comment">// HT.insert(1, 1);</span>
+<a name="l00019"></a>00019 <span class="comment">// {</span>
+<a name="l00020"></a>00020 <span class="comment">// ScopedHashTableScope<int, int> Scope2(HT);</span>
+<a name="l00021"></a>00021 <span class="comment">// HT.insert(0, 42);</span>
+<a name="l00022"></a>00022 <span class="comment">// }</span>
+<a name="l00023"></a>00023 <span class="comment">// }</span>
+<a name="l00024"></a>00024 <span class="comment">//</span>
+<a name="l00025"></a>00025 <span class="comment">// Looking up the value for "0" in the Scope2 block will return 42. Looking</span>
+<a name="l00026"></a>00026 <span class="comment">// up the value for 0 before 42 is inserted or after Scope2 is popped will</span>
+<a name="l00027"></a>00027 <span class="comment">// return 0.</span>
+<a name="l00028"></a>00028 <span class="comment">//</span>
+<a name="l00029"></a>00029 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00030"></a>00030
+<a name="l00031"></a>00031 <span class="preprocessor">#ifndef LLVM_ADT_SCOPEDHASHTABLE_H</span>
+<a name="l00032"></a>00032 <span class="preprocessor"></span><span class="preprocessor">#define LLVM_ADT_SCOPEDHASHTABLE_H</span>
+<a name="l00033"></a>00033 <span class="preprocessor"></span>
+<a name="l00034"></a>00034 <span class="preprocessor">#include "<a class="code" href="DenseMap_8h.html">llvm/ADT/DenseMap.h</a>"</span>
+<a name="l00035"></a>00035 <span class="preprocessor">#include "<a class="code" href="Allocator_8h.html">llvm/Support/Allocator.h</a>"</span>
+<a name="l00036"></a>00036
+<a name="l00037"></a>00037 <span class="keyword">namespace </span>llvm {
+<a name="l00038"></a>00038
+<a name="l00039"></a>00039 <span class="keyword">template</span> <<span class="keyword">typename</span> K, <span class="keyword">typename</span> V, <span class="keyword">typename</span> KInfo = DenseMapInfo<K>,
+<a name="l00040"></a>00040 <span class="keyword">typename</span> AllocatorTy = MallocAllocator>
+<a name="l00041"></a>00041 <span class="keyword">class </span>ScopedHashTable;
+<a name="l00042"></a>00042
+<a name="l00043"></a>00043 <span class="keyword">template</span> <<span class="keyword">typename</span> K, <span class="keyword">typename</span> V>
+<a name="l00044"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html">00044</a> <span class="keyword">class </span><a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> {
+<a name="l00045"></a>00045 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *NextInScope;
+<a name="l00046"></a>00046 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *NextForKey;
+<a name="l00047"></a>00047 K Key;
+<a name="l00048"></a>00048 V Val;
+<a name="l00049"></a>00049 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a>(<span class="keyword">const</span> K &key, <span class="keyword">const</span> V &val) : Key(key), Val(val) {}
+<a name="l00050"></a>00050 <span class="keyword">public</span>:
+<a name="l00051"></a>00051
+<a name="l00052"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html#add80f0e09bc3f52223f2a18498fa50eb">00052</a> <span class="keyword">const</span> K &<a class="code" href="classllvm_1_1ScopedHashTableVal.html#add80f0e09bc3f52223f2a18498fa50eb">getKey</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> Key; }
+<a name="l00053"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html#a7ae4013210b7a9f290b777a006a3bf4e">00053</a> <span class="keyword">const</span> V &<a class="code" href="classllvm_1_1ScopedHashTableVal.html#a7ae4013210b7a9f290b777a006a3bf4e">getValue</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> Val; }
+<a name="l00054"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html#a31bd4e1afe4e777824d834fee5569654">00054</a> V &<a class="code" href="classllvm_1_1ScopedHashTableVal.html#a31bd4e1afe4e777824d834fee5569654">getValue</a>() { <span class="keywordflow">return</span> Val; }
+<a name="l00055"></a>00055
+<a name="l00056"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html#a6c2f3b5bc81b4992c09b5c610a86e785">00056</a> <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *<a class="code" href="classllvm_1_1ScopedHashTableVal.html#a6c2f3b5bc81b4992c09b5c610a86e785">getNextForKey</a>() { <span class="keywordflow">return</span> NextForKey; }
+<a name="l00057"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html#ae0f8afe222a8f773bee88599deef2291">00057</a> <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *<a class="code" href="classllvm_1_1ScopedHashTableVal.html#ae0f8afe222a8f773bee88599deef2291">getNextForKey</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> NextForKey; }
+<a name="l00058"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html#a16e5b4bee32fbc7a568cdf274b0e2946">00058</a> <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *<a class="code" href="classllvm_1_1ScopedHashTableVal.html#a16e5b4bee32fbc7a568cdf274b0e2946">getNextInScope</a>() { <span class="keywordflow">return</span> NextInScope; }
+<a name="l00059"></a>00059
+<a name="l00060"></a>00060 <span class="keyword">template</span> <<span class="keyword">typename</span> AllocatorTy>
+<a name="l00061"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html#aedf91a1e0506c0164e2749405915e9e2">00061</a> <span class="keyword">static</span> <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *<a class="code" href="classllvm_1_1ScopedHashTableVal.html#aedf91a1e0506c0164e2749405915e9e2">Create</a>(<a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *nextInScope,
+<a name="l00062"></a>00062 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *nextForKey,
+<a name="l00063"></a>00063 <span class="keyword">const</span> K &key, <span class="keyword">const</span> V &val,
+<a name="l00064"></a>00064 AllocatorTy &Allocator) {
+<a name="l00065"></a>00065 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a> *New = Allocator.template Allocate<ScopedHashTableVal>();
+<a name="l00066"></a>00066 <span class="comment">// Set up the value.</span>
+<a name="l00067"></a>00067 <span class="keyword">new</span> (New) <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a>(key, val);
+<a name="l00068"></a>00068 New->NextInScope = nextInScope;
+<a name="l00069"></a>00069 New->NextForKey = nextForKey;
+<a name="l00070"></a>00070 <span class="keywordflow">return</span> New;
+<a name="l00071"></a>00071 }
+<a name="l00072"></a>00072
+<a name="l00073"></a>00073 <span class="keyword">template</span> <<span class="keyword">typename</span> AllocatorTy>
+<a name="l00074"></a><a class="code" href="classllvm_1_1ScopedHashTableVal.html#afa142de6353eb00dc802a4fdaa752ac8">00074</a> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScopedHashTableVal.html#afa142de6353eb00dc802a4fdaa752ac8">Destroy</a>(AllocatorTy &Allocator) {
+<a name="l00075"></a>00075 <span class="comment">// Free memory referenced by the item.</span>
+<a name="l00076"></a>00076 this->~<a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal</a>();
+<a name="l00077"></a>00077 Allocator.Deallocate(<span class="keyword">this</span>);
+<a name="l00078"></a>00078 }
+<a name="l00079"></a>00079 };
+<a name="l00080"></a>00080
+<a name="l00081"></a>00081 <span class="keyword">template</span> <<span class="keyword">typename</span> K, <span class="keyword">typename</span> V, <span class="keyword">typename</span> KInfo = DenseMapInfo<K>,
+<a name="l00082"></a>00082 <span class="keyword">typename</span> AllocatorTy = MallocAllocator>
+<a name="l00083"></a><a class="code" href="classllvm_1_1ScopedHashTableScope.html">00083</a> <span class="keyword">class </span><a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a> {<span class="comment"></span>
+<a name="l00084"></a>00084 <span class="comment"> /// HT - The hashtable that we are active for.</span>
+<a name="l00085"></a>00085 <span class="comment"></span> <a class="code" href="classllvm_1_1ScopedHashTable.html">ScopedHashTable<K, V, KInfo, AllocatorTy></a> &HT;
+<a name="l00086"></a>00086 <span class="comment"></span>
+<a name="l00087"></a>00087 <span class="comment"> /// PrevScope - This is the scope that we are shadowing in HT.</span>
+<a name="l00088"></a>00088 <span class="comment"></span> <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a> *PrevScope;
+<a name="l00089"></a>00089 <span class="comment"></span>
+<a name="l00090"></a>00090 <span class="comment"> /// LastValInScope - This is the last value that was inserted for this scope</span>
+<a name="l00091"></a>00091 <span class="comment"> /// or null if none have been inserted yet.</span>
+<a name="l00092"></a>00092 <span class="comment"></span> <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> *LastValInScope;
+<a name="l00093"></a>00093 <span class="keywordtype">void</span> operator=(<a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a>&) <a class="code" href="Compiler_8h.html#aacca75352b8e153274310c374564eb01">LLVM_DELETED_FUNCTION</a>;
+<a name="l00094"></a>00094 <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a>(<a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a>&) <a class="code" href="Compiler_8h.html#aacca75352b8e153274310c374564eb01">LLVM_DELETED_FUNCTION</a>;
+<a name="l00095"></a>00095 <span class="keyword">public</span>:
+<a name="l00096"></a>00096 <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a>(<a class="code" href="classllvm_1_1ScopedHashTable.html">ScopedHashTable<K, V, KInfo, AllocatorTy></a> &HT);
+<a name="l00097"></a>00097 <a class="code" href="classllvm_1_1ScopedHashTableScope.html#a4e760236e413a4c31537281e1d5425d5">~ScopedHashTableScope</a>();
+<a name="l00098"></a>00098
+<a name="l00099"></a><a class="code" href="classllvm_1_1ScopedHashTableScope.html#aedfd48b6b79f32133bde9a551625635b">00099</a> <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a> *<a class="code" href="classllvm_1_1ScopedHashTableScope.html#aedfd48b6b79f32133bde9a551625635b">getParentScope</a>() { <span class="keywordflow">return</span> PrevScope; }
+<a name="l00100"></a><a class="code" href="classllvm_1_1ScopedHashTableScope.html#a21e574a8aec4ebc3bbde38d773331a95">00100</a> <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a> *<a class="code" href="classllvm_1_1ScopedHashTableScope.html#a21e574a8aec4ebc3bbde38d773331a95">getParentScope</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> PrevScope; }
+<a name="l00101"></a>00101
+<a name="l00102"></a>00102 <span class="keyword">private</span>:
+<a name="l00103"></a><a class="code" href="classllvm_1_1ScopedHashTableScope.html#ae4d998f25072daf15cf7ce875b978d39">00103</a> <span class="keyword">friend</span> <span class="keyword">class </span><a class="code" href="classllvm_1_1ScopedHashTable.html">ScopedHashTable</a><K, V, KInfo, AllocatorTy>;
+<a name="l00104"></a>00104 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> *getLastValInScope() {
+<a name="l00105"></a>00105 <span class="keywordflow">return</span> LastValInScope;
+<a name="l00106"></a>00106 }
+<a name="l00107"></a>00107 <span class="keywordtype">void</span> setLastValInScope(<a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> *Val) {
+<a name="l00108"></a>00108 LastValInScope = Val;
+<a name="l00109"></a>00109 }
+<a name="l00110"></a>00110 };
+<a name="l00111"></a>00111
+<a name="l00112"></a>00112
+<a name="l00113"></a>00113 <span class="keyword">template</span> <<span class="keyword">typename</span> K, <span class="keyword">typename</span> V, <span class="keyword">typename</span> KInfo = DenseMapInfo<K> >
+<a name="l00114"></a><a class="code" href="classllvm_1_1ScopedHashTableIterator.html">00114</a> <span class="keyword">class </span><a class="code" href="classllvm_1_1ScopedHashTableIterator.html">ScopedHashTableIterator</a> {
+<a name="l00115"></a>00115 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> *Node;
+<a name="l00116"></a>00116 <span class="keyword">public</span>:
+<a name="l00117"></a><a class="code" href="classllvm_1_1ScopedHashTableIterator.html#a0b4c19baa7002b51de4cd784711da4b6">00117</a> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html#a0b4c19baa7002b51de4cd784711da4b6">ScopedHashTableIterator</a>(<a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> *node) : Node(node) {}
+<a name="l00118"></a>00118
+<a name="l00119"></a><a class="code" href="classllvm_1_1ScopedHashTableIterator.html#a3ae027deb5b762a0b4bf8b1a28520691">00119</a> V &<a class="code" href="classllvm_1_1ScopedHashTableIterator.html#a3ae027deb5b762a0b4bf8b1a28520691">operator*</a>()<span class="keyword"> const </span>{
+<a name="l00120"></a>00120 assert(Node && <span class="stringliteral">"Dereference end()"</span>);
+<a name="l00121"></a>00121 <span class="keywordflow">return</span> Node->getValue();
+<a name="l00122"></a>00122 }
+<a name="l00123"></a><a class="code" href="classllvm_1_1ScopedHashTableIterator.html#abeb4e78d816dc4aa9df8ae66d2f19511">00123</a> V *<a class="code" href="classllvm_1_1ScopedHashTableIterator.html#abeb4e78d816dc4aa9df8ae66d2f19511">operator-></a>()<span class="keyword"> const </span>{
+<a name="l00124"></a>00124 <span class="keywordflow">return</span> &Node->getValue();
+<a name="l00125"></a>00125 }
+<a name="l00126"></a>00126
+<a name="l00127"></a><a class="code" href="classllvm_1_1ScopedHashTableIterator.html#a486352acb41cf9ae32fd44fdb1374a78">00127</a> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html#a486352acb41cf9ae32fd44fdb1374a78">operator==</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html">ScopedHashTableIterator</a> &RHS)<span class="keyword"> const </span>{
+<a name="l00128"></a>00128 <span class="keywordflow">return</span> Node == RHS.Node;
+<a name="l00129"></a>00129 }
+<a name="l00130"></a><a class="code" href="classllvm_1_1ScopedHashTableIterator.html#a850d244e2ca24bdbc4f7fedf1b98ac8c">00130</a> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html#a850d244e2ca24bdbc4f7fedf1b98ac8c">operator!=</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html">ScopedHashTableIterator</a> &RHS)<span class="keyword"> const </span>{
+<a name="l00131"></a>00131 <span class="keywordflow">return</span> Node != RHS.Node;
+<a name="l00132"></a>00132 }
+<a name="l00133"></a>00133
+<a name="l00134"></a><a class="code" href="classllvm_1_1ScopedHashTableIterator.html#abb71abb0e220210b5d931ef49bb10edf">00134</a> <span class="keyword">inline</span> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html">ScopedHashTableIterator</a>& <a class="code" href="classllvm_1_1ScopedHashTableIterator.html#abb71abb0e220210b5d931ef49bb10edf">operator++</a>() { <span class="comment">// Preincrement</span>
+<a name="l00135"></a>00135 assert(Node && <span class="stringliteral">"incrementing past end()"</span>);
+<a name="l00136"></a>00136 Node = Node->getNextForKey();
+<a name="l00137"></a>00137 <span class="keywordflow">return</span> *<span class="keyword">this</span>;
+<a name="l00138"></a>00138 }
+<a name="l00139"></a><a class="code" href="classllvm_1_1ScopedHashTableIterator.html#ae573eee195351581071a0bf813a0a839">00139</a> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html">ScopedHashTableIterator</a> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html#ae573eee195351581071a0bf813a0a839">operator++</a>(<span class="keywordtype">int</span>) { <span class="comment">// Postincrement</span>
+<a name="l00140"></a>00140 <a class="code" href="classllvm_1_1ScopedHashTableIterator.html">ScopedHashTableIterator</a> tmp = *<span class="keyword">this</span>; ++*<span class="keyword">this</span>; <span class="keywordflow">return</span> tmp;
+<a name="l00141"></a>00141 }
+<a name="l00142"></a>00142 };
+<a name="l00143"></a>00143
+<a name="l00144"></a>00144
+<a name="l00145"></a>00145 <span class="keyword">template</span> <<span class="keyword">typename</span> K, <span class="keyword">typename</span> V, <span class="keyword">typename</span> KInfo, <span class="keyword">typename</span> AllocatorTy>
+<a name="l00146"></a><a class="code" href="classllvm_1_1ScopedHashTable.html">00146</a> <span class="keyword">class </span><a class="code" href="classllvm_1_1ScopedHashTable.html">ScopedHashTable</a> {
+<a name="l00147"></a>00147 <span class="keyword">public</span>:<span class="comment"></span>
+<a name="l00148"></a>00148 <span class="comment"> /// ScopeTy - This is a helpful typedef that allows clients to get easy access</span>
+<a name="l00149"></a>00149 <span class="comment"> /// to the name of the scope for this hash table.</span>
+<a name="l00150"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a2bd418ae840e38621a1de5420b02342d">00150</a> <span class="comment"></span> <span class="keyword">typedef</span> <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope<K, V, KInfo, AllocatorTy></a> <a class="code" href="classllvm_1_1ScopedHashTable.html#a2bd418ae840e38621a1de5420b02342d">ScopeTy</a>;
+<a name="l00151"></a>00151 <span class="keyword">private</span>:
+<a name="l00152"></a>00152 <span class="keyword">typedef</span> <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ValTy</a>;
+<a name="l00153"></a>00153 <a class="code" href="classllvm_1_1DenseMap.html">DenseMap<K, ValTy*, KInfo></a> TopLevelMap;
+<a name="l00154"></a>00154 <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopeTy</a> *CurScope;
+<a name="l00155"></a>00155
+<a name="l00156"></a>00156 AllocatorTy Allocator;
+<a name="l00157"></a>00157
+<a name="l00158"></a>00158 <a class="code" href="classllvm_1_1ScopedHashTable.html#afc8a87137ced1a2ab0ff784a56332a29">ScopedHashTable</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1ScopedHashTable.html">ScopedHashTable</a>&); <span class="comment">// NOT YET IMPLEMENTED</span>
+<a name="l00159"></a>00159 <span class="keywordtype">void</span> operator=(<span class="keyword">const</span> <a class="code" href="classllvm_1_1ScopedHashTable.html">ScopedHashTable</a>&); <span class="comment">// NOT YET IMPLEMENTED</span>
+<a name="l00160"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a9cacde0ad5d45457a49128c4f5d160d9">00160</a> <span class="keyword">friend</span> <span class="keyword">class </span><a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopedHashTableScope</a><K, V, KInfo, AllocatorTy>;
+<a name="l00161"></a>00161 <span class="keyword">public</span>:
+<a name="l00162"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#afc8a87137ced1a2ab0ff784a56332a29">00162</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#afc8a87137ced1a2ab0ff784a56332a29">ScopedHashTable</a>() : CurScope(0) {}
+<a name="l00163"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a2048ed3be8eea84ec94b2b0526a4c00e">00163</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#a2048ed3be8eea84ec94b2b0526a4c00e">ScopedHashTable</a>(AllocatorTy <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11bad9577456b5bb7a03b7f42a710e122ab5">A</a>) : CurScope(0), Allocator(A) {}
+<a name="l00164"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a5e11b204b1703d5999ac2fac41fab462">00164</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#a5e11b204b1703d5999ac2fac41fab462">~ScopedHashTable</a>() {
+<a name="l00165"></a>00165 assert(CurScope == 0 && TopLevelMap.<a class="code" href="classllvm_1_1DenseMapBase.html#ac0ea276ca8ef68cc206db705a7092612">empty</a>() && <span class="stringliteral">"Scope imbalance!"</span>);
+<a name="l00166"></a>00166 }
+<a name="l00167"></a>00167
+<a name="l00168"></a>00168 <span class="comment"></span>
+<a name="l00169"></a>00169 <span class="comment"> /// Access to the allocator.</span>
+<a name="l00170"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#aeefcd809416003d13694f2ceb5486468">00170</a> <span class="comment"></span> <span class="keyword">typedef</span> <span class="keyword">typename</span> <a class="code" href="structllvm_1_1ReferenceAdder.html#ae3a707da112843ef0dca2f50bea0f970">ReferenceAdder<AllocatorTy>::result</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#aeefcd809416003d13694f2ceb5486468" title="Access to the allocator.">AllocatorRefTy</a>;
+<a name="l00171"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#af5ebba4017a31ec62b146f997841a3c7">00171</a> <span class="keyword">typedef</span> <span class="keyword">typename</span> <a class="code" href="structllvm_1_1ReferenceAdder.html#ae3a707da112843ef0dca2f50bea0f970">ReferenceAdder<const AllocatorTy>::result</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#af5ebba4017a31ec62b146f997841a3c7">AllocatorCRefTy</a>;
+<a name="l00172"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a2d28aafd56a3ef8569a1655a6bfcad52">00172</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#aeefcd809416003d13694f2ceb5486468" title="Access to the allocator.">AllocatorRefTy</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#a2d28aafd56a3ef8569a1655a6bfcad52">getAllocator</a>() { <span class="keywordflow">return</span> Allocator; }
+<a name="l00173"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#aeeacc797ec24daf821dffb90be8b8b54">00173</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#af5ebba4017a31ec62b146f997841a3c7">AllocatorCRefTy</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#aeeacc797ec24daf821dffb90be8b8b54">getAllocator</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> Allocator; }
+<a name="l00174"></a>00174
+<a name="l00175"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#ae2f8be190a012feb65ae521e7c1012c4">00175</a> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ScopedHashTable.html#ae2f8be190a012feb65ae521e7c1012c4">count</a>(<span class="keyword">const</span> K &Key)<span class="keyword"> const </span>{
+<a name="l00176"></a>00176 <span class="keywordflow">return</span> TopLevelMap.<a class="code" href="classllvm_1_1DenseMapBase.html#a4efb46d4834f6f750ae0649ed89ce44c" title="count - Return true if the specified key is in the map.">count</a>(Key);
+<a name="l00177"></a>00177 }
+<a name="l00178"></a>00178
+<a name="l00179"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a6590d9b4ca780d7f61b777029dd4b45b">00179</a> V <a class="code" href="classllvm_1_1ScopedHashTable.html#a6590d9b4ca780d7f61b777029dd4b45b">lookup</a>(<span class="keyword">const</span> K &Key) {
+<a name="l00180"></a>00180 <span class="keyword">typename</span> <a class="code" href="classllvm_1_1DenseMap.html">DenseMap<K, ValTy*, KInfo>::iterator</a> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> = TopLevelMap.<a class="code" href="classllvm_1_1DenseMapBase.html#a21cf94357e53cd1069aba475266fdb63">find</a>(Key);
+<a name="l00181"></a>00181 <span class="keywordflow">if</span> (I != TopLevelMap.<a class="code" href="classllvm_1_1DenseMapBase.html#a321e37d79af8b4287f8a1dcf9aff9c01">end</a>())
+<a name="l00182"></a>00182 <span class="keywordflow">return</span> I->second->getValue();
+<a name="l00183"></a>00183
+<a name="l00184"></a>00184 <span class="keywordflow">return</span> V();
+<a name="l00185"></a>00185 }
+<a name="l00186"></a>00186
+<a name="l00187"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a8824955db5de091ec7e48eba96fb4cea">00187</a> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScopedHashTable.html#a8824955db5de091ec7e48eba96fb4cea">insert</a>(<span class="keyword">const</span> K &Key, <span class="keyword">const</span> V &Val) {
+<a name="l00188"></a>00188 <a class="code" href="classllvm_1_1ScopedHashTable.html#a6dbb41fd5cc8c3a1aec830d3e6cd232e">insertIntoScope</a>(CurScope, Key, Val);
+<a name="l00189"></a>00189 }
+<a name="l00190"></a>00190
+<a name="l00191"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a3c81a90f289785e836dfbff67195fdef">00191</a> <span class="keyword">typedef</span> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html">ScopedHashTableIterator<K, V, KInfo></a> <a class="code" href="classllvm_1_1ScopedHashTable.html#a3c81a90f289785e836dfbff67195fdef">iterator</a>;
+<a name="l00192"></a>00192
+<a name="l00193"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a596dea5093a571b247daef479795354e">00193</a> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html">iterator</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#a596dea5093a571b247daef479795354e">end</a>() { <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1ScopedHashTable.html#a3c81a90f289785e836dfbff67195fdef">iterator</a>(0); }
+<a name="l00194"></a>00194
+<a name="l00195"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a0c102a7b1f547f7a52e6d4dd17fa3cb3">00195</a> <a class="code" href="classllvm_1_1ScopedHashTableIterator.html">iterator</a> <a class="code" href="classllvm_1_1ScopedHashTable.html#a0c102a7b1f547f7a52e6d4dd17fa3cb3">begin</a>(<span class="keyword">const</span> K &Key) {
+<a name="l00196"></a>00196 <span class="keyword">typename</span> <a class="code" href="classllvm_1_1DenseMap.html">DenseMap<K, ValTy*, KInfo>::iterator</a> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> =
+<a name="l00197"></a>00197 TopLevelMap.<a class="code" href="classllvm_1_1DenseMapBase.html#a21cf94357e53cd1069aba475266fdb63">find</a>(Key);
+<a name="l00198"></a>00198 <span class="keywordflow">if</span> (I == TopLevelMap.<a class="code" href="classllvm_1_1DenseMapBase.html#a321e37d79af8b4287f8a1dcf9aff9c01">end</a>()) <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1ScopedHashTable.html#a596dea5093a571b247daef479795354e">end</a>();
+<a name="l00199"></a>00199 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1ScopedHashTable.html#a3c81a90f289785e836dfbff67195fdef">iterator</a>(I->second);
+<a name="l00200"></a>00200 }
+<a name="l00201"></a>00201
+<a name="l00202"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a0f171ec614a9c400277196962bf2a98e">00202</a> <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopeTy</a> *<a class="code" href="classllvm_1_1ScopedHashTable.html#a0f171ec614a9c400277196962bf2a98e">getCurScope</a>() { <span class="keywordflow">return</span> CurScope; }
+<a name="l00203"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#aad1c3fe3d61f3579bcb14863bd351441">00203</a> <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopeTy</a> *<a class="code" href="classllvm_1_1ScopedHashTable.html#aad1c3fe3d61f3579bcb14863bd351441">getCurScope</a>()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> CurScope; }
+<a name="l00204"></a>00204 <span class="comment"></span>
+<a name="l00205"></a>00205 <span class="comment"> /// insertIntoScope - This inserts the specified key/value at the specified</span>
+<a name="l00206"></a>00206 <span class="comment"> /// (possibly not the current) scope. While it is ok to insert into a scope</span>
+<a name="l00207"></a>00207 <span class="comment"> /// that isn't the current one, it isn't ok to insert *underneath* an existing</span>
+<a name="l00208"></a>00208 <span class="comment"> /// value of the specified key.</span>
+<a name="l00209"></a><a class="code" href="classllvm_1_1ScopedHashTable.html#a6dbb41fd5cc8c3a1aec830d3e6cd232e">00209</a> <span class="comment"></span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScopedHashTable.html#a6dbb41fd5cc8c3a1aec830d3e6cd232e">insertIntoScope</a>(<a class="code" href="classllvm_1_1ScopedHashTableScope.html">ScopeTy</a> *S, <span class="keyword">const</span> K &Key, <span class="keyword">const</span> V &Val) {
+<a name="l00210"></a>00210 assert(S && <span class="stringliteral">"No scope active!"</span>);
+<a name="l00211"></a>00211 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> *&KeyEntry = TopLevelMap[Key];
+<a name="l00212"></a>00212 KeyEntry = <a class="code" href="classllvm_1_1ScopedHashTableVal.html#aedf91a1e0506c0164e2749405915e9e2">ValTy::Create</a>(S->getLastValInScope(), KeyEntry, Key, Val,
+<a name="l00213"></a>00213 Allocator);
+<a name="l00214"></a>00214 S->setLastValInScope(KeyEntry);
+<a name="l00215"></a>00215 }
+<a name="l00216"></a>00216 };
+<a name="l00217"></a>00217 <span class="comment"></span>
+<a name="l00218"></a>00218 <span class="comment">/// ScopedHashTableScope ctor - Install this as the current scope for the hash</span>
+<a name="l00219"></a>00219 <span class="comment">/// table.</span>
+<a name="l00220"></a>00220 <span class="comment"></span><span class="keyword">template</span> <<span class="keyword">typename</span> K, <span class="keyword">typename</span> V, <span class="keyword">typename</span> KInfo, <span class="keyword">typename</span> Allocator>
+<a name="l00221"></a>00221 ScopedHashTableScope<K, V, KInfo, Allocator>::
+<a name="l00222"></a>00222 ScopedHashTableScope(ScopedHashTable<K, V, KInfo, Allocator> &ht) : HT(ht) {
+<a name="l00223"></a>00223 PrevScope = HT.CurScope;
+<a name="l00224"></a>00224 HT.CurScope = <span class="keyword">this</span>;
+<a name="l00225"></a>00225 LastValInScope = 0;
+<a name="l00226"></a>00226 }
+<a name="l00227"></a>00227
+<a name="l00228"></a>00228 <span class="keyword">template</span> <<span class="keyword">typename</span> K, <span class="keyword">typename</span> V, <span class="keyword">typename</span> KInfo, <span class="keyword">typename</span> Allocator>
+<a name="l00229"></a><a class="code" href="classllvm_1_1ScopedHashTableScope.html#a4e760236e413a4c31537281e1d5425d5">00229</a> <a class="code" href="classllvm_1_1ScopedHashTableScope.html#a4e760236e413a4c31537281e1d5425d5">ScopedHashTableScope<K, V, KInfo, Allocator>::~ScopedHashTableScope</a>() {
+<a name="l00230"></a>00230 assert(HT.CurScope == <span class="keyword">this</span> && <span class="stringliteral">"Scope imbalance!"</span>);
+<a name="l00231"></a>00231 HT.CurScope = PrevScope;
+<a name="l00232"></a>00232
+<a name="l00233"></a>00233 <span class="comment">// Pop and delete all values corresponding to this scope.</span>
+<a name="l00234"></a>00234 <span class="keywordflow">while</span> (<a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> *ThisEntry = LastValInScope) {
+<a name="l00235"></a>00235 <span class="comment">// Pop this value out of the TopLevelMap.</span>
+<a name="l00236"></a>00236 <span class="keywordflow">if</span> (ThisEntry->getNextForKey() == 0) {
+<a name="l00237"></a>00237 assert(HT.TopLevelMap[ThisEntry->getKey()] == ThisEntry &&
+<a name="l00238"></a>00238 <span class="stringliteral">"Scope imbalance!"</span>);
+<a name="l00239"></a>00239 HT.TopLevelMap.erase(ThisEntry->getKey());
+<a name="l00240"></a>00240 } <span class="keywordflow">else</span> {
+<a name="l00241"></a>00241 <a class="code" href="classllvm_1_1ScopedHashTableVal.html">ScopedHashTableVal<K, V></a> *&KeyEntry = HT.TopLevelMap[ThisEntry->getKey()];
+<a name="l00242"></a>00242 assert(KeyEntry == ThisEntry && <span class="stringliteral">"Scope imbalance!"</span>);
+<a name="l00243"></a>00243 KeyEntry = ThisEntry-><a class="code" href="classllvm_1_1ScopedHashTableVal.html#a6c2f3b5bc81b4992c09b5c610a86e785">getNextForKey</a>();
+<a name="l00244"></a>00244 }
+<a name="l00245"></a>00245
+<a name="l00246"></a>00246 <span class="comment">// Pop this value out of the scope.</span>
+<a name="l00247"></a>00247 LastValInScope = ThisEntry-><a class="code" href="classllvm_1_1ScopedHashTableVal.html#a16e5b4bee32fbc7a568cdf274b0e2946">getNextInScope</a>();
+<a name="l00248"></a>00248
+<a name="l00249"></a>00249 <span class="comment">// Delete this entry.</span>
+<a name="l00250"></a>00250 ThisEntry-><a class="code" href="classllvm_1_1ScopedHashTableVal.html#afa142de6353eb00dc802a4fdaa752ac8">Destroy</a>(HT.getAllocator());
+<a name="l00251"></a>00251 }
+<a name="l00252"></a>00252 }
+<a name="l00253"></a>00253
+<a name="l00254"></a>00254 } <span class="comment">// end namespace llvm</span>
+<a name="l00255"></a>00255
+<a name="l00256"></a>00256 <span class="preprocessor">#endif</span>
+</pre></div></div>
+</div>
+<hr>
+<p class="footer">
+Generated on Fri Dec 21 2012 00:37:32 for <a href="http://llvm.org/">LLVM</a> by
+<a href="http://www.doxygen.org"><img src="doxygen.png" alt="Doxygen"
+align="middle" border="0"/>1.7.5.1</a><br>
+Copyright © 2003-2012 University of Illinois at Urbana-Champaign.
+All Rights Reserved.</p>
+
+<hr>
+<!--#include virtual="/attrib.incl" -->
+
+</body>
+</html>
Added: www-releases/trunk/3.2/docs/doxygen/html/ScoreboardHazardRecognizer_8h_source.html
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+++ www-releases/trunk/3.2/docs/doxygen/html/ScoreboardHazardRecognizer_8h_source.html Fri Dec 21 00:57:24 2012
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+<meta name="keywords" content="LLVM,Low Level Virtual Machine,C++,doxygen,API,documentation"/>
+<meta name="description" content="C++ source code API documentation for LLVM."/>
+<title>LLVM: ScoreboardHazardRecognizer.h Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
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+ <ul>
+ <li class="navelem"><a class="el" href="dir_b41d254693bea6e92988e5bb1ad97e02.html">llvm-3.2.src</a> </li>
+ <li class="navelem"><a class="el" href="dir_25acc6571c4e3a053ee4203146b47a61.html">include</a> </li>
+ <li class="navelem"><a class="el" href="dir_fd2d7b5ce83b1c1657cd6600d8cb39fa.html">llvm</a> </li>
+ <li class="navelem"><a class="el" href="dir_33f9015af551a3c03ac5a968f2023d57.html">CodeGen</a> </li>
+ </ul>
+ </div>
+</div>
+<div class="header">
+ <div class="headertitle">
+<div class="title">ScoreboardHazardRecognizer.h</div> </div>
+</div>
+<div class="contents">
+<a href="ScoreboardHazardRecognizer_8h.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//=- llvm/CodeGen/ScoreboardHazardRecognizer.h - Schedule Support -*- C++ -*-=//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file defines the ScoreboardHazardRecognizer class, which</span>
+<a name="l00011"></a>00011 <span class="comment">// encapsulates hazard-avoidance heuristics for scheduling, based on the</span>
+<a name="l00012"></a>00012 <span class="comment">// scheduling itineraries specified for the target.</span>
+<a name="l00013"></a>00013 <span class="comment">//</span>
+<a name="l00014"></a>00014 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00015"></a>00015
+<a name="l00016"></a>00016 <span class="preprocessor">#ifndef LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H</span>
+<a name="l00017"></a>00017 <span class="preprocessor"></span><span class="preprocessor">#define LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H</span>
+<a name="l00018"></a>00018 <span class="preprocessor"></span>
+<a name="l00019"></a>00019 <span class="preprocessor">#include "<a class="code" href="ScheduleHazardRecognizer_8h.html">llvm/CodeGen/ScheduleHazardRecognizer.h</a>"</span>
+<a name="l00020"></a>00020 <span class="preprocessor">#include "<a class="code" href="DataTypes_8h.html">llvm/Support/DataTypes.h</a>"</span>
+<a name="l00021"></a>00021
+<a name="l00022"></a>00022 <span class="preprocessor">#include <cassert></span>
+<a name="l00023"></a>00023 <span class="preprocessor">#include <cstring></span>
+<a name="l00024"></a>00024
+<a name="l00025"></a>00025 <span class="keyword">namespace </span>llvm {
+<a name="l00026"></a>00026
+<a name="l00027"></a>00027 <span class="keyword">class </span>InstrItineraryData;
+<a name="l00028"></a>00028 <span class="keyword">class </span>ScheduleDAG;
+<a name="l00029"></a>00029 <span class="keyword">class </span>SUnit;
+<a name="l00030"></a>00030
+<a name="l00031"></a><a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html">00031</a> <span class="keyword">class </span><a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html">ScoreboardHazardRecognizer</a> : <span class="keyword">public</span> <a class="code" href="classllvm_1_1ScheduleHazardRecognizer.html">ScheduleHazardRecognizer</a> {
+<a name="l00032"></a>00032 <span class="comment">// Scoreboard to track function unit usage. Scoreboard[0] is a</span>
+<a name="l00033"></a>00033 <span class="comment">// mask of the FUs in use in the cycle currently being</span>
+<a name="l00034"></a>00034 <span class="comment">// schedule. Scoreboard[1] is a mask for the next cycle. The</span>
+<a name="l00035"></a>00035 <span class="comment">// Scoreboard is used as a circular buffer with the current cycle</span>
+<a name="l00036"></a>00036 <span class="comment">// indicated by Head.</span>
+<a name="l00037"></a>00037 <span class="comment">//</span>
+<a name="l00038"></a>00038 <span class="comment">// Scoreboard always counts cycles in forward execution order. If used by a</span>
+<a name="l00039"></a>00039 <span class="comment">// bottom-up scheduler, then the scoreboard cycles are the inverse of the</span>
+<a name="l00040"></a>00040 <span class="comment">// scheduler's cycles.</span>
+<a name="l00041"></a>00041 <span class="keyword">class </span>Scoreboard {
+<a name="l00042"></a>00042 <span class="keywordtype">unsigned</span> *<a class="code" href="namespacellvm_1_1object_1_1macho.html#a56678f646a4a478d777eb8821f710db0a557a58f6e018464dcf0635728ef14dd1">Data</a>;
+<a name="l00043"></a>00043
+<a name="l00044"></a>00044 <span class="comment">// The maximum number of cycles monitored by the Scoreboard. This</span>
+<a name="l00045"></a>00045 <span class="comment">// value is determined based on the target itineraries to ensure</span>
+<a name="l00046"></a>00046 <span class="comment">// that all hazards can be tracked.</span>
+<a name="l00047"></a>00047 <span class="keywordtype">size_t</span> Depth;
+<a name="l00048"></a>00048 <span class="comment">// Indices into the Scoreboard that represent the current cycle.</span>
+<a name="l00049"></a>00049 <span class="keywordtype">size_t</span> Head;
+<a name="l00050"></a>00050 <span class="keyword">public</span>:
+<a name="l00051"></a>00051 Scoreboard():<a class="code" href="namespacellvm_1_1object_1_1macho.html#a56678f646a4a478d777eb8821f710db0a557a58f6e018464dcf0635728ef14dd1">Data</a>(NULL), Depth(0), Head(0) { }
+<a name="l00052"></a>00052 ~Scoreboard() {
+<a name="l00053"></a>00053 <span class="keyword">delete</span>[] <a class="code" href="namespacellvm_1_1object_1_1macho.html#a56678f646a4a478d777eb8821f710db0a557a58f6e018464dcf0635728ef14dd1">Data</a>;
+<a name="l00054"></a>00054 }
+<a name="l00055"></a>00055
+<a name="l00056"></a>00056 <span class="keywordtype">size_t</span> getDepth()<span class="keyword"> const </span>{ <span class="keywordflow">return</span> Depth; }
+<a name="l00057"></a>00057 <span class="keywordtype">unsigned</span>& operator[](<span class="keywordtype">size_t</span> idx)<span class="keyword"> const </span>{
+<a name="l00058"></a>00058 <span class="comment">// Depth is expected to be a power-of-2.</span>
+<a name="l00059"></a>00059 assert(Depth && !(Depth & (Depth - 1)) &&
+<a name="l00060"></a>00060 <span class="stringliteral">"Scoreboard was not initialized properly!"</span>);
+<a name="l00061"></a>00061
+<a name="l00062"></a>00062 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1object_1_1macho.html#a56678f646a4a478d777eb8821f710db0a557a58f6e018464dcf0635728ef14dd1">Data</a>[(Head + idx) & (Depth-1)];
+<a name="l00063"></a>00063 }
+<a name="l00064"></a>00064
+<a name="l00065"></a>00065 <span class="keywordtype">void</span> reset(<span class="keywordtype">size_t</span> d = 1) {
+<a name="l00066"></a>00066 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm_1_1object_1_1macho.html#a56678f646a4a478d777eb8821f710db0a557a58f6e018464dcf0635728ef14dd1">Data</a> == NULL) {
+<a name="l00067"></a>00067 Depth = d;
+<a name="l00068"></a>00068 <a class="code" href="namespacellvm_1_1object_1_1macho.html#a56678f646a4a478d777eb8821f710db0a557a58f6e018464dcf0635728ef14dd1">Data</a> = <span class="keyword">new</span> <span class="keywordtype">unsigned</span>[Depth];
+<a name="l00069"></a>00069 }
+<a name="l00070"></a>00070
+<a name="l00071"></a>00071 <a class="code" href="namespacellvm_1_1LibFunc.html#abf8f6830387f338fed0bce2e65108c6fa9f7f1b6be1144152902121f2463d0368" title="void *memset(void *b, int c, size_t len);">memset</a>(<a class="code" href="namespacellvm_1_1object_1_1macho.html#a56678f646a4a478d777eb8821f710db0a557a58f6e018464dcf0635728ef14dd1">Data</a>, 0, Depth * <span class="keyword">sizeof</span>(<a class="code" href="namespacellvm_1_1object_1_1macho.html#a56678f646a4a478d777eb8821f710db0a557a58f6e018464dcf0635728ef14dd1">Data</a>[0]));
+<a name="l00072"></a>00072 Head = 0;
+<a name="l00073"></a>00073 }
+<a name="l00074"></a>00074
+<a name="l00075"></a>00075 <span class="keywordtype">void</span> <a class="code" href="namespacellvm_1_1object.html#a77d2b12be43df06e7e80ed8c70b82709">advance</a>() {
+<a name="l00076"></a>00076 Head = (Head + 1) & (Depth-1);
+<a name="l00077"></a>00077 }
+<a name="l00078"></a>00078
+<a name="l00079"></a>00079 <span class="keywordtype">void</span> recede() {
+<a name="l00080"></a>00080 Head = (Head - 1) & (Depth-1);
+<a name="l00081"></a>00081 }
+<a name="l00082"></a>00082
+<a name="l00083"></a>00083 <span class="comment">// Print the scoreboard.</span>
+<a name="l00084"></a>00084 <span class="keywordtype">void</span> <a class="code" href="namespacellvm.html#a03503773241005f01b090b9862aad304">dump</a>() <span class="keyword">const</span>;
+<a name="l00085"></a>00085 };
+<a name="l00086"></a>00086
+<a name="l00087"></a>00087 <span class="preprocessor">#ifndef NDEBUG</span>
+<a name="l00088"></a>00088 <span class="preprocessor"></span> <span class="comment">// Support for tracing ScoreboardHazardRecognizer as a component within</span>
+<a name="l00089"></a>00089 <span class="comment">// another module. Follows the current thread-unsafe model of tracing.</span>
+<a name="l00090"></a>00090 <span class="keyword">static</span> <span class="keyword">const</span> <span class="keywordtype">char</span> *DebugType;
+<a name="l00091"></a>00091 <span class="preprocessor">#endif</span>
+<a name="l00092"></a>00092 <span class="preprocessor"></span>
+<a name="l00093"></a>00093 <span class="comment">// Itinerary data for the target.</span>
+<a name="l00094"></a>00094 <span class="keyword">const</span> <a class="code" href="classllvm_1_1InstrItineraryData.html">InstrItineraryData</a> *ItinData;
+<a name="l00095"></a>00095
+<a name="l00096"></a>00096 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *DAG;
+<a name="l00097"></a>00097 <span class="comment"></span>
+<a name="l00098"></a>00098 <span class="comment"> /// IssueWidth - Max issue per cycle. 0=Unknown.</span>
+<a name="l00099"></a>00099 <span class="comment"></span> <span class="keywordtype">unsigned</span> IssueWidth;
+<a name="l00100"></a>00100 <span class="comment"></span>
+<a name="l00101"></a>00101 <span class="comment"> /// IssueCount - Count instructions issued in this cycle.</span>
+<a name="l00102"></a>00102 <span class="comment"></span> <span class="keywordtype">unsigned</span> IssueCount;
+<a name="l00103"></a>00103
+<a name="l00104"></a>00104 Scoreboard ReservedScoreboard;
+<a name="l00105"></a>00105 Scoreboard RequiredScoreboard;
+<a name="l00106"></a>00106
+<a name="l00107"></a>00107 <span class="keyword">public</span>:
+<a name="l00108"></a>00108 <a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html#a5f9322345c87e05294a18b842253e4b5">ScoreboardHazardRecognizer</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1InstrItineraryData.html">InstrItineraryData</a> *ItinData,
+<a name="l00109"></a>00109 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ScheduleDAG.html">ScheduleDAG</a> *DAG,
+<a name="l00110"></a>00110 <span class="keyword">const</span> <span class="keywordtype">char</span> *ParentDebugType = <span class="stringliteral">""</span>);
+<a name="l00111"></a>00111 <span class="comment"></span>
+<a name="l00112"></a>00112 <span class="comment"> /// atIssueLimit - Return true if no more instructions may be issued in this</span>
+<a name="l00113"></a>00113 <span class="comment"> /// cycle.</span>
+<a name="l00114"></a>00114 <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html#a949cb2747796cfc2990ca4b8b7eb7192">atIssueLimit</a>() <span class="keyword">const</span>;
+<a name="l00115"></a>00115
+<a name="l00116"></a>00116 <span class="comment">// Stalls provides an cycle offset at which SU will be scheduled. It will be</span>
+<a name="l00117"></a>00117 <span class="comment">// negative for bottom-up scheduling.</span>
+<a name="l00118"></a>00118 <span class="keyword">virtual</span> <a class="code" href="classllvm_1_1ScheduleHazardRecognizer.html#a9bec0e329b12bbc503d08db497d43267">HazardType</a> <a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html#ade72dd46b878397c2be1a40a027c671e">getHazardType</a>(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU, <span class="keywordtype">int</span> Stalls);
+<a name="l00119"></a>00119 <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html#a03b0ea812bb68e841e7c8233c3853b1b">Reset</a>();
+<a name="l00120"></a>00120 <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html#aa6812ac0c61dfe0101be5c2e1b8d9ba5">EmitInstruction</a>(<a class="code" href="classllvm_1_1SUnit.html" title="SUnit - Scheduling unit. This is a node in the scheduling DAG.">SUnit</a> *SU);
+<a name="l00121"></a>00121 <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html#af45c71894601eeecdc612a17328b0d49">AdvanceCycle</a>();
+<a name="l00122"></a>00122 <span class="keyword">virtual</span> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ScoreboardHazardRecognizer.html#a13376837917cba98c1d2cc49b1b50576">RecedeCycle</a>();
+<a name="l00123"></a>00123 };
+<a name="l00124"></a>00124
+<a name="l00125"></a>00125 }
+<a name="l00126"></a>00126
+<a name="l00127"></a>00127 <span class="preprocessor">#endif //!LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H</span>
+</pre></div></div>
+</div>
+<hr>
+<p class="footer">
+Generated on Fri Dec 21 2012 00:37:32 for <a href="http://llvm.org/">LLVM</a> by
+<a href="http://www.doxygen.org"><img src="doxygen.png" alt="Doxygen"
+align="middle" border="0"/>1.7.5.1</a><br>
+Copyright © 2003-2012 University of Illinois at Urbana-Champaign.
+All Rights Reserved.</p>
+
+<hr>
+<!--#include virtual="/attrib.incl" -->
+
+</body>
+</html>
Added: www-releases/trunk/3.2/docs/doxygen/html/SearchForAddressOfSpecialSymbol_8cpp_source.html
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.2/docs/doxygen/html/SearchForAddressOfSpecialSymbol_8cpp_source.html?rev=170845&view=auto
==============================================================================
--- www-releases/trunk/3.2/docs/doxygen/html/SearchForAddressOfSpecialSymbol_8cpp_source.html (added)
+++ www-releases/trunk/3.2/docs/doxygen/html/SearchForAddressOfSpecialSymbol_8cpp_source.html Fri Dec 21 00:57:24 2012
@@ -0,0 +1,113 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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+<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"/>
+<meta name="keywords" content="LLVM,Low Level Virtual Machine,C++,doxygen,API,documentation"/>
+<meta name="description" content="C++ source code API documentation for LLVM."/>
+<title>LLVM: SearchForAddressOfSpecialSymbol.cpp Source File</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head><body>
+<p class="title">LLVM API Documentation</p>
+<!-- Generated by Doxygen 1.7.5.1 -->
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+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
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+ <li class="current"><a href="files.html"><span>Files</span></a></li>
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+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>File Members</span></a></li>
+ </ul>
+ </div>
+ <div id="nav-path" class="navpath">
+ <ul>
+ <li class="navelem"><a class="el" href="dir_b41d254693bea6e92988e5bb1ad97e02.html">llvm-3.2.src</a> </li>
+ <li class="navelem"><a class="el" href="dir_74e9364f374e99e3aeab4fae4e196292.html">lib</a> </li>
+ <li class="navelem"><a class="el" href="dir_3927ff15cdce1d22d8dcb33a29894069.html">Support</a> </li>
+ </ul>
+ </div>
+</div>
+<div class="header">
+ <div class="headertitle">
+<div class="title">SearchForAddressOfSpecialSymbol.cpp</div> </div>
+</div>
+<div class="contents">
+<a href="SearchForAddressOfSpecialSymbol_8cpp.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//===- SearchForAddressOfSpecialSymbol.cpp - Function addresses -*- C++ -*-===//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file pulls the addresses of certain symbols out of the linker. It must</span>
+<a name="l00011"></a>00011 <span class="comment">// include as few header files as possible because it declares the symbols as</span>
+<a name="l00012"></a>00012 <span class="comment">// void*, which would conflict with the actual symbol type if any header</span>
+<a name="l00013"></a>00013 <span class="comment">// declared it.</span>
+<a name="l00014"></a>00014 <span class="comment">//</span>
+<a name="l00015"></a>00015 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00016"></a>00016
+<a name="l00017"></a>00017 <span class="preprocessor">#include <string.h></span>
+<a name="l00018"></a>00018
+<a name="l00019"></a>00019 <span class="comment">// Must declare the symbols in the global namespace.</span>
+<a name="l00020"></a><a class="code" href="SearchForAddressOfSpecialSymbol_8cpp.html#a93ff722658154c522bb73d03a4bb5d17">00020</a> <span class="keyword">static</span> <span class="keywordtype">void</span> *<a class="code" href="SearchForAddressOfSpecialSymbol_8cpp.html#a93ff722658154c522bb73d03a4bb5d17">DoSearch</a>(<span class="keyword">const</span> <span class="keywordtype">char</span>* symbolName) {
+<a name="l00021"></a>00021 <span class="preprocessor">#define EXPLICIT_SYMBOL(SYM) \</span>
+<a name="l00022"></a>00022 <span class="preprocessor"> extern void *SYM; if (!strcmp(symbolName, #SYM)) return &SYM</span>
+<a name="l00023"></a>00023 <span class="preprocessor"></span>
+<a name="l00024"></a>00024 <span class="comment">// If this is darwin, it has some funky issues, try to solve them here. Some</span>
+<a name="l00025"></a>00025 <span class="comment">// important symbols are marked 'private external' which doesn't allow</span>
+<a name="l00026"></a>00026 <span class="comment">// SearchForAddressOfSymbol to find them. As such, we special case them here,</span>
+<a name="l00027"></a>00027 <span class="comment">// there is only a small handful of them.</span>
+<a name="l00028"></a>00028
+<a name="l00029"></a>00029 <span class="preprocessor">#ifdef __APPLE__</span>
+<a name="l00030"></a>00030 <span class="preprocessor"></span> {
+<a name="l00031"></a>00031 <span class="comment">// __eprintf is sometimes used for assert() handling on x86.</span>
+<a name="l00032"></a>00032 <span class="comment">//</span>
+<a name="l00033"></a>00033 <span class="comment">// FIXME: Currently disabled when using Clang, as we don't always have our</span>
+<a name="l00034"></a>00034 <span class="comment">// runtime support libraries available.</span>
+<a name="l00035"></a>00035 <span class="preprocessor">#ifndef __clang__</span>
+<a name="l00036"></a>00036 <span class="preprocessor"></span><span class="preprocessor">#ifdef __i386__</span>
+<a name="l00037"></a>00037 <span class="preprocessor"></span> <a class="code" href="DynamicLibrary_8cpp.html#a5277c791a48b31f68dbef1de772218e9">EXPLICIT_SYMBOL</a>(__eprintf);
+<a name="l00038"></a>00038 <span class="preprocessor">#endif</span>
+<a name="l00039"></a>00039 <span class="preprocessor"></span><span class="preprocessor">#endif</span>
+<a name="l00040"></a>00040 <span class="preprocessor"></span> }
+<a name="l00041"></a>00041 <span class="preprocessor">#endif</span>
+<a name="l00042"></a>00042 <span class="preprocessor"></span>
+<a name="l00043"></a>00043 <span class="preprocessor">#ifdef __CYGWIN__</span>
+<a name="l00044"></a>00044 <span class="preprocessor"></span> {
+<a name="l00045"></a>00045 <a class="code" href="DynamicLibrary_8cpp.html#a5277c791a48b31f68dbef1de772218e9">EXPLICIT_SYMBOL</a>(_alloca);
+<a name="l00046"></a>00046 <a class="code" href="DynamicLibrary_8cpp.html#a5277c791a48b31f68dbef1de772218e9">EXPLICIT_SYMBOL</a>(__main);
+<a name="l00047"></a>00047 }
+<a name="l00048"></a>00048 <span class="preprocessor">#endif</span>
+<a name="l00049"></a>00049 <span class="preprocessor"></span>
+<a name="l00050"></a>00050 <span class="preprocessor">#undef EXPLICIT_SYMBOL</span>
+<a name="l00051"></a>00051 <span class="preprocessor"></span> <span class="keywordflow">return</span> 0;
+<a name="l00052"></a>00052 }
+<a name="l00053"></a>00053
+<a name="l00054"></a>00054 <span class="keyword">namespace </span>llvm {
+<a name="l00055"></a><a class="code" href="namespacellvm.html#a7785178b05096736112d384ec13e78ac">00055</a> <span class="keywordtype">void</span> *<a class="code" href="namespacellvm.html#a7785178b05096736112d384ec13e78ac">SearchForAddressOfSpecialSymbol</a>(<span class="keyword">const</span> <span class="keywordtype">char</span>* symbolName) {
+<a name="l00056"></a>00056 <span class="keywordflow">return</span> <a class="code" href="SearchForAddressOfSpecialSymbol_8cpp.html#a93ff722658154c522bb73d03a4bb5d17">DoSearch</a>(symbolName);
+<a name="l00057"></a>00057 }
+<a name="l00058"></a>00058 } <span class="comment">// namespace llvm</span>
+</pre></div></div>
+</div>
+<hr>
+<p class="footer">
+Generated on Fri Dec 21 2012 00:37:32 for <a href="http://llvm.org/">LLVM</a> by
+<a href="http://www.doxygen.org"><img src="doxygen.png" alt="Doxygen"
+align="middle" border="0"/>1.7.5.1</a><br>
+Copyright © 2003-2012 University of Illinois at Urbana-Champaign.
+All Rights Reserved.</p>
+
+<hr>
+<!--#include virtual="/attrib.incl" -->
+
+</body>
+</html>
Added: www-releases/trunk/3.2/docs/doxygen/html/SelectionDAGBuilder_8cpp__incl.dot
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.2/docs/doxygen/html/SelectionDAGBuilder_8cpp__incl.dot?rev=170845&view=auto
==============================================================================
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+++ www-releases/trunk/3.2/docs/doxygen/html/SelectionDAGDumper_8cpp.html Fri Dec 21 00:57:24 2012
@@ -0,0 +1,252 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
+<html><head>
+<meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1"/>
+<meta name="keywords" content="LLVM,Low Level Virtual Machine,C++,doxygen,API,documentation"/>
+<meta name="description" content="C++ source code API documentation for LLVM."/>
+<title>LLVM: SelectionDAGDumper.cpp File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css"/>
+</head><body>
+<p class="title">LLVM API Documentation</p>
+<!-- Generated by Doxygen 1.7.5.1 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
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+ <li><a href="annotated.html"><span>Classes</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ <li><a href="dirs.html"><span>Directories</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>File Members</span></a></li>
+ </ul>
+ </div>
+ <div id="nav-path" class="navpath">
+ <ul>
+ <li class="navelem"><a class="el" href="dir_b41d254693bea6e92988e5bb1ad97e02.html">llvm-3.2.src</a> </li>
+ <li class="navelem"><a class="el" href="dir_74e9364f374e99e3aeab4fae4e196292.html">lib</a> </li>
+ <li class="navelem"><a class="el" href="dir_f2244d21cf8bec63d11bfc1ad661d96f.html">CodeGen</a> </li>
+ <li class="navelem"><a class="el" href="dir_43253d775e33d5158290be54cbed80db.html">SelectionDAG</a> </li>
+ </ul>
+ </div>
+</div>
+<div class="header">
+ <div class="summary">
+<a href="#typedef-members">Typedefs</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">SelectionDAGDumper.cpp File Reference</div> </div>
+</div>
+<div class="contents">
+<div class="textblock"><code>#include "<a class="el" href="ScheduleDAGSDNodes_8h_source.html">ScheduleDAGSDNodes.h</a>"</code><br/>
+<code>#include "<a class="el" href="DebugInfo_8h_source.html">llvm/DebugInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="Function_8h_source.html">llvm/Function.h</a>"</code><br/>
+<code>#include "<a class="el" href="Intrinsics_8h_source.html">llvm/Intrinsics.h</a>"</code><br/>
+<code>#include "<a class="el" href="Writer_8h_source.html">llvm/Assembly/Writer.h</a>"</code><br/>
+<code>#include "<a class="el" href="SelectionDAG_8h_source.html">llvm/CodeGen/SelectionDAG.h</a>"</code><br/>
+<code>#include "<a class="el" href="MachineConstantPool_8h_source.html">llvm/CodeGen/MachineConstantPool.h</a>"</code><br/>
+<code>#include "<a class="el" href="MachineFunction_8h_source.html">llvm/CodeGen/MachineFunction.h</a>"</code><br/>
+<code>#include "<a class="el" href="MachineModuleInfo_8h_source.html">llvm/CodeGen/MachineModuleInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetInstrInfo_8h_source.html">llvm/Target/TargetInstrInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetIntrinsicInfo_8h_source.html">llvm/Target/TargetIntrinsicInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="Target_2TargetMachine_8h_source.html">llvm/Target/TargetMachine.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetRegisterInfo_8h_source.html">llvm/Target/TargetRegisterInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="Debug_8h_source.html">llvm/Support/Debug.h</a>"</code><br/>
+<code>#include "<a class="el" href="GraphWriter_8h_source.html">llvm/Support/GraphWriter.h</a>"</code><br/>
+<code>#include "<a class="el" href="raw__ostream_8h_source.html">llvm/Support/raw_ostream.h</a>"</code><br/>
+<code>#include "<a class="el" href="StringExtras_8h_source.html">llvm/ADT/StringExtras.h</a>"</code><br/>
+</div><div class="textblock"><div class="dynheader">
+Include dependency graph for SelectionDAGDumper.cpp:</div>
+<div class="dyncontent">
+<div class="center"><img src="SelectionDAGDumper_8cpp__incl.png" border="0" usemap="#SelectionDAGDumper_8cpp" alt=""/></div>
+<!-- MAP 0 -->
+</div>
+</div>
+<p><a href="SelectionDAGDumper_8cpp_source.html">Go to the source code of this file.</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">typedef <a class="el" href="classllvm_1_1SmallPtrSet.html">SmallPtrSet</a>< const <br class="typebreak"/>
+<a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *, 128 > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGDumper_8cpp.html#ab0be3ea5f7c82a73082d80598dcdb156">VisitedSDNodeSet</a></td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGDumper_8cpp.html#ad9526a1ce54457f4cef4a593ad1e99ea">DumpNodes</a> (const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="el" href="classunsigned.html">unsigned</a> indent, const <a class="el" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> *G)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGDumper_8cpp.html#a8b40b63522fe1b491ba458feec392ea6">DumpNodesr</a> (<a class="el" href="classllvm_1_1raw__ostream.html">raw_ostream</a> &OS, const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="el" href="classunsigned.html">unsigned</a> indent, const <a class="el" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> *G, <a class="el" href="SelectionDAGDumper_8cpp.html#ab0be3ea5f7c82a73082d80598dcdb156">VisitedSDNodeSet</a> &once)</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGDumper_8cpp.html#adfc37ceb937f230dbfdbda000e383090">printrWithDepthHelper</a> (<a class="el" href="classllvm_1_1raw__ostream.html">raw_ostream</a> &OS, const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *N, const <a class="el" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> *G, <a class="el" href="classunsigned.html">unsigned</a> depth, <a class="el" href="classunsigned.html">unsigned</a> indent)</td></tr>
+</table>
+<hr/><h2>Typedef Documentation</h2>
+<a class="anchor" id="ab0be3ea5f7c82a73082d80598dcdb156"></a><!-- doxytag: member="SelectionDAGDumper.cpp::VisitedSDNodeSet" ref="ab0be3ea5f7c82a73082d80598dcdb156" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef <a class="el" href="classllvm_1_1SmallPtrSet.html">SmallPtrSet</a><const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *, 128> <a class="el" href="SelectionDAGDumper_8cpp.html#ab0be3ea5f7c82a73082d80598dcdb156">VisitedSDNodeSet</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00547">547</a> of file <a class="el" href="SelectionDAGDumper_8cpp_source.html">SelectionDAGDumper.cpp</a>.</p>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="ad9526a1ce54457f4cef4a593ad1e99ea"></a><!-- doxytag: member="SelectionDAGDumper.cpp::DumpNodes" ref="ad9526a1ce54457f4cef4a593ad1e99ea" args="(const SDNode *N, unsigned indent, const SelectionDAG *G)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void DumpNodes </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>indent</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> * </td>
+ <td class="paramname"><em>G</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00515">515</a> of file <a class="el" href="SelectionDAGDumper_8cpp_source.html">SelectionDAGDumper.cpp</a>.</p>
+
+<p>References <a class="el" href="Debug_8cpp_source.html#l00101">llvm::dbgs()</a>, <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00329">llvm::SDNode::dump()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">llvm::SDValue::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00532">llvm::SDNode::getNumOperands()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00400">llvm::SDNode::hasOneUse()</a>, and <a class="el" href="raw__ostream_8cpp_source.html#l00385">llvm::raw_ostream::indent()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00528">llvm::SelectionDAG::dump()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a8b40b63522fe1b491ba458feec392ea6"></a><!-- doxytag: member="SelectionDAGDumper.cpp::DumpNodesr" ref="a8b40b63522fe1b491ba458feec392ea6" args="(raw_ostream &OS, const SDNode *N, unsigned indent, const SelectionDAG *G, VisitedSDNodeSet &once)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void DumpNodesr </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1raw__ostream.html">raw_ostream</a> & </td>
+ <td class="paramname"><em>OS</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>indent</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> * </td>
+ <td class="paramname"><em>G</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="SelectionDAGDumper_8cpp.html#ab0be3ea5f7c82a73082d80598dcdb156">VisitedSDNodeSet</a> & </td>
+ <td class="paramname"><em>once</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00548">548</a> of file <a class="el" href="SelectionDAGDumper_8cpp_source.html">SelectionDAGDumper.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">llvm::SDValue::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00532">llvm::SDNode::getNumOperands()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00102">llvm::SDValue::getResNo()</a>, <a class="el" href="raw__ostream_8cpp_source.html#l00385">llvm::raw_ostream::indent()</a>, <a class="el" href="SmallPtrSet_8h_source.html#l00254">llvm::SmallPtrSet< PtrType, SmallSize >::insert()</a>, and <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00542">llvm::SDNode::printr()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00584">llvm::SDNode::dumpr()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="adfc37ceb937f230dbfdbda000e383090"></a><!-- doxytag: member="SelectionDAGDumper.cpp::printrWithDepthHelper" ref="adfc37ceb937f230dbfdbda000e383090" args="(raw_ostream &OS, const SDNode *N, const SelectionDAG *G, unsigned depth, unsigned indent)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void printrWithDepthHelper </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1raw__ostream.html">raw_ostream</a> & </td>
+ <td class="paramname"><em>OS</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> * </td>
+ <td class="paramname"><em>G</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>depth</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>indent</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00594">594</a> of file <a class="el" href="SelectionDAGDumper_8cpp_source.html">SelectionDAGDumper.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">llvm::SDValue::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00532">llvm::SDNode::getNumOperands()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00774">llvm::SDValue::getValueType()</a>, <a class="el" href="raw__ostream_8cpp_source.html#l00385">llvm::raw_ostream::indent()</a>, <a class="el" href="ValueTypes_8h_source.html#l00038">llvm::MVT::Other</a>, and <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00635">llvm::SDNode::print()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGDumper_8cpp_source.html#l00616">llvm::SDNode::printrWithDepth()</a>.</p>
+
+</div>
+</div>
+</div>
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+<title>LLVM: SelectionDAGISel.cpp File Reference</title>
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+<p class="title">LLVM API Documentation</p>
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+ <li class="navelem"><a class="el" href="dir_f2244d21cf8bec63d11bfc1ad661d96f.html">CodeGen</a> </li>
+ <li class="navelem"><a class="el" href="dir_43253d775e33d5158290be54cbed80db.html">SelectionDAG</a> </li>
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+<a href="#namespaces">Namespaces</a> |
+<a href="#define-members">Defines</a> |
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+<a href="#func-members">Functions</a> |
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+ <div class="headertitle">
+<div class="title">SelectionDAGISel.cpp File Reference</div> </div>
+</div>
+<div class="contents">
+<div class="textblock"><code>#include "<a class="el" href="ScheduleDAGSDNodes_8h_source.html">ScheduleDAGSDNodes.h</a>"</code><br/>
+<code>#include "<a class="el" href="SelectionDAGBuilder_8h_source.html">SelectionDAGBuilder.h</a>"</code><br/>
+<code>#include "<a class="el" href="Constants_8h_source.html">llvm/Constants.h</a>"</code><br/>
+<code>#include "<a class="el" href="DebugInfo_8h_source.html">llvm/DebugInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="Function_8h_source.html">llvm/Function.h</a>"</code><br/>
+<code>#include "<a class="el" href="InlineAsm_8h_source.html">llvm/InlineAsm.h</a>"</code><br/>
+<code>#include "<a class="el" href="Instructions_8h_source.html">llvm/Instructions.h</a>"</code><br/>
+<code>#include "<a class="el" href="Intrinsics_8h_source.html">llvm/Intrinsics.h</a>"</code><br/>
+<code>#include "<a class="el" href="IntrinsicInst_8h_source.html">llvm/IntrinsicInst.h</a>"</code><br/>
+<code>#include "<a class="el" href="LLVMContext_8h_source.html">llvm/LLVMContext.h</a>"</code><br/>
+<code>#include "<a class="el" href="Module_8h_source.html">llvm/Module.h</a>"</code><br/>
+<code>#include "<a class="el" href="AliasAnalysis_8h_source.html">llvm/Analysis/AliasAnalysis.h</a>"</code><br/>
+<code>#include "<a class="el" href="BranchProbabilityInfo_8h_source.html">llvm/Analysis/BranchProbabilityInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="FastISel_8h_source.html">llvm/CodeGen/FastISel.h</a>"</code><br/>
+<code>#include "<a class="el" href="FunctionLoweringInfo_8h_source.html">llvm/CodeGen/FunctionLoweringInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="GCStrategy_8h_source.html">llvm/CodeGen/GCStrategy.h</a>"</code><br/>
+<code>#include "<a class="el" href="GCMetadata_8h_source.html">llvm/CodeGen/GCMetadata.h</a>"</code><br/>
+<code>#include "<a class="el" href="MachineFrameInfo_8h_source.html">llvm/CodeGen/MachineFrameInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="MachineFunction_8h_source.html">llvm/CodeGen/MachineFunction.h</a>"</code><br/>
+<code>#include "<a class="el" href="MachineInstrBuilder_8h_source.html">llvm/CodeGen/MachineInstrBuilder.h</a>"</code><br/>
+<code>#include "<a class="el" href="MachineModuleInfo_8h_source.html">llvm/CodeGen/MachineModuleInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="MachineRegisterInfo_8h_source.html">llvm/CodeGen/MachineRegisterInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="ScheduleHazardRecognizer_8h_source.html">llvm/CodeGen/ScheduleHazardRecognizer.h</a>"</code><br/>
+<code>#include "<a class="el" href="SchedulerRegistry_8h_source.html">llvm/CodeGen/SchedulerRegistry.h</a>"</code><br/>
+<code>#include "<a class="el" href="SelectionDAG_8h_source.html">llvm/CodeGen/SelectionDAG.h</a>"</code><br/>
+<code>#include "<a class="el" href="SelectionDAGISel_8h_source.html">llvm/CodeGen/SelectionDAGISel.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetRegisterInfo_8h_source.html">llvm/Target/TargetRegisterInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetIntrinsicInfo_8h_source.html">llvm/Target/TargetIntrinsicInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetInstrInfo_8h_source.html">llvm/Target/TargetInstrInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetLibraryInfo_8h_source.html">llvm/Target/TargetLibraryInfo.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetLowering_8h_source.html">llvm/Target/TargetLowering.h</a>"</code><br/>
+<code>#include "<a class="el" href="Target_2TargetMachine_8h_source.html">llvm/Target/TargetMachine.h</a>"</code><br/>
+<code>#include "<a class="el" href="TargetOptions_8h_source.html">llvm/Target/TargetOptions.h</a>"</code><br/>
+<code>#include "<a class="el" href="BasicBlockUtils_8h_source.html">llvm/Transforms/Utils/BasicBlockUtils.h</a>"</code><br/>
+<code>#include "<a class="el" href="Compiler_8h_source.html">llvm/Support/Compiler.h</a>"</code><br/>
+<code>#include "<a class="el" href="Debug_8h_source.html">llvm/Support/Debug.h</a>"</code><br/>
+<code>#include "<a class="el" href="ErrorHandling_8h_source.html">llvm/Support/ErrorHandling.h</a>"</code><br/>
+<code>#include "<a class="el" href="Timer_8h_source.html">llvm/Support/Timer.h</a>"</code><br/>
+<code>#include "<a class="el" href="raw__ostream_8h_source.html">llvm/Support/raw_ostream.h</a>"</code><br/>
+<code>#include "<a class="el" href="PostOrderIterator_8h_source.html">llvm/ADT/PostOrderIterator.h</a>"</code><br/>
+<code>#include "<a class="el" href="Statistic_8h_source.html">llvm/ADT/Statistic.h</a>"</code><br/>
+<code>#include <algorithm></code><br/>
+</div><div class="textblock"><div class="dynheader">
+Include dependency graph for SelectionDAGISel.cpp:</div>
+<div class="dyncontent">
+<div class="center"><img src="SelectionDAGISel_8cpp__incl.png" border="0" usemap="#SelectionDAGISel_8cpp" alt=""/></div>
+<!-- MAP 0 -->
+</div>
+</div>
+<p><a href="SelectionDAGISel_8cpp_source.html">Go to the source code of this file.</a></p>
+<table class="memberdecls">
+<tr><td colspan="2"><h2><a name="namespaces"></a>
+Namespaces</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">namespace </td><td class="memItemRight" valign="bottom"><a class="el" href="namespacellvm.html">llvm</a></td></tr>
+<tr><td class="mdescLeft"> </td><td class="mdescRight"><p>List of target independent CodeGen pass IDs. </p>
+<br/></td></tr>
+<tr><td colspan="2"><h2><a name="define-members"></a>
+Defines</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ad78e062f62e0d6e453941fb4ca843e4d">DEBUG_TYPE</a> "isel"</td></tr>
+<tr><td colspan="2"><h2><a name="enum-members"></a>
+Enumerations</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">enum </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ac6cd0b51896db5749a4e980d3ff455ee">ChainResult</a> { <a class="el" href="SelectionDAGISel_8cpp.html#ac6cd0b51896db5749a4e980d3ff455eea0a6c2ab7f55c86f88acc60dcc525ce1a">CR_Simple</a>,
+<a class="el" href="SelectionDAGISel_8cpp.html#ac6cd0b51896db5749a4e980d3ff455eeaa1b1f84cfc5d9f183da5247e66b0dbf7">CR_InducesCycle</a>,
+<a class="el" href="SelectionDAGISel_8cpp.html#ac6cd0b51896db5749a4e980d3ff455eea9bd57bfa2b960ba18a1e68e1b8af21ab">CR_LeadsToInteriorNode</a>
+ }</td></tr>
+<tr><td colspan="2"><h2><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a8f8de71119ce7ef1af413a5e555b6ca0">STATISTIC</a> (NumFastIselFailures,"Number of <a class="el" href="SimplifyInstructions_8cpp.html#afbf38da490ab8cea559fee0c9081db06">instructions</a> fast isel failed on")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a012a4ab923e36be9dbe6e9e757749241">STATISTIC</a> (NumFastIselSuccess,"Number of <a class="el" href="SimplifyInstructions_8cpp.html#afbf38da490ab8cea559fee0c9081db06">instructions</a> fast isel selected")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a4fb7080a199ac44b772f3c9869376ff0">STATISTIC</a> (NumFastIselBlocks,"Number of blocks selected entirely by fast isel")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a55be46e59a794a2f58b2cf6a9ed96563">STATISTIC</a> (NumDAGBlocks,"Number of blocks selected using DAG")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#af7d237256bcb5b26f8dc10aa8212a35d">STATISTIC</a> (NumDAGIselRetries,"Number of times dag isel has to try another path")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#af25613558512edf86e21db1ed10c1e54">STATISTIC</a> (NumFastIselFailRet,"Fast isel fails on Ret")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a0da893f63639896ddeaf910763ada8a1">STATISTIC</a> (NumFastIselFailBr,"Fast isel fails on Br")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#aa30f18b699d8d673afb67eefa8edfcb6">STATISTIC</a> (NumFastIselFailSwitch,"Fast isel fails on Switch")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a2372e5ed377c5d8c73a5c2c663bb64b1">STATISTIC</a> (NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a91427b4cb58c6eee245e7dfe76122024">STATISTIC</a> (NumFastIselFailInvoke,"Fast isel fails on Invoke")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a12c46028df83582854b730a0889eaef0">STATISTIC</a> (NumFastIselFailResume,"Fast isel fails on Resume")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a87630530c1bfcbf4a3e9a10e73d166c4">STATISTIC</a> (NumFastIselFailUnreachable,"Fast isel fails on Unreachable")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a7dc53ed853f83b36adf37bfec08e90d5">STATISTIC</a> (NumFastIselFailAdd,"Fast isel fails on Add")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a5ba284f4788abd2082f3e6c7da6451e7">STATISTIC</a> (NumFastIselFailFAdd,"Fast isel fails on FAdd")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#abd6ce8bcf334790e81ffaca4b7d26349">STATISTIC</a> (NumFastIselFailSub,"Fast isel fails on Sub")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a73d04a5a05fc79742b8cc7b3cd45b89a">STATISTIC</a> (NumFastIselFailFSub,"Fast isel fails on FSub")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a2e0fdf0bedf6e191a0dfc11d754dc5b0">STATISTIC</a> (NumFastIselFailMul,"Fast isel fails on Mul")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ad5788753aa0197903f37aa21e99afe11">STATISTIC</a> (NumFastIselFailFMul,"Fast isel fails on FMul")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#acbc2b5c4774a919c0d07173f34b92d3c">STATISTIC</a> (NumFastIselFailUDiv,"Fast isel fails on UDiv")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a47239ec37b31fef09162e8fa77c6b76c">STATISTIC</a> (NumFastIselFailSDiv,"Fast isel fails on SDiv")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a33f80afae00be29a6889ddb95e93e22e">STATISTIC</a> (NumFastIselFailFDiv,"Fast isel fails on FDiv")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#aa63a527b85083f59a31530075f00c300">STATISTIC</a> (NumFastIselFailURem,"Fast isel fails on URem")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a37b6862b79fcd66034cabe8a8feb5279">STATISTIC</a> (NumFastIselFailSRem,"Fast isel fails on SRem")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a6a74215342ea3b2eb7d1f89b55f604c8">STATISTIC</a> (NumFastIselFailFRem,"Fast isel fails on FRem")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a34baacf6fdd1ba97fc7f6a6e7f1fc12c">STATISTIC</a> (NumFastIselFailAnd,"Fast isel fails on And")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a4fd7aa87cfc0b266665745e2bbc21eb2">STATISTIC</a> (NumFastIselFailOr,"Fast isel fails on Or")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ac4e2c9aa8693f5fbc59577e7b2e89fb9">STATISTIC</a> (NumFastIselFailXor,"Fast isel fails on Xor")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a319a382b2bdb4410c090ac693cb8d572">STATISTIC</a> (NumFastIselFailAlloca,"Fast isel fails on Alloca")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ae4f3be68874336ee92ce82d45626b66a">STATISTIC</a> (NumFastIselFailLoad,"Fast isel fails on Load")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a238582f8fb9d3ea5bcffb24cb616357a">STATISTIC</a> (NumFastIselFailStore,"Fast isel fails on Store")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ae1c26e8d98dffc316aa431b28221e1b9">STATISTIC</a> (NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a55952e301a7c88e6128d299cccd550e1">STATISTIC</a> (NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#addfafe4306d6194feee38d5f9dc3a394">STATISTIC</a> (NumFastIselFailFence,"Fast isel fails on Frence")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ad0bc1640397fdb7f66644024805db7b4">STATISTIC</a> (NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a17384a029c48186f9b9b9b7c7891db0e">STATISTIC</a> (NumFastIselFailTrunc,"Fast isel fails on Trunc")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a209e10fd37f5538653dda81c86e3f5ca">STATISTIC</a> (NumFastIselFailZExt,"Fast isel fails on ZExt")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ac7824f7a244ad2c41947ff64bf67a8ea">STATISTIC</a> (NumFastIselFailSExt,"Fast isel fails on SExt")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a371d5b847d32ae90de8eba10935eb4b2">STATISTIC</a> (NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#af29ad109e7bcc0c67b399898bad71792">STATISTIC</a> (NumFastIselFailFPExt,"Fast isel fails on FPExt")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#aaf4bc347a7dd0ab279c1cc15ed12d0af">STATISTIC</a> (NumFastIselFailFPToUI,"Fast isel fails on FPToUI")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a91fcc96dfb8d3f343d0ae34774768d11">STATISTIC</a> (NumFastIselFailFPToSI,"Fast isel fails on FPToSI")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a5dad427534e458a8b36bc5d864f07920">STATISTIC</a> (NumFastIselFailUIToFP,"Fast isel fails on UIToFP")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a4484c295e23e75e249ec9ff3e4c7efbd">STATISTIC</a> (NumFastIselFailSIToFP,"Fast isel fails on SIToFP")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#aab4b56e3ae3c320a0bd0063b8a1b6b2c">STATISTIC</a> (NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a251414e3221d4b8aacccbc4a9b940764">STATISTIC</a> (NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a39ede8bf61467966c69887f44fb9ca55">STATISTIC</a> (NumFastIselFailBitCast,"Fast isel fails on BitCast")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a1baae66d5d6a7164e291ce020aa7ef1e">STATISTIC</a> (NumFastIselFailICmp,"Fast isel fails on ICmp")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a8043f28dbd7e11a1fd137bcb357cc284">STATISTIC</a> (NumFastIselFailFCmp,"Fast isel fails on FCmp")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a9f5232adba00631120418de427ac5251">STATISTIC</a> (NumFastIselFailPHI,"Fast isel fails on PHI")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a0d2149e47589582f9000b3b183a93968">STATISTIC</a> (NumFastIselFailSelect,"Fast isel fails on Select")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ae34fa43f64f4be9e8c4bd93943909bd0">STATISTIC</a> (NumFastIselFailCall,"Fast isel fails on Call")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a05784e64ab162567bd06df09f2f5a449">STATISTIC</a> (NumFastIselFailShl,"Fast isel fails on Shl")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a34b65bb7be96acdde43d6fc86bd317a5">STATISTIC</a> (NumFastIselFailLShr,"Fast isel fails on LShr")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a29530a0019c36c1c767bdf14f0557977">STATISTIC</a> (NumFastIselFailAShr,"Fast isel fails on AShr")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a8c8080a3981dc6ca463dee0d056050ea">STATISTIC</a> (NumFastIselFailVAArg,"Fast isel fails on VAArg")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#aa3475a06a507f8cd93ae2abc675864d3">STATISTIC</a> (NumFastIselFailExtractElement,"Fast isel fails on ExtractElement")</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#aaee960026d756bbe908af089d3642bff">STATISTIC</a> (NumFastIselFailInsertElement,"Fast isel fails on InsertElement")</td></tr>
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+LLVM_ATTRIBUTE_ALWAYS_INLINE <br class="typebreak"/>
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+<tr><td class="mdescLeft"> </td><td class="mdescRight">GetVBR - decode a vbr encoding whose top bit is set. <a href="#a27774280441b6460e4183ab3054ea406"></a><br/></td></tr>
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+<tr><td class="memItemLeft" align="right" valign="top">static <br class="typebreak"/>
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+<tr><td class="memItemLeft" align="right" valign="top">static <br class="typebreak"/>
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+LLVM_ATTRIBUTE_ALWAYS_INLINE <br class="typebreak"/>
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+<tr><td class="memItemLeft" align="right" valign="top">static <br class="typebreak"/>
+LLVM_ATTRIBUTE_ALWAYS_INLINE <br class="typebreak"/>
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+<tr><td class="memItemLeft" align="right" valign="top">static <br class="typebreak"/>
+LLVM_ATTRIBUTE_ALWAYS_INLINE <br class="typebreak"/>
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+<tr><td class="memItemLeft" align="right" valign="top">static <br class="typebreak"/>
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+<tr><td colspan="2"><h2><a name="var-members"></a>
+Variables</h2></td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a086b60310efb455c4b210eeae130b974">EnableFastISelVerbose2</a> ("fast-isel-verbose2", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Enable extra verbose messages in the \"fast\" ""instruction selector"))</td></tr>
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+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a9d50504a9daa484cb9ffe06b0a4e8d0c">EnableFastISelAbort</a> ("fast-isel-abort", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Enable abort <a class="el" href="Scalar_2SimplifyLibCalls_8cpp.html#a4c349cd4b664546b9b9eef619d58c12d">calls</a> when \"fast\" instruction fails"))</td></tr>
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+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a94d15c343cf88bcdac352ecec4163427">ViewLegalizeTypesDAGs</a> ("view-legalize-types-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show dags before legalize types"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a6ea92b9ff38ccbd5e49b8db2ee2ed6c0">ViewLegalizeDAGs</a> ("view-legalize-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show dags before legalize"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a5eb1e524620af2b978b96889db819cd5">ViewDAGCombine2</a> ("view-dag-combine2-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show dags before the second ""dag combine <a class="el" href="TwoAddressInstructionPass_8cpp.html#a34b5cf133e2453a532a504197fec9171">pass</a>"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a9493966ca8816c129a6afef7ef0b0866">ViewDAGCombineLT</a> ("view-dag-combine-lt-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show dags before the post legalize types"" dag combine <a class="el" href="TwoAddressInstructionPass_8cpp.html#a34b5cf133e2453a532a504197fec9171">pass</a>"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a1020617e313312866c30e376a9e4558f">ViewISelDAGs</a> ("view-isel-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show isel dags as they are selected"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a561cc487aa2f40047631afeca18a058a">ViewSchedDAGs</a> ("view-sched-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show sched dags as they are processed"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a>< <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#ae7868871a8317ca2ce9ff0dfde545b24">ViewSUnitDAGs</a> ("view-sunit-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show <a class="el" href="classllvm_1_1SUnit.html">SUnit</a> dags after they are processed"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><br class="typebreak"/>
+< RegisterScheduler::FunctionPassCtor, <br class="typebreak"/>
+<a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>, <a class="el" href="classllvm_1_1RegisterPassParser.html">RegisterPassParser</a><br class="typebreak"/>
+< <a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> > > </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#afabfb264c515ec09675c6a53ecf95785">ISHeuristic</a> ("pre-RA-sched", cl::init(&createDefaultScheduler), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Instruction schedulers available (before register"" <a class="el" href="StrongPHIElimination_8cpp.html#a1a0492b9a49bb2dab78ace5b3298fad6">allocation</a>):"))</td></tr>
+<tr><td class="memItemLeft" align="right" valign="top">static <a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="SelectionDAGISel_8cpp.html#a2ffa56bb0fe093d549f7c5b8cb32cc98">defaultListDAGScheduler</a> ("default","Best scheduler for the target", createDefaultScheduler)</td></tr>
+</table>
+<hr/><h2>Define Documentation</h2>
+<a class="anchor" id="ad78e062f62e0d6e453941fb4ca843e4d"></a><!-- doxytag: member="SelectionDAGISel.cpp::DEBUG_TYPE" ref="ad78e062f62e0d6e453941fb4ca843e4d" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define DEBUG_TYPE "isel"</td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l00014">14</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+</div>
+</div>
+<hr/><h2>Enumeration Type Documentation</h2>
+<a class="anchor" id="ac6cd0b51896db5749a4e980d3ff455ee"></a><!-- doxytag: member="SelectionDAGISel.cpp::ChainResult" ref="ac6cd0b51896db5749a4e980d3ff455ee" args="" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">enum <a class="el" href="SelectionDAGISel_8cpp.html#ac6cd0b51896db5749a4e980d3ff455ee">ChainResult</a></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<dl><dt><b>Enumerator: </b></dt><dd><table border="0" cellspacing="2" cellpadding="0">
+<tr><td valign="top"><em><a class="anchor" id="ac6cd0b51896db5749a4e980d3ff455eea0a6c2ab7f55c86f88acc60dcc525ce1a"></a><!-- doxytag: member="CR_Simple" ref="ac6cd0b51896db5749a4e980d3ff455eea0a6c2ab7f55c86f88acc60dcc525ce1a" args="" -->CR_Simple</em> </td><td>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ac6cd0b51896db5749a4e980d3ff455eeaa1b1f84cfc5d9f183da5247e66b0dbf7"></a><!-- doxytag: member="CR_InducesCycle" ref="ac6cd0b51896db5749a4e980d3ff455eeaa1b1f84cfc5d9f183da5247e66b0dbf7" args="" -->CR_InducesCycle</em> </td><td>
+</td></tr>
+<tr><td valign="top"><em><a class="anchor" id="ac6cd0b51896db5749a4e980d3ff455eea9bd57bfa2b960ba18a1e68e1b8af21ab"></a><!-- doxytag: member="CR_LeadsToInteriorNode" ref="ac6cd0b51896db5749a4e980d3ff455eea9bd57bfa2b960ba18a1e68e1b8af21ab" args="" -->CR_LeadsToInteriorNode</em> </td><td>
+</td></tr>
+</table>
+</dd>
+</dl>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l01774">1774</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+</div>
+</div>
+<hr/><h2>Function Documentation</h2>
+<a class="anchor" id="a617864a293ee07b291bef2224ea10567"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckAndImm" ref="a617864a293ee07b291bef2224ea10567" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckAndImm </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a> & </td>
+ <td class="paramname"><em>SDISel</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02095">2095</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="ISDOpcodes_8h_source.html#l00307">llvm::ISD::AND</a>, <a class="el" href="CallingConv_8h_source.html#l00031">llvm::CallingConv::C</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l01428">llvm::SelectionDAGISel::CheckAndMask()</a>, <a class="el" href="Casting_8h_source.html#l00233">llvm::dyn_cast()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00771">llvm::SDValue::getOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00780">llvm::SDValue::getOperand()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l01687">GetVBR()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="acae3c0616dac16e457abe75892673ad4"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckChildType" ref="acae3c0616dac16e457abe75892673ad4" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering &TLI, unsigned ChildNo)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckChildType </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetLowering.html">TargetLowering</a> & </td>
+ <td class="paramname"><em>TLI</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>ChildNo</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02056">2056</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGISel_8cpp_source.html#l02046">CheckType()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00777">llvm::SDValue::getNumOperands()</a>, and <a class="el" href="SelectionDAGNodes_8h_source.html#l00780">llvm::SDValue::getOperand()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="aaab015bad5b65423fd9921361c3c4e57"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckCondCode" ref="aaab015bad5b65423fd9921361c3c4e57" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckCondCode </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02066">2066</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a55ddd986b32899ac868a18ee9d1182a1"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckInteger" ref="a55ddd986b32899ac868a18ee9d1182a1" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckInteger </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02084">2084</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="CallingConv_8h_source.html#l00031">llvm::CallingConv::C</a>, <a class="el" href="Casting_8h_source.html#l00233">llvm::dyn_cast()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l01162">llvm::ConstantSDNode::getSExtValue()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l01687">GetVBR()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a4c75c8c52c2be067a8825ce146452bc2"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckNodePredicate" ref="a4c75c8c52c2be067a8825ce146452bc2" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel, SDNode *N)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckNodePredicate </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a> & </td>
+ <td class="paramname"><em>SDISel</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>CheckNodePredicate - Implements OP_CheckNodePredicate. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02032">2032</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGISel_8h_source.html#l00219">llvm::SelectionDAGISel::CheckNodePredicate()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ae27ccd25e008885da31b6af396bbb0cf"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckOpcode" ref="ae27ccd25e008885da31b6af396bbb0cf" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDNode *N)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckOpcode </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02038">2038</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a6699dbb00a8f802ae5f1db4599f93121"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckOrImm" ref="a6699dbb00a8f802ae5f1db4599f93121" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SelectionDAGISel &SDISel)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckOrImm </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a> & </td>
+ <td class="paramname"><em>SDISel</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02108">2108</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="CallingConv_8h_source.html#l00031">llvm::CallingConv::C</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l01457">llvm::SelectionDAGISel::CheckOrMask()</a>, <a class="el" href="Casting_8h_source.html#l00233">llvm::dyn_cast()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00771">llvm::SDValue::getOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00780">llvm::SDValue::getOperand()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l01687">GetVBR()</a>, and <a class="el" href="ISDOpcodes_8h_source.html#l00307">llvm::ISD::OR</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="abb3b2c1fa23bf08df12215f52696c0f1"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckPatternPredicate" ref="abb3b2c1fa23bf08df12215f52696c0f1" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, const SelectionDAGISel &SDISel)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckPatternPredicate </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a> & </td>
+ <td class="paramname"><em>SDISel</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>CheckPatternPredicate - Implements OP_CheckPatternPredicate. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02025">2025</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGISel_8h_source.html#l00211">llvm::SelectionDAGISel::CheckPatternPredicate()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a79923c0bb7ad7ead32b876800220d6b3"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckSame" ref="a79923c0bb7ad7ead32b876800220d6b3" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const SmallVectorImpl< std::pair< SDValue, SDNode * > > &RecordedNodes)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckSame </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl</a>< std::pair< <a class="el" href="classllvm_1_1SDValue.html">SDValue</a>, <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * > > & </td>
+ <td class="paramname"><em>RecordedNodes</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>CheckSame - Implements OP_CheckSame. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02014">2014</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a59c52febe3a70cc54a8af6d4c67fdee9"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckType" ref="a59c52febe3a70cc54a8af6d4c67fdee9" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering &TLI)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckType </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetLowering.html">TargetLowering</a> & </td>
+ <td class="paramname"><em>TLI</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02046">2046</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="TargetLowering_8h_source.html#l00153">llvm::TargetLowering::getPointerTy()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00774">llvm::SDValue::getValueType()</a>, and <a class="el" href="ValueTypes_8h_source.html#l00140">llvm::MVT::iPTR</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02056">CheckChildType()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ad989c21528eda8f431248737176cc3c4"></a><!-- doxytag: member="SelectionDAGISel.cpp::CheckValueType" ref="ad989c21528eda8f431248737176cc3c4" args="(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N, const TargetLowering &TLI)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> CheckValueType </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>MatcherIndex</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1TargetLowering.html">TargetLowering</a> & </td>
+ <td class="paramname"><em>TLI</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02073">2073</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="TargetLowering_8h_source.html#l00153">llvm::TargetLowering::getPointerTy()</a>, and <a class="el" href="ValueTypes_8h_source.html#l00140">llvm::MVT::iPTR</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">IsPredicateKnownToFail()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="abc62c7ae4b5f73ce4a6e84dcc10682a3"></a><!-- doxytag: member="SelectionDAGISel.cpp::collectFailStats" ref="abc62c7ae4b5f73ce4a6e84dcc10682a3" args="(const Instruction *I)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void collectFailStats </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1Instruction.html">Instruction</a> * </td>
+ <td class="paramname"><em>I</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l00908">908</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="InstVisitor_8h_source.html#l00133">llvm::Alloca</a>, <a class="el" href="APInt_8h_source.html#l01759">llvm::APIntOps::And()</a>, <a class="el" href="CallingConvLower_8h_source.html#l00149">llvm::Call</a>, <a class="el" href="InstCombineCompares_8cpp_source.html#l00040">ExtractElement()</a>, <a class="el" href="InstVisitor_8h_source.html#l00154">llvm::FPExt</a>, <a class="el" href="InstVisitor_8h_source.html#l00150">llvm::FPToSI</a>, <a class="el" href="Instruction_8h_source.html#l00082">llvm::Instruction::getOpcode()</a>, <a class="el" href="InstVisitor_8h_source.html#l00162">llvm::ICmp</a>, <a class="el" href="InstVisitor_8h_source.html#l00174">llvm::InsertValue</a>, <a class="el" href="InstVisitor_8h_source.html#l00156">llvm::IntToPtr</a>, <a class="el" href="SparcInstrInfo_8h_source.html#l00031">llvm::SPII::Load</a>, <a class="el" href="InstVisitor_8h_source.html#l00124">llvm::LShr</a>, <a class="el" href="APInt_8h_source.html#l01765">llv
m::APIntOps::Or()</a>, <a class="el" href="InstVisitor_8h_source.html#l00164">llvm::PHI</a>, <a class="el" href="MBlazeISelLowering_8h_source.html#l00082">llvm::MBlazeISD::Ret</a>, <a class="el" href="MCInstrDesc_8h_source.html#l00110">llvm::MCID::Select</a>, <a class="el" href="InstVisitor_8h_source.html#l00148">llvm::SExt</a>, <a class="el" href="InstVisitor_8h_source.html#l00172">llvm::ShuffleVector</a>, <a class="el" href="InstVisitor_8h_source.html#l00152">llvm::SIToFP</a>, <a class="el" href="SparcInstrInfo_8h_source.html#l00032">llvm::SPII::Store</a>, <a class="el" href="InstVisitor_8h_source.html#l00146">llvm::Trunc</a>, and <a class="el" href="APInt_8h_source.html#l01771">llvm::APIntOps::Xor()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ad2b055f61a61a64d892bdae575ca6209"></a><!-- doxytag: member="SelectionDAGISel.cpp::findGlueUse" ref="ad2b055f61a61a64d892bdae575ca6209" args="(SDNode *N)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="classllvm_1_1SDNode.html">SDNode</a>* findGlueUse </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>N</em></td><td>)</td>
+ <td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>findGlueUse - Return use of MVT::Glue value produced by the specified SDNode. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l01537">1537</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGNodes_8h_source.html#l00589">llvm::SDNode::getNumValues()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00241">llvm::SDUse::getResNo()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00233">llvm::SDUse::getUser()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00482">llvm::SDNode::use_begin()</a>, and <a class="el" href="SelectionDAGNodes_8h_source.html#l00486">llvm::SDNode::use_end()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l01599">llvm::SelectionDAGISel::IsLegalToFold()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a3834318b09ff2507fd007a27e734d8d6"></a><!-- doxytag: member="SelectionDAGISel.cpp::findNonImmUse" ref="a3834318b09ff2507fd007a27e734d8d6" args="(SDNode *Use, SDNode *Def, SDNode *ImmedUse, SDNode *Root, SmallPtrSet< SDNode *, 16 > &Visited, bool IgnoreChains)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> findNonImmUse </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>Use</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>Def</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>ImmedUse</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>Root</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallPtrSet.html">SmallPtrSet</a>< <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> *, 16 > & </td>
+ <td class="paramname"><em>Visited</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> </td>
+ <td class="paramname"><em>IgnoreChains</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>findNonImmUse - Return true if "Use" is a non-immediate use of "Def". This function recursively traverses up the operand chain, ignoring certain nodes. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l01550">1550</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">llvm::SDValue::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00411">llvm::SDNode::getNodeId()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00532">llvm::SDNode::getNumOperands()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00538">llvm::SDNode::getOperand()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00774">llvm::SDValue::getValueType()</a>, <a class="el" href="SmallPtrSet_8h_source.html#l00254">llvm::SmallPtrSet< PtrType, SmallSize >::insert()</a>, and <a class="el" href="ValueTypes_8h_source.html#l00038">llvm::MVT::Other</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l01599">llvm::SelectionDAGISel::IsLegalToFold()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a27774280441b6460e4183ab3054ea406"></a><!-- doxytag: member="SelectionDAGISel.cpp::GetVBR" ref="a27774280441b6460e4183ab3054ea406" args="(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static LLVM_ATTRIBUTE_ALWAYS_INLINE uint64_t GetVBR </td>
+ <td>(</td>
+ <td class="paramtype">uint64_t </td>
+ <td class="paramname"><em>Val</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>MatcherTable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> & </td>
+ <td class="paramname"><em>Idx</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>GetVBR - decode a vbr encoding whose top bit is set. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l01687">1687</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02095">CheckAndImm()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02084">CheckInteger()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02108">CheckOrImm()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="aeb0bc3fb3008d1f61c5a1adb0b901c82"></a><!-- doxytag: member="SelectionDAGISel.cpp::HandleMergeInputChains" ref="aeb0bc3fb3008d1f61c5a1adb0b901c82" args="(SmallVectorImpl< SDNode * > &ChainNodesMatched, SelectionDAG *CurDAG)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="classllvm_1_1SDValue.html">SDValue</a> HandleMergeInputChains </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl</a>< <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * > & </td>
+ <td class="paramname"><em>ChainNodesMatched</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> * </td>
+ <td class="paramname"><em>CurDAG</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>HandleMergeInputChains - This implements the OPC_EmitMergeInputChains operation for when the pattern matched at least one node with a chains. The input vector contains a list of all of the chained nodes that we match. We must determine if this is a valid thing to cover (i.e. matching it won't induce cycles in the DAG) and if so, creating a TokenFactor node. that will be used as the input node chain for the generated nodes. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l01908">1908</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T >::begin()</a>, <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l01776">CR_InducesCycle</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T >::end()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">llvm::SDValue::getNode()</a>, <a class="el" href="SelectionDAG_8cpp_source.html#l02409">llvm::SelectionDAG::getNode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00532">llvm::SDNode::getNumOperands()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l0
0538">llvm::SDNode::getOperand()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00774">llvm::SDValue::getValueType()</a>, <a class="el" href="ValueTypes_8h_source.html#l00038">llvm::MVT::Other</a>, <a class="el" href="SmallVector_8h_source.html#l00231">llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back()</a>, <a class="el" href="SmallVector_8h_source.html#l00126">llvm::SmallVectorTemplateCommon< T >::size()</a>, <a class="el" href="SmallVector_8h_source.html#l00126">llvm::SmallVectorTemplateCommon< T, typename >::size()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00050">llvm::ISD::TokenFactor</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l01790">WalkChainUsers()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a9eb151f67a54574fa315413f25a5b53c"></a><!-- doxytag: member="SelectionDAGISel.cpp::isFoldedOrDeadInstruction" ref="a9eb151f67a54574fa315413f25a5b53c" args="(const Instruction *I, FunctionLoweringInfo *FuncInfo)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> isFoldedOrDeadInstruction </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1Instruction.html">Instruction</a> * </td>
+ <td class="paramname"><em>I</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1FunctionLoweringInfo.html">FunctionLoweringInfo</a> * </td>
+ <td class="paramname"><em>FuncInfo</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>isFoldedOrDeadInstruction - Return true if the specified instruction is side-effect free and is either dead or folded into a generated instruction. Return false if it needs to be emitted. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l00894">894</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, <a class="el" href="FunctionLoweringInfo_8h_source.html#l00135">llvm::FunctionLoweringInfo::isExportedInst()</a>, and <a class="el" href="Instruction_8cpp_source.html#l00350">llvm::Instruction::mayWriteToMemory()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a41976e1f6ca65fb7830e1f348d751000"></a><!-- doxytag: member="SelectionDAGISel.cpp::IsPredicateKnownToFail" ref="a41976e1f6ca65fb7830e1f348d751000" args="(const unsigned char *Table, unsigned Index, SDValue N, bool &Result, const SelectionDAGISel &SDISel, SmallVectorImpl< std::pair< SDValue, SDNode * > > &RecordedNodes)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="classunsigned.html">unsigned</a> IsPredicateKnownToFail </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classunsigned.html">unsigned</a> <a class="el" href="classchar.html">char</a> * </td>
+ <td class="paramname"><em>Table</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classunsigned.html">unsigned</a> </td>
+ <td class="paramname"><em>Index</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SDValue.html">SDValue</a> </td>
+ <td class="paramname"><em>N</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a> & </td>
+ <td class="paramname"><em>Result</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a> & </td>
+ <td class="paramname"><em>SDISel</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl</a>< std::pair< <a class="el" href="classllvm_1_1SDValue.html">SDValue</a>, <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * > > & </td>
+ <td class="paramname"><em>RecordedNodes</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>IsPredicateKnownToFail - If we know how and can do so without pushing a scope, evaluate the current node. If the current predicate is known to fail, set Result=true and return anything. If the current predicate is known to pass, set Result=false and return the MatcherIndex to continue with. If the current predicate is unknown, set Result=false and return the MatcherIndex to continue with. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l02126">2126</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SelectionDAGISel_8cpp_source.html#l02095">CheckAndImm()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02056">CheckChildType()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02066">CheckCondCode()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02084">CheckInteger()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02032">CheckNodePredicate()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02038">CheckOpcode()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02108">CheckOrImm()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02025">CheckPatternPredicate()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02014">CheckSame()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02046">CheckType()</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l02073">CheckValueType()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00105">ll
vm::SDValue::getNode()</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00127">llvm::SelectionDAGISel::OPC_CheckAndImm</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00120">llvm::SelectionDAGISel::OPC_CheckChild0Type</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00120">llvm::SelectionDAGISel::OPC_CheckChild1Type</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00120">llvm::SelectionDAGISel::OPC_CheckChild2Type</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00121">llvm::SelectionDAGISel::OPC_CheckChild3Type</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00121">llvm::SelectionDAGISel::OPC_CheckChild4Type</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00121">llvm::SelectionDAGISel::OPC_CheckChild5Type</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00122">llvm::SelectionDAGISel::OPC_CheckChild6Type</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00122">llvm::SelectionDAGISel::OPC_Check
Child7Type</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00124">llvm::SelectionDAGISel::OPC_CheckCondCode</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00123">llvm::SelectionDAGISel::OPC_CheckInteger</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00116">llvm::SelectionDAGISel::OPC_CheckOpcode</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00127">llvm::SelectionDAGISel::OPC_CheckOrImm</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00114">llvm::SelectionDAGISel::OPC_CheckPatternPredicate</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00115">llvm::SelectionDAGISel::OPC_CheckPredicate</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00113">llvm::SelectionDAGISel::OPC_CheckSame</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00118">llvm::SelectionDAGISel::OPC_CheckType</a>, <a class="el" href="SelectionDAGISel_8h_source.html#l00125">llvm::SelectionDAGISel::OPC_CheckValueType</a>, and <a class="
el" href="SelectionDAGISel_8h_source.html#l00045">llvm::SelectionDAGISel::TLI</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l02204">llvm::SelectionDAGISel::SelectCodeCommon()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a32183b39b95b00f771b16930a39d31fb"></a><!-- doxytag: member="SelectionDAGISel.cpp::SplitCriticalSideEffectEdges" ref="a32183b39b95b00f771b16930a39d31fb" args="(Function &Fn, Pass *SDISel)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void SplitCriticalSideEffectEdges </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1Function.html">Function</a> & </td>
+ <td class="paramname"><em>Fn</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1Pass.html">Pass</a> * </td>
+ <td class="paramname"><em>SDISel</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that may trap on it. In this case we have to split the edge so that the path through the predecessor block that doesn't go to the phi block doesn't execute the possibly trapping instruction.</p>
+<p>This is required for correctness, so it must be done at -O0. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l00305">305</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="Function_8h_source.html#l00350">llvm::Function::begin()</a>, <a class="el" href="Constants_8cpp_source.html#l00220">llvm::Constant::canTrap()</a>, <a class="el" href="Casting_8h_source.html#l00233">llvm::dyn_cast()</a>, <a class="el" href="Function_8h_source.html#l00352">llvm::Function::end()</a>, <a class="el" href="Instructions_8h_source.html#l02060">llvm::PHINode::getIncomingBlock()</a>, <a class="el" href="Instructions_8h_source.html#l02045">llvm::PHINode::getIncomingValue()</a>, <a class="el" href="Instructions_8h_source.html#l02041">llvm::PHINode::getNumIncomingValues()</a>, <a class="el" href="InstrTypes_8h_source.html#l00059">llvm::TerminatorInst::getNumSuccessors()</a>, <a class="el" href="BasicBlockUtils_8cpp_source.html#l00242">llvm::GetSuccessorNumber()</a>, <a class="el" href="BasicBlock_8cpp_source.html#l00120">llvm::BasicBlock::getTerminator()</a>, <a class="el" href="ARMBaseInfo_8h_source.html#l00097">llvm::ARM_PROC::I</a>, a
nd <a class="el" href="BreakCriticalEdges_8cpp_source.html#l00174">llvm::SplitCriticalEdge()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l00336">llvm::SelectionDAGISel::runOnMachineFunction()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a8f8de71119ce7ef1af413a5e555b6ca0"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="a8f8de71119ce7ef1af413a5e555b6ca0" args="(NumFastIselFailures,"Number of instructions fast isel failed on")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailures </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of <a class="el" href="SimplifyInstructions_8cpp.html#afbf38da490ab8cea559fee0c9081db06">instructions</a> fast isel failed on" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a012a4ab923e36be9dbe6e9e757749241"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="a012a4ab923e36be9dbe6e9e757749241" args="(NumFastIselSuccess,"Number of instructions fast isel selected")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselSuccess </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of <a class="el" href="SimplifyInstructions_8cpp.html#afbf38da490ab8cea559fee0c9081db06">instructions</a> fast isel selected" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a4fb7080a199ac44b772f3c9869376ff0"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="a4fb7080a199ac44b772f3c9869376ff0" args="(NumFastIselBlocks,"Number of blocks selected entirely by fast isel")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselBlocks </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of blocks selected entirely by fast isel" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a55be46e59a794a2f58b2cf6a9ed96563"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="a55be46e59a794a2f58b2cf6a9ed96563" args="(NumDAGBlocks,"Number of blocks selected using DAG")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumDAGBlocks </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of blocks selected using DAG" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af7d237256bcb5b26f8dc10aa8212a35d"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="af7d237256bcb5b26f8dc10aa8212a35d" args="(NumDAGIselRetries,"Number of times dag isel has to try another path")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumDAGIselRetries </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Number of times dag isel has to try another path" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af25613558512edf86e21db1ed10c1e54"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="af25613558512edf86e21db1ed10c1e54" args="(NumFastIselFailRet,"Fast isel fails on Ret")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailRet </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on Ret" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a0da893f63639896ddeaf910763ada8a1"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="a0da893f63639896ddeaf910763ada8a1" args="(NumFastIselFailBr,"Fast isel fails on Br")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailBr </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on Br" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
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+ <td class="paramname"> </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on FMul" </td>
+ <td class="paramname"> </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on UDiv" </td>
+ <td class="paramname"> </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on SDiv" </td>
+ <td class="paramname"> </td>
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+ <td class="memname">STATISTIC </td>
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+ <td class="paramtype">"Fast isel fails on FDiv" </td>
+ <td class="paramname"> </td>
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+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on URem" </td>
+ <td class="paramname"> </td>
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+ <td>)</td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on SRem" </td>
+ <td class="paramname"> </td>
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
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+ <td class="paramname"> </td>
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname"> </td>
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+ <td class="memname">STATISTIC </td>
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+ <td class="paramtype">"Fast isel fails on Or" </td>
+ <td class="paramname"> </td>
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+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramname"> </td>
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+ <td>)</td>
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+<div class="memproto">
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramname"> </td>
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+ <td>)</td>
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+ <td class="memname">STATISTIC </td>
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+ <td class="paramtype">"Fast isel fails on Load" </td>
+ <td class="paramname"> </td>
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+ <td>)</td>
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+ <td class="memname">STATISTIC </td>
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+ <td class="paramname"> </td>
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+ <td class="memname">STATISTIC </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on Trunc" </td>
+ <td class="paramname"> </td>
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+ <td class="paramname"> </td>
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+ <td class="paramtype">"Fast isel fails on SExt" </td>
+ <td class="paramname"> </td>
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+ <td class="paramtype">"Fast isel fails on FPTrunc" </td>
+ <td class="paramname"> </td>
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+ <td>)</td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on FPExt" </td>
+ <td class="paramname"> </td>
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+ <td>)</td>
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+ <td class="memname">STATISTIC </td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on FPToUI" </td>
+ <td class="paramname"> </td>
+ </tr>
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+ <td></td>
+ <td>)</td>
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on FPToSI" </td>
+ <td class="paramname"> </td>
+ </tr>
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+ <td>)</td>
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+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on UIToFP" </td>
+ <td class="paramname"> </td>
+ </tr>
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+ <td></td>
+ <td>)</td>
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+<div class="memdoc">
+
+</div>
+</div>
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+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailSIToFP </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on SIToFP" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
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+</div>
+<div class="memdoc">
+
+</div>
+</div>
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+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailIntToPtr </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on IntToPtr" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
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+<div class="memdoc">
+
+</div>
+</div>
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+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailPtrToInt </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on PtrToInt" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
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+<div class="memdoc">
+
+</div>
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+<a class="anchor" id="a39ede8bf61467966c69887f44fb9ca55"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="a39ede8bf61467966c69887f44fb9ca55" args="(NumFastIselFailBitCast,"Fast isel fails on BitCast")" -->
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+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailBitCast </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on BitCast" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
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+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on ICmp" </td>
+ <td class="paramname"> </td>
+ </tr>
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+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
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+<div class="memdoc">
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+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on FCmp" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
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+<div class="memproto">
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+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on PHI" </td>
+ <td class="paramname"> </td>
+ </tr>
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+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
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+<div class="memdoc">
+
+</div>
+</div>
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+<div class="memproto">
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+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on Select" </td>
+ <td class="paramname"> </td>
+ </tr>
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+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
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+
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramtype">"Fast isel fails on Call" </td>
+ <td class="paramname"> </td>
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+ <td>)</td>
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on Shl" </td>
+ <td class="paramname"> </td>
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on LShr" </td>
+ <td class="paramname"> </td>
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+ <td>)</td>
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+ <td class="memname">STATISTIC </td>
+ <td>(</td>
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+ <td class="paramname">, </td>
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+ <td class="paramkey"></td>
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+ <td class="paramtype">"Fast isel fails on AShr" </td>
+ <td class="paramname"> </td>
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+ <td>)</td>
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+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailVAArg </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on VAArg" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="aa3475a06a507f8cd93ae2abc675864d3"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="aa3475a06a507f8cd93ae2abc675864d3" args="(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailExtractElement </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on ExtractElement" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="aaee960026d756bbe908af089d3642bff"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="aaee960026d756bbe908af089d3642bff" args="(NumFastIselFailInsertElement,"Fast isel fails on InsertElement")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailInsertElement </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on InsertElement" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="adbd2614b041490602a16b7cd2efc0e71"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="adbd2614b041490602a16b7cd2efc0e71" args="(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailShuffleVector </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on ShuffleVector" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a7c6a7f52bac53b3d1f249397cadce293"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="a7c6a7f52bac53b3d1f249397cadce293" args="(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailExtractValue </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on ExtractValue" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="ab55b879b9fa41a4554ab6d288a659cad"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="ab55b879b9fa41a4554ab6d288a659cad" args="(NumFastIselFailInsertValue,"Fast isel fails on InsertValue")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailInsertValue </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on InsertValue" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a9ee9ed7b727fcdae430ca56d8e58eb39"></a><!-- doxytag: member="SelectionDAGISel.cpp::STATISTIC" ref="a9ee9ed7b727fcdae430ca56d8e58eb39" args="(NumFastIselFailLandingPad,"Fast isel fails on LandingPad")" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">STATISTIC </td>
+ <td>(</td>
+ <td class="paramtype">NumFastIselFailLandingPad </td>
+ <td class="paramname">, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">"Fast isel fails on LandingPad" </td>
+ <td class="paramname"> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="af3cb0eaaeb4f774d7dcb68f956ec78ee"></a><!-- doxytag: member="SelectionDAGISel.cpp::WalkChainUsers" ref="af3cb0eaaeb4f774d7dcb68f956ec78ee" args="(const SDNode *ChainedNode, SmallVectorImpl< SDNode * > &ChainedNodesInPattern, SmallVectorImpl< SDNode * > &InteriorChainedNodes)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">static <a class="el" href="SelectionDAGISel_8cpp.html#ac6cd0b51896db5749a4e980d3ff455ee">ChainResult</a> WalkChainUsers </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * </td>
+ <td class="paramname"><em>ChainedNode</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl</a>< <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * > & </td>
+ <td class="paramname"><em>ChainedNodesInPattern</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype"><a class="el" href="classllvm_1_1SmallVectorImpl.html">SmallVectorImpl</a>< <a class="el" href="classllvm_1_1SDNode.html">SDNode</a> * > & </td>
+ <td class="paramname"><em>InteriorChainedNodes</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td><code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>WalkChainUsers - Walk down the users of the specified chained node that is part of the pattern we're matching, looking at all of the users we find. This determines whether something is an interior node, whether we have a non-pattern node in between two pattern nodes (which prevent folding because it would induce a cycle) and whether we have a TokenFactor node sandwiched between pattern nodes (in which case the TF becomes part of the pattern).</p>
+<p>The walk we do here is guaranteed to be small because we quickly get down to already selected nodes "below" us. </p>
+
+<p>Definition at line <a class="el" href="SelectionDAGISel_8cpp_source.html#l01790">1790</a> of file <a class="el" href="SelectionDAGISel_8cpp_source.html">SelectionDAGISel.cpp</a>.</p>
+
+<p>References <a class="el" href="SmallVector_8h_source.html#l00111">llvm::SmallVectorTemplateCommon< T, typename >::begin()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00163">llvm::ISD::CopyFromReg</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00158">llvm::ISD::CopyToReg</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l01776">CR_InducesCycle</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l01777">CR_LeadsToInteriorNode</a>, <a class="el" href="SelectionDAGISel_8cpp_source.html#l01775">CR_Simple</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00521">llvm::ISD::EH_LABEL</a>, <a class="el" href="SmallVector_8h_source.html#l00113">llvm::SmallVectorTemplateCommon< T, typename >::end()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00411">llvm::SDNode::getNodeId()</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00363">llvm::SDNode::getOpcode()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00572">llvm
::ISD::HANDLENODE</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00516">llvm::ISD::INLINEASM</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00378">llvm::SDNode::isMachineOpcode()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00642">llvm::ISD::LIFETIME_END</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00642">llvm::ISD::LIFETIME_START</a>, <a class="el" href="ValueTypes_8h_source.html#l00038">llvm::MVT::Other</a>, <a class="el" href="SmallVector_8h_source.html#l00231">llvm::SmallVectorTemplateBase< T, isPodLike >::push_back()</a>, <a class="el" href="ISDOpcodes_8h_source.html#l00050">llvm::ISD::TokenFactor</a>, <a class="el" href="SelectionDAGNodes_8h_source.html#l00482">llvm::SDNode::use_begin()</a>, and <a class="el" href="SelectionDAGNodes_8h_source.html#l00486">llvm::SDNode::use_end()</a>.</p>
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l01908">HandleMergeInputChains()</a>.</p>
+
+</div>
+</div>
+<hr/><h2>Variable Documentation</h2>
+<a class="anchor" id="a2ffa56bb0fe093d549f7c5b8cb32cc98"></a><!-- doxytag: member="SelectionDAGISel.cpp::defaultListDAGScheduler" ref="a2ffa56bb0fe093d549f7c5b8cb32cc98" args="("default","Best scheduler for the target", createDefaultScheduler)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a> <a class="el" href="SelectionDAGISel_8cpp.html#a2ffa56bb0fe093d549f7c5b8cb32cc98">defaultListDAGScheduler</a>("default","Best scheduler for the target", createDefaultScheduler)<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a9d50504a9daa484cb9ffe06b0a4e8d0c"></a><!-- doxytag: member="SelectionDAGISel.cpp::EnableFastISelAbort" ref="a9d50504a9daa484cb9ffe06b0a4e8d0c" args="("fast-isel-abort", cl::Hidden, cl::desc("Enable abort calls when \"fast\" instruction fails"))" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="SelectionDAGISel_8cpp.html#a9d50504a9daa484cb9ffe06b0a4e8d0c">EnableFastISelAbort</a>("fast-isel-abort", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Enable abort <a class="el" href="Scalar_2SimplifyLibCalls_8cpp.html#a4c349cd4b664546b9b9eef619d58c12d">calls</a> when \"fast\" instruction fails"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l00336">llvm::SelectionDAGISel::runOnMachineFunction()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="ad64839db51b02e2d40ec293faabeeec2"></a><!-- doxytag: member="SelectionDAGISel.cpp::EnableFastISelVerbose" ref="ad64839db51b02e2d40ec293faabeeec2" args="("fast-isel-verbose", cl::Hidden, cl::desc("Enable verbose messages in the \"fast\" ""instruction selector"))" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="SelectionDAGISel_8cpp.html#ad64839db51b02e2d40ec293faabeeec2">EnableFastISelVerbose</a>("fast-isel-verbose", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Enable verbose messages in the \"fast\" ""instruction selector"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l00336">llvm::SelectionDAGISel::runOnMachineFunction()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="a086b60310efb455c4b210eeae130b974"></a><!-- doxytag: member="SelectionDAGISel.cpp::EnableFastISelVerbose2" ref="a086b60310efb455c4b210eeae130b974" args="("fast-isel-verbose2", cl::Hidden, cl::desc("Enable extra verbose messages in the \"fast\" ""instruction selector"))" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="SelectionDAGISel_8cpp.html#a086b60310efb455c4b210eeae130b974">EnableFastISelVerbose2</a>("fast-isel-verbose2", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Enable extra verbose messages in the \"fast\" ""instruction selector"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="afabfb264c515ec09675c6a53ecf95785"></a><!-- doxytag: member="SelectionDAGISel.cpp::ISHeuristic" ref="afabfb264c515ec09675c6a53ecf95785" args="("pre-RA-sched", cl::init(&createDefaultScheduler), cl::desc("Instruction schedulers available (before register"" allocation):"))" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><RegisterScheduler::FunctionPassCtor, <a class="el" href="SimplifyInstructions_8cpp.html#a6dd713bd88673625bb181528a61bdc85">false</a>, <a class="el" href="classllvm_1_1RegisterPassParser.html">RegisterPassParser</a><<a class="el" href="classllvm_1_1RegisterScheduler.html">RegisterScheduler</a>> > <a class="el" href="SelectionDAGISel_8cpp.html#afabfb264c515ec09675c6a53ecf95785">ISHeuristic</a>("pre-RA-sched", cl::init(&createDefaultScheduler), <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Instruction schedulers available (before register"" <a class="el" href="StrongPHIElimination_8cpp.html#a1a0492b9a49bb2dab78ace5b3298fad6">allocation</a>):"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+<p>ISHeuristic command line option for instruction schedulers. </p>
+
+</div>
+</div>
+<a class="anchor" id="a882ae4a44bdaba10b04f867cc59d0b12"></a><!-- doxytag: member="SelectionDAGISel.cpp::UseMBPI" ref="a882ae4a44bdaba10b04f867cc59d0b12" args="("use-mbpi", cl::desc("use Machine Branch Probability Info"), cl::init(true), cl::Hidden)" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="SelectionDAGISel_8cpp.html#a882ae4a44bdaba10b04f867cc59d0b12">UseMBPI</a>("use-mbpi", cl::desc("use Machine Branch Probability Info"), cl::init(<a class="el" href="LoopSimplify_8cpp.html#a13f020c6a40eb04f1b4f9ddfbb004ce0">true</a>), cl::Hidden)<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+<p>Referenced by <a class="el" href="SelectionDAGISel_8cpp_source.html#l00287">llvm::SelectionDAGISel::getAnalysisUsage()</a>, and <a class="el" href="SelectionDAGISel_8cpp_source.html#l00336">llvm::SelectionDAGISel::runOnMachineFunction()</a>.</p>
+
+</div>
+</div>
+<a class="anchor" id="aa0a1387d2f4f4c555f6e70f8772e2b36"></a><!-- doxytag: member="SelectionDAGISel.cpp::ViewDAGCombine1" ref="aa0a1387d2f4f4c555f6e70f8772e2b36" args="("view-dag-combine1-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the first ""dag combine pass"))" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="SelectionDAGISel_8cpp.html#aa0a1387d2f4f4c555f6e70f8772e2b36">ViewDAGCombine1</a>("view-dag-combine1-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show dags before the first ""dag combine <a class="el" href="TwoAddressInstructionPass_8cpp.html#a34b5cf133e2453a532a504197fec9171">pass</a>"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a5eb1e524620af2b978b96889db819cd5"></a><!-- doxytag: member="SelectionDAGISel.cpp::ViewDAGCombine2" ref="a5eb1e524620af2b978b96889db819cd5" args="("view-dag-combine2-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the second ""dag combine pass"))" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="SelectionDAGISel_8cpp.html#a5eb1e524620af2b978b96889db819cd5">ViewDAGCombine2</a>("view-dag-combine2-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show dags before the second ""dag combine <a class="el" href="TwoAddressInstructionPass_8cpp.html#a34b5cf133e2453a532a504197fec9171">pass</a>"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a9493966ca8816c129a6afef7ef0b0866"></a><!-- doxytag: member="SelectionDAGISel.cpp::ViewDAGCombineLT" ref="a9493966ca8816c129a6afef7ef0b0866" args="("view-dag-combine-lt-dags", cl::Hidden, cl::desc("Pop up a window to show dags before the post legalize types"" dag combine pass"))" -->
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="classllvm_1_1cl_1_1opt.html">cl::opt</a><<a class="el" href="X86DisassemblerDecoder_8c.html#a6156fe0b594c9754f386f6c6a30c8165">bool</a>> <a class="el" href="SelectionDAGISel_8cpp.html#a9493966ca8816c129a6afef7ef0b0866">ViewDAGCombineLT</a>("view-dag-combine-lt-dags", cl::Hidden, <a class="el" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>("Pop up a window to show dags before the post legalize types"" dag combine <a class="el" href="TwoAddressInstructionPass_8cpp.html#a34b5cf133e2453a532a504197fec9171">pass</a>"))<code> [static]</code></td>
+ </tr>
+ </table>
+</div>
+<div class="memdoc">
+
+</div>
+</div>
+<a class="anchor" id="a1020617e313312866c30e376a9e4558f"></a><!-- doxytag: member="SelectionDAGISel.cpp::ViewISelDAGs" ref="a1020617e313312866c30e376a9e4558f" args="("view-isel-dags", cl::Hidden, cl::desc("Pop up a window to show isel dags as they are selected"))" -->
+<div class="memitem">
+<div class="memproto">
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