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Tanya Lattner
tonic at nondot.org
Thu Dec 20 22:58:17 PST 2012
Added: www-releases/trunk/3.2/docs/doxygen/html/ARMFrameLowering_8cpp_source.html
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+<title>LLVM: ARMFrameLowering.cpp Source File</title>
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+ <li class="navelem"><a class="el" href="dir_8a55ec9894173378e0d08f27f306eeee.html">Target</a> </li>
+ <li class="navelem"><a class="el" href="dir_579de1806e7c3f5ec4b2837753e33796.html">ARM</a> </li>
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+<div class="title">ARMFrameLowering.cpp</div> </div>
+</div>
+<div class="contents">
+<a href="ARMFrameLowering_8cpp.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//===-- ARMFrameLowering.cpp - ARM Frame Information ----------------------===//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file contains the ARM implementation of TargetFrameLowering class.</span>
+<a name="l00011"></a>00011 <span class="comment">//</span>
+<a name="l00012"></a>00012 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00013"></a>00013
+<a name="l00014"></a>00014 <span class="preprocessor">#include "<a class="code" href="ARMFrameLowering_8h.html">ARMFrameLowering.h</a>"</span>
+<a name="l00015"></a>00015 <span class="preprocessor">#include "<a class="code" href="ARMBaseInstrInfo_8h.html">ARMBaseInstrInfo.h</a>"</span>
+<a name="l00016"></a>00016 <span class="preprocessor">#include "<a class="code" href="ARMBaseRegisterInfo_8h.html">ARMBaseRegisterInfo.h</a>"</span>
+<a name="l00017"></a>00017 <span class="preprocessor">#include "<a class="code" href="ARMMachineFunctionInfo_8h.html">ARMMachineFunctionInfo.h</a>"</span>
+<a name="l00018"></a>00018 <span class="preprocessor">#include "<a class="code" href="CallingConv_8h.html">llvm/CallingConv.h</a>"</span>
+<a name="l00019"></a>00019 <span class="preprocessor">#include "<a class="code" href="Function_8h.html">llvm/Function.h</a>"</span>
+<a name="l00020"></a>00020 <span class="preprocessor">#include "<a class="code" href="ARMAddressingModes_8h.html">MCTargetDesc/ARMAddressingModes.h</a>"</span>
+<a name="l00021"></a>00021 <span class="preprocessor">#include "<a class="code" href="Function_8h.html">llvm/Function.h</a>"</span>
+<a name="l00022"></a>00022 <span class="preprocessor">#include "<a class="code" href="MachineFrameInfo_8h.html">llvm/CodeGen/MachineFrameInfo.h</a>"</span>
+<a name="l00023"></a>00023 <span class="preprocessor">#include "<a class="code" href="MachineFunction_8h.html">llvm/CodeGen/MachineFunction.h</a>"</span>
+<a name="l00024"></a>00024 <span class="preprocessor">#include "<a class="code" href="MachineInstrBuilder_8h.html">llvm/CodeGen/MachineInstrBuilder.h</a>"</span>
+<a name="l00025"></a>00025 <span class="preprocessor">#include "<a class="code" href="MachineRegisterInfo_8h.html">llvm/CodeGen/MachineRegisterInfo.h</a>"</span>
+<a name="l00026"></a>00026 <span class="preprocessor">#include "<a class="code" href="RegisterScavenging_8h.html">llvm/CodeGen/RegisterScavenging.h</a>"</span>
+<a name="l00027"></a>00027 <span class="preprocessor">#include "<a class="code" href="TargetOptions_8h.html">llvm/Target/TargetOptions.h</a>"</span>
+<a name="l00028"></a>00028 <span class="preprocessor">#include "<a class="code" href="CommandLine_8h.html">llvm/Support/CommandLine.h</a>"</span>
+<a name="l00029"></a>00029
+<a name="l00030"></a>00030 <span class="keyword">using namespace </span>llvm;
+<a name="l00031"></a>00031
+<a name="l00032"></a>00032 <span class="keyword">static</span> <a class="code" href="classllvm_1_1cl_1_1opt.html">cl::opt<bool></a>
+<a name="l00033"></a>00033 <a class="code" href="ARMFrameLowering_8cpp.html#a714d5787e4c9238659853436e5fcd83e">SpillAlignedNEONRegs</a>(<span class="stringliteral">"align-neon-spills"</span>, <a class="code" href="namespacellvm_1_1cl.html#a68075925a54790e71ca790e1d4f21a40a263ac008d8d31f13ce460395fc4cf7e6">cl::Hidden</a>, <a class="code" href="namespacellvm_1_1cl.html#a10a041239ae1870cfcc064bfaa79fb65">cl::init</a>(<span class="keyword">true</span>),
+<a name="l00034"></a>00034 <a class="code" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>(<span class="stringliteral">"Align ARM NEON spills in prolog and epilog"</span>));
+<a name="l00035"></a>00035
+<a name="l00036"></a>00036 <span class="keyword">static</span> <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a>
+<a name="l00037"></a>00037 <a class="code" href="ARMFrameLowering_8cpp.html#a0409e368b6e75e93e77f9c29a03edbe9">skipAlignedDPRCS2Spills</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>,
+<a name="l00038"></a>00038 <span class="keywordtype">unsigned</span> NumAlignedDPRCS2Regs);
+<a name="l00039"></a>00039 <span class="comment"></span>
+<a name="l00040"></a>00040 <span class="comment">/// hasFP - Return true if the specified function should have a dedicated frame</span>
+<a name="l00041"></a>00041 <span class="comment">/// pointer register. This is true if the function has variable sized allocas</span>
+<a name="l00042"></a>00042 <span class="comment">/// or if frame pointer elimination is disabled.</span>
+<a name="l00043"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#a9c8349fdf1c2f7ed13cd1a1bd1aeb19e">00043</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a9c8349fdf1c2f7ed13cd1a1bd1aeb19e">ARMFrameLowering::hasFP</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF)<span class="keyword"> const </span>{
+<a name="l00044"></a>00044 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *RegInfo = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a70b47eca6a99c87b81f4c1b1455dc090">getRegisterInfo</a>();
+<a name="l00045"></a>00045
+<a name="l00046"></a>00046 <span class="comment">// iOS requires FP not to be clobbered for backtracing purpose.</span>
+<a name="l00047"></a>00047 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a80f7cdbc91b73599f8319c4a88c7ca18">isTargetIOS</a>())
+<a name="l00048"></a>00048 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00049"></a>00049
+<a name="l00050"></a>00050 <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l00051"></a>00051 <span class="comment">// Always eliminate non-leaf frame pointers.</span>
+<a name="l00052"></a>00052 <span class="keywordflow">return</span> ((MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ab1fb67187fc37e569cc5171cbebba873">Options</a>.<a class="code" href="classllvm_1_1TargetOptions.html#a55b913089f1134db4cc1ea6e677c62bd">DisableFramePointerElim</a>(MF) &&
+<a name="l00053"></a>00053 MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#ad104abdabbcb68deacc60c0aea1bca34" title="hasCalls - Return true if the current function has any function calls.">hasCalls</a>()) ||
+<a name="l00054"></a>00054 RegInfo-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#adf8e30b3e759b1283c5fbda668190ee6">needsStackRealignment</a>(MF) ||
+<a name="l00055"></a>00055 MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a5cd76eb2aeed3ae46da1bb1b132f1831">hasVarSizedObjects</a>() ||
+<a name="l00056"></a>00056 MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a48b4b361d757d1ab48f783b8875712c1">isFrameAddressTaken</a>());
+<a name="l00057"></a>00057 }
+<a name="l00058"></a>00058 <span class="comment"></span>
+<a name="l00059"></a>00059 <span class="comment">/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is</span>
+<a name="l00060"></a>00060 <span class="comment">/// not required, we reserve argument space for call sites in the function</span>
+<a name="l00061"></a>00061 <span class="comment">/// immediately on entry to the current function. This eliminates the need for</span>
+<a name="l00062"></a>00062 <span class="comment">/// add/sub sp brackets around call sites. Returns true if the call frame is</span>
+<a name="l00063"></a>00063 <span class="comment">/// included as part of the stack frame.</span>
+<a name="l00064"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#a8f1ddf69e36ed0354ae69fedd3fed9a5">00064</a> <span class="comment"></span><span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a8f1ddf69e36ed0354ae69fedd3fed9a5">ARMFrameLowering::hasReservedCallFrame</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF)<span class="keyword"> const </span>{
+<a name="l00065"></a>00065 <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *FFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l00066"></a>00066 <span class="keywordtype">unsigned</span> CFSize = FFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a00e048d1d905fa65ee3377d99d4f2ae3">getMaxCallFrameSize</a>();
+<a name="l00067"></a>00067 <span class="comment">// It's not always a good idea to include the call frame as part of the</span>
+<a name="l00068"></a>00068 <span class="comment">// stack frame. ARM (especially Thumb) has small immediate offset to</span>
+<a name="l00069"></a>00069 <span class="comment">// address the stack frame. So a large call frame can cause poor codegen</span>
+<a name="l00070"></a>00070 <span class="comment">// and may even makes it impossible to scavenge a register.</span>
+<a name="l00071"></a>00071 <span class="keywordflow">if</span> (CFSize >= ((1 << 12) - 1) / 2) <span class="comment">// Half of imm12</span>
+<a name="l00072"></a>00072 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00073"></a>00073
+<a name="l00074"></a>00074 <span class="keywordflow">return</span> !MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a5cd76eb2aeed3ae46da1bb1b132f1831">hasVarSizedObjects</a>();
+<a name="l00075"></a>00075 }
+<a name="l00076"></a>00076 <span class="comment"></span>
+<a name="l00077"></a>00077 <span class="comment">/// canSimplifyCallFramePseudos - If there is a reserved call frame, the</span>
+<a name="l00078"></a>00078 <span class="comment">/// call frame pseudos can be simplified. Unlike most targets, having a FP</span>
+<a name="l00079"></a>00079 <span class="comment">/// is not sufficient here since we still may reference some objects via SP</span>
+<a name="l00080"></a>00080 <span class="comment">/// even when FP is available in Thumb2 mode.</span>
+<a name="l00081"></a>00081 <span class="comment"></span><span class="keywordtype">bool</span>
+<a name="l00082"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#a68fb321e1ddcf431572aa4d374c3baad">00082</a> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a68fb321e1ddcf431572aa4d374c3baad">ARMFrameLowering::canSimplifyCallFramePseudos</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF)<span class="keyword"> const </span>{
+<a name="l00083"></a>00083 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a8f1ddf69e36ed0354ae69fedd3fed9a5">hasReservedCallFrame</a>(MF) || MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a5cd76eb2aeed3ae46da1bb1b132f1831">hasVarSizedObjects</a>();
+<a name="l00084"></a>00084 }
+<a name="l00085"></a>00085
+<a name="l00086"></a><a class="code" href="ARMFrameLowering_8cpp.html#a58fe9caa8dcb8186dc09761b76df7b5c">00086</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="ARMFrameLowering_8cpp.html#a58fe9caa8dcb8186dc09761b76df7b5c">isCalleeSavedRegister</a>(<span class="keywordtype">unsigned</span> <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>, <span class="keyword">const</span> uint16_t *CSRegs) {
+<a name="l00087"></a>00087 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; CSRegs[i]; ++i)
+<a name="l00088"></a>00088 <span class="keywordflow">if</span> (Reg == CSRegs[i])
+<a name="l00089"></a>00089 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00090"></a>00090 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00091"></a>00091 }
+<a name="l00092"></a>00092
+<a name="l00093"></a><a class="code" href="ARMFrameLowering_8cpp.html#adcf1477a493b2d105f7f298b145bb188">00093</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="ARMFrameLowering_8cpp.html#adcf1477a493b2d105f7f298b145bb188">isCSRestore</a>(<a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>,
+<a name="l00094"></a>00094 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a> &TII,
+<a name="l00095"></a>00095 <span class="keyword">const</span> uint16_t *CSRegs) {
+<a name="l00096"></a>00096 <span class="comment">// Integer spill area is handled with "pop".</span>
+<a name="l00097"></a>00097 <span class="keywordflow">if</span> (MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == ARM::LDMIA_RET ||
+<a name="l00098"></a>00098 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == ARM::t2LDMIA_RET ||
+<a name="l00099"></a>00099 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == ARM::LDMIA_UPD ||
+<a name="l00100"></a>00100 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == ARM::t2LDMIA_UPD ||
+<a name="l00101"></a>00101 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == ARM::VLDMDIA_UPD) {
+<a name="l00102"></a>00102 <span class="comment">// The first two operands are predicates. The last two are</span>
+<a name="l00103"></a>00103 <span class="comment">// imp-def and imp-use of SP. Check everything in between.</span>
+<a name="l00104"></a>00104 <span class="keywordflow">for</span> (<span class="keywordtype">int</span> i = 5, e = MI-><a class="code" href="classllvm_1_1MachineInstr.html#a7b5fe96d88954efc855e6c466207e535">getNumOperands</a>(); i != e; ++i)
+<a name="l00105"></a>00105 <span class="keywordflow">if</span> (!<a class="code" href="ARMFrameLowering_8cpp.html#a58fe9caa8dcb8186dc09761b76df7b5c">isCalleeSavedRegister</a>(MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(i).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>(), CSRegs))
+<a name="l00106"></a>00106 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00107"></a>00107 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00108"></a>00108 }
+<a name="l00109"></a>00109 <span class="keywordflow">if</span> ((MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == ARM::LDR_POST_IMM ||
+<a name="l00110"></a>00110 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == ARM::LDR_POST_REG ||
+<a name="l00111"></a>00111 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a242314c0ae0147d1a7ef54c9bc312616">getOpcode</a>() == ARM::t2LDR_POST) &&
+<a name="l00112"></a>00112 <a class="code" href="ARMFrameLowering_8cpp.html#a58fe9caa8dcb8186dc09761b76df7b5c">isCalleeSavedRegister</a>(MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(0).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>(), CSRegs) &&
+<a name="l00113"></a>00113 MI-><a class="code" href="classllvm_1_1MachineInstr.html#a302e45878c6dc1714334c7ce96d56846">getOperand</a>(1).<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>() == ARM::SP)
+<a name="l00114"></a>00114 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00115"></a>00115
+<a name="l00116"></a>00116 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00117"></a>00117 }
+<a name="l00118"></a>00118
+<a name="l00119"></a>00119 <span class="keyword">static</span> <span class="keywordtype">void</span>
+<a name="l00120"></a><a class="code" href="ARMFrameLowering_8cpp.html#a9ab4b7db48660c4412dcd120e7e13648">00120</a> <a class="code" href="ARMFrameLowering_8cpp.html#a9ab4b7db48660c4412dcd120e7e13648">emitSPUpdate</a>(<span class="keywordtype">bool</span> isARM,
+<a name="l00121"></a>00121 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB, <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> &MBBI,
+<a name="l00122"></a>00122 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl, <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a> &TII,
+<a name="l00123"></a>00123 <span class="keywordtype">int</span> NumBytes, <span class="keywordtype">unsigned</span> MIFlags = <a class="code" href="classllvm_1_1MachineInstr.html#aafacf84de1cb994a92dc045f4aa1d518a75967179a013c48b7d5b1690cb0b47cc">MachineInstr::NoFlags</a>) {
+<a name="l00124"></a>00124 <span class="keywordflow">if</span> (isARM)
+<a name="l00125"></a>00125 <a class="code" href="namespacellvm.html#a402aa8ec2571af98e3b5871721c6f642">emitARMRegPlusImmediate</a>(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
+<a name="l00126"></a>00126 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6a8b2ef77967dee1220cc6ee5aee595e11">ARMCC::AL</a>, 0, TII, MIFlags);
+<a name="l00127"></a>00127 <span class="keywordflow">else</span>
+<a name="l00128"></a>00128 <a class="code" href="namespacellvm.html#ae59f84da43ddc1b247716625b3b31dfb">emitT2RegPlusImmediate</a>(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
+<a name="l00129"></a>00129 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6a8b2ef77967dee1220cc6ee5aee595e11">ARMCC::AL</a>, 0, TII, MIFlags);
+<a name="l00130"></a>00130 }
+<a name="l00131"></a>00131
+<a name="l00132"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#ab32bf14ad0d8ab098d171a3abc45c78a">00132</a> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#ab32bf14ad0d8ab098d171a3abc45c78a">ARMFrameLowering::emitPrologue</a>(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF)<span class="keyword"> const </span>{
+<a name="l00133"></a>00133 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB = MF.<a class="code" href="classllvm_1_1MachineFunction.html#af562445435f18637f07676da054ba02c">front</a>();
+<a name="l00134"></a>00134 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MBBI = MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>();
+<a name="l00135"></a>00135 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l00136"></a>00136 <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l00137"></a>00137 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html">ARMBaseRegisterInfo</a> *RegInfo =
+<a name="l00138"></a>00138 <span class="keyword">static_cast<</span><span class="keyword">const </span><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html">ARMBaseRegisterInfo</a>*<span class="keyword">></span>(MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a70b47eca6a99c87b81f4c1b1455dc090">getRegisterInfo</a>());
+<a name="l00139"></a>00139 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a> &TII =
+<a name="l00140"></a>00140 *<span class="keyword">static_cast<</span><span class="keyword">const </span><a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a>*<span class="keyword">></span>(MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>());
+<a name="l00141"></a>00141 assert(!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>() &&
+<a name="l00142"></a>00142 <span class="stringliteral">"This emitPrologue does not support Thumb1!"</span>);
+<a name="l00143"></a>00143 <span class="keywordtype">bool</span> isARM = !AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>();
+<a name="l00144"></a>00144 <span class="keywordtype">unsigned</span> VARegSaveSize = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a81e3b6570ae669e775597d683027deea">getVarArgsRegSaveSize</a>();
+<a name="l00145"></a>00145 <span class="keywordtype">unsigned</span> NumBytes = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a34874094b3ba8b56fd68801250f77183">getStackSize</a>();
+<a name="l00146"></a>00146 <span class="keyword">const</span> std::vector<CalleeSavedInfo> &CSI = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a5296aac05a8ccceb0d89d449611722d3">getCalleeSavedInfo</a>();
+<a name="l00147"></a>00147 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = MBBI != MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#acbc921830578e2741be6549db716c0ce">end</a>() ? MBBI->getDebugLoc() : <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a>();
+<a name="l00148"></a>00148 <span class="keywordtype">unsigned</span> FramePtr = RegInfo->getFrameRegister(MF);
+<a name="l00149"></a>00149
+<a name="l00150"></a>00150 <span class="comment">// Determine the sizes of each callee-save spill areas and record which frame</span>
+<a name="l00151"></a>00151 <span class="comment">// belongs to which callee-save spill areas.</span>
+<a name="l00152"></a>00152 <span class="keywordtype">unsigned</span> GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
+<a name="l00153"></a>00153 <span class="keywordtype">int</span> FramePtrSpillFI = 0;
+<a name="l00154"></a>00154 <span class="keywordtype">int</span> D8SpillFI = 0;
+<a name="l00155"></a>00155
+<a name="l00156"></a>00156 <span class="comment">// All calls are tail calls in GHC calling conv, and functions have no</span>
+<a name="l00157"></a>00157 <span class="comment">// prologue/epilogue.</span>
+<a name="l00158"></a>00158 <span class="keywordflow">if</span> (MF.<a class="code" href="classllvm_1_1MachineFunction.html#ad784a6594990530bffb2018aeeed56f3">getFunction</a>()-><a class="code" href="classllvm_1_1Function.html#af4d5ada526cdf057f5f29047e058187d">getCallingConv</a>() == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974a8e8dc64aad833bd23d07d3384522575e">CallingConv::GHC</a>)
+<a name="l00159"></a>00159 <span class="keywordflow">return</span>;
+<a name="l00160"></a>00160
+<a name="l00161"></a>00161 <span class="comment">// Allocate the vararg register save area. This is not counted in NumBytes.</span>
+<a name="l00162"></a>00162 <span class="keywordflow">if</span> (VARegSaveSize)
+<a name="l00163"></a>00163 <a class="code" href="ARMFrameLowering_8cpp.html#a9ab4b7db48660c4412dcd120e7e13648">emitSPUpdate</a>(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
+<a name="l00164"></a>00164 <a class="code" href="classllvm_1_1MachineInstr.html#aafacf84de1cb994a92dc045f4aa1d518a78f1067d270179dff7915b90a03ce237">MachineInstr::FrameSetup</a>);
+<a name="l00165"></a>00165
+<a name="l00166"></a>00166 <span class="keywordflow">if</span> (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ac39b5595d3a23db77d972ba5b37c4348">hasStackFrame</a>()) {
+<a name="l00167"></a>00167 <span class="keywordflow">if</span> (NumBytes != 0)
+<a name="l00168"></a>00168 <a class="code" href="ARMFrameLowering_8cpp.html#a9ab4b7db48660c4412dcd120e7e13648">emitSPUpdate</a>(isARM, MBB, MBBI, dl, TII, -NumBytes,
+<a name="l00169"></a>00169 <a class="code" href="classllvm_1_1MachineInstr.html#aafacf84de1cb994a92dc045f4aa1d518a78f1067d270179dff7915b90a03ce237">MachineInstr::FrameSetup</a>);
+<a name="l00170"></a>00170 <span class="keywordflow">return</span>;
+<a name="l00171"></a>00171 }
+<a name="l00172"></a>00172
+<a name="l00173"></a>00173 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = CSI.size(); i != e; ++i) {
+<a name="l00174"></a>00174 <span class="keywordtype">unsigned</span> <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a> = CSI[i].getReg();
+<a name="l00175"></a>00175 <span class="keywordtype">int</span> FI = CSI[i].getFrameIdx();
+<a name="l00176"></a>00176 <span class="keywordflow">switch</span> (Reg) {
+<a name="l00177"></a>00177 <span class="keywordflow">case</span> ARM::R4:
+<a name="l00178"></a>00178 <span class="keywordflow">case</span> ARM::R5:
+<a name="l00179"></a>00179 <span class="keywordflow">case</span> ARM::R6:
+<a name="l00180"></a>00180 <span class="keywordflow">case</span> ARM::R7:
+<a name="l00181"></a>00181 <span class="keywordflow">case</span> ARM::LR:
+<a name="l00182"></a>00182 <span class="keywordflow">if</span> (Reg == FramePtr)
+<a name="l00183"></a>00183 FramePtrSpillFI = FI;
+<a name="l00184"></a>00184 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a348450c69cba2dd3545856bcf52949f2">addGPRCalleeSavedArea1Frame</a>(FI);
+<a name="l00185"></a>00185 GPRCS1Size += 4;
+<a name="l00186"></a>00186 <span class="keywordflow">break</span>;
+<a name="l00187"></a>00187 <span class="keywordflow">case</span> ARM::R8:
+<a name="l00188"></a>00188 <span class="keywordflow">case</span> ARM::R9:
+<a name="l00189"></a>00189 <span class="keywordflow">case</span> ARM::R10:
+<a name="l00190"></a>00190 <span class="keywordflow">case</span> ARM::R11:
+<a name="l00191"></a>00191 <span class="keywordflow">if</span> (Reg == FramePtr)
+<a name="l00192"></a>00192 FramePtrSpillFI = FI;
+<a name="l00193"></a>00193 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a80f7cdbc91b73599f8319c4a88c7ca18">isTargetIOS</a>()) {
+<a name="l00194"></a>00194 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a5a44123a272e87e59ccf2680c0d22002">addGPRCalleeSavedArea2Frame</a>(FI);
+<a name="l00195"></a>00195 GPRCS2Size += 4;
+<a name="l00196"></a>00196 } <span class="keywordflow">else</span> {
+<a name="l00197"></a>00197 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a348450c69cba2dd3545856bcf52949f2">addGPRCalleeSavedArea1Frame</a>(FI);
+<a name="l00198"></a>00198 GPRCS1Size += 4;
+<a name="l00199"></a>00199 }
+<a name="l00200"></a>00200 <span class="keywordflow">break</span>;
+<a name="l00201"></a>00201 <span class="keywordflow">default</span>:
+<a name="l00202"></a>00202 <span class="comment">// This is a DPR. Exclude the aligned DPRCS2 spills.</span>
+<a name="l00203"></a>00203 <span class="keywordflow">if</span> (Reg == <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a>)
+<a name="l00204"></a>00204 D8SpillFI = FI;
+<a name="l00205"></a>00205 <span class="keywordflow">if</span> (<a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg < ARM::D8 || Reg ></a>= <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a> + AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a70543217b38bd2e8dc926e315a78c930">getNumAlignedDPRCS2Regs</a>()) {
+<a name="l00206"></a>00206 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a74d475c5d09e918aeff9de6592a77afd">addDPRCalleeSavedAreaFrame</a>(FI);
+<a name="l00207"></a>00207 DPRCSSize += 8;
+<a name="l00208"></a>00208 }
+<a name="l00209"></a>00209 }
+<a name="l00210"></a>00210 }
+<a name="l00211"></a>00211
+<a name="l00212"></a>00212 <span class="comment">// Move past area 1.</span>
+<a name="l00213"></a>00213 <span class="keywordflow">if</span> (GPRCS1Size > 0) MBBI++;
+<a name="l00214"></a>00214
+<a name="l00215"></a>00215 <span class="comment">// Set FP to point to the stack slot that contains the previous FP.</span>
+<a name="l00216"></a>00216 <span class="comment">// For iOS, FP is R7, which has now been stored in spill area 1.</span>
+<a name="l00217"></a>00217 <span class="comment">// Otherwise, if this is not iOS, all the callee-saved registers go</span>
+<a name="l00218"></a>00218 <span class="comment">// into spill area 1, including the FP in R11. In either case, it is</span>
+<a name="l00219"></a>00219 <span class="comment">// now safe to emit this assignment.</span>
+<a name="l00220"></a>00220 <span class="keywordtype">bool</span> HasFP = <a class="code" href="classllvm_1_1ARMFrameLowering.html#a9c8349fdf1c2f7ed13cd1a1bd1aeb19e">hasFP</a>(MF);
+<a name="l00221"></a>00221 <span class="keywordflow">if</span> (HasFP) {
+<a name="l00222"></a>00222 <span class="keywordtype">unsigned</span> ADDriOpc = !AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>() ? ARM::ADDri : ARM::t2ADDri;
+<a name="l00223"></a>00223 <a class="code" href="classllvm_1_1MachineInstrBuilder.html">MachineInstrBuilder</a> MIB =
+<a name="l00224"></a>00224 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
+<a name="l00225"></a>00225 .addFrameIndex(FramePtrSpillFI).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(0)
+<a name="l00226"></a>00226 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a66fb0307f35f874cb65deb84eea9553f">setMIFlag</a>(<a class="code" href="classllvm_1_1MachineInstr.html#aafacf84de1cb994a92dc045f4aa1d518a78f1067d270179dff7915b90a03ce237">MachineInstr::FrameSetup</a>);
+<a name="l00227"></a>00227 <a class="code" href="namespacellvm.html#a8b9edb9ece6ca4b10c73ae93a487c600">AddDefaultCC</a>(<a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(MIB));
+<a name="l00228"></a>00228 }
+<a name="l00229"></a>00229
+<a name="l00230"></a>00230 <span class="comment">// Move past area 2.</span>
+<a name="l00231"></a>00231 <span class="keywordflow">if</span> (GPRCS2Size > 0) MBBI++;
+<a name="l00232"></a>00232
+<a name="l00233"></a>00233 <span class="comment">// Determine starting offsets of spill areas.</span>
+<a name="l00234"></a>00234 <span class="keywordtype">unsigned</span> DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
+<a name="l00235"></a>00235 <span class="keywordtype">unsigned</span> GPRCS2Offset = DPRCSOffset + DPRCSSize;
+<a name="l00236"></a>00236 <span class="keywordtype">unsigned</span> GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
+<a name="l00237"></a>00237 <span class="keywordflow">if</span> (HasFP)
+<a name="l00238"></a>00238 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a715beb8a7c94f2868cb72ea4656f31c9">setFramePtrSpillOffset</a>(MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#aefac52e417d31959e35868879aba672b">getObjectOffset</a>(FramePtrSpillFI) +
+<a name="l00239"></a>00239 NumBytes);
+<a name="l00240"></a>00240 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ad5045ecd1e290139522971b28a299884">setGPRCalleeSavedArea1Offset</a>(GPRCS1Offset);
+<a name="l00241"></a>00241 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#acda46c15b10dfb33ceac5c4b39580221">setGPRCalleeSavedArea2Offset</a>(GPRCS2Offset);
+<a name="l00242"></a>00242 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a6752926550d5fd64a4e4e9fc06640e15">setDPRCalleeSavedAreaOffset</a>(DPRCSOffset);
+<a name="l00243"></a>00243
+<a name="l00244"></a>00244 <span class="comment">// Move past area 3.</span>
+<a name="l00245"></a>00245 <span class="keywordflow">if</span> (DPRCSSize > 0) {
+<a name="l00246"></a>00246 MBBI++;
+<a name="l00247"></a>00247 <span class="comment">// Since vpush register list cannot have gaps, there may be multiple vpush</span>
+<a name="l00248"></a>00248 <span class="comment">// instructions in the prologue.</span>
+<a name="l00249"></a>00249 <span class="keywordflow">while</span> (MBBI->getOpcode() == ARM::VSTMDDB_UPD)
+<a name="l00250"></a>00250 MBBI++;
+<a name="l00251"></a>00251 }
+<a name="l00252"></a>00252
+<a name="l00253"></a>00253 <span class="comment">// Move past the aligned DPRCS2 area.</span>
+<a name="l00254"></a>00254 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a70543217b38bd2e8dc926e315a78c930">getNumAlignedDPRCS2Regs</a>() > 0) {
+<a name="l00255"></a>00255 MBBI = <a class="code" href="ARMFrameLowering_8cpp.html#a0409e368b6e75e93e77f9c29a03edbe9">skipAlignedDPRCS2Spills</a>(MBBI, AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a70543217b38bd2e8dc926e315a78c930">getNumAlignedDPRCS2Regs</a>());
+<a name="l00256"></a>00256 <span class="comment">// The code inserted by emitAlignedDPRCS2Spills realigns the stack, and</span>
+<a name="l00257"></a>00257 <span class="comment">// leaves the stack pointer pointing to the DPRCS2 area.</span>
+<a name="l00258"></a>00258 <span class="comment">//</span>
+<a name="l00259"></a>00259 <span class="comment">// Adjust NumBytes to represent the stack slots below the DPRCS2 area.</span>
+<a name="l00260"></a>00260 NumBytes += MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#aefac52e417d31959e35868879aba672b">getObjectOffset</a>(D8SpillFI);
+<a name="l00261"></a>00261 } <span class="keywordflow">else</span>
+<a name="l00262"></a>00262 NumBytes = DPRCSOffset;
+<a name="l00263"></a>00263
+<a name="l00264"></a>00264 <span class="keywordflow">if</span> (NumBytes) {
+<a name="l00265"></a>00265 <span class="comment">// Adjust SP after all the callee-save spills.</span>
+<a name="l00266"></a>00266 <a class="code" href="ARMFrameLowering_8cpp.html#a9ab4b7db48660c4412dcd120e7e13648">emitSPUpdate</a>(isARM, MBB, MBBI, dl, TII, -NumBytes,
+<a name="l00267"></a>00267 <a class="code" href="classllvm_1_1MachineInstr.html#aafacf84de1cb994a92dc045f4aa1d518a78f1067d270179dff7915b90a03ce237">MachineInstr::FrameSetup</a>);
+<a name="l00268"></a>00268 <span class="keywordflow">if</span> (HasFP && isARM)
+<a name="l00269"></a>00269 <span class="comment">// Restore from fp only in ARM mode: e.g. sub sp, r7, #24</span>
+<a name="l00270"></a>00270 <span class="comment">// Note it's not safe to do this in Thumb2 mode because it would have</span>
+<a name="l00271"></a>00271 <span class="comment">// taken two instructions:</span>
+<a name="l00272"></a>00272 <span class="comment">// mov sp, r7</span>
+<a name="l00273"></a>00273 <span class="comment">// sub sp, #24</span>
+<a name="l00274"></a>00274 <span class="comment">// If an interrupt is taken between the two instructions, then sp is in</span>
+<a name="l00275"></a>00275 <span class="comment">// an inconsistent state (pointing to the middle of callee-saved area).</span>
+<a name="l00276"></a>00276 <span class="comment">// The interrupt handler can end up clobbering the registers.</span>
+<a name="l00277"></a>00277 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#aeebbc8bb36d06a4c62b09481cd3d94cb">setShouldRestoreSPFromFP</a>(<span class="keyword">true</span>);
+<a name="l00278"></a>00278 }
+<a name="l00279"></a>00279
+<a name="l00280"></a>00280 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a414966800902f6e5b323ff39ab90f376">isTargetELF</a>() && <a class="code" href="classllvm_1_1ARMFrameLowering.html#a9c8349fdf1c2f7ed13cd1a1bd1aeb19e">hasFP</a>(MF))
+<a name="l00281"></a>00281 MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a87a1fe769ec763a9c8f8427a017a45d7">setOffsetAdjustment</a>(MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a1ff5632f5b1783befc4324f6546a595c">getOffsetAdjustment</a>() -
+<a name="l00282"></a>00282 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a5b7bcbb91305fd94fd5200fdb37d444b">getFramePtrSpillOffset</a>());
+<a name="l00283"></a>00283
+<a name="l00284"></a>00284 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a858cd4502f6da3c957874ba54cc63008">setGPRCalleeSavedArea1Size</a>(GPRCS1Size);
+<a name="l00285"></a>00285 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a4d76a3f5d557ad4b5ba0fea030c265d6">setGPRCalleeSavedArea2Size</a>(GPRCS2Size);
+<a name="l00286"></a>00286 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a01e5dd8ce0571f928ae814e3db5542fc">setDPRCalleeSavedAreaSize</a>(DPRCSSize);
+<a name="l00287"></a>00287
+<a name="l00288"></a>00288 <span class="comment">// If we need dynamic stack realignment, do it here. Be paranoid and make</span>
+<a name="l00289"></a>00289 <span class="comment">// sure if we also have VLAs, we have a base pointer for frame access.</span>
+<a name="l00290"></a>00290 <span class="comment">// If aligned NEON registers were spilled, the stack has already been</span>
+<a name="l00291"></a>00291 <span class="comment">// realigned.</span>
+<a name="l00292"></a>00292 <span class="keywordflow">if</span> (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a70543217b38bd2e8dc926e315a78c930">getNumAlignedDPRCS2Regs</a>() && RegInfo->needsStackRealignment(MF)) {
+<a name="l00293"></a>00293 <span class="keywordtype">unsigned</span> MaxAlign = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a0af0a11b8eda54e79422c199cb687f5c">getMaxAlignment</a>();
+<a name="l00294"></a>00294 assert (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>());
+<a name="l00295"></a>00295 <span class="keywordflow">if</span> (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>()) {
+<a name="l00296"></a>00296 <span class="comment">// Emit bic sp, sp, MaxAlign</span>
+<a name="l00297"></a>00297 <a class="code" href="namespacellvm.html#a8b9edb9ece6ca4b10c73ae93a487c600">AddDefaultCC</a>(<a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl,
+<a name="l00298"></a>00298 TII.get(ARM::BICri), ARM::SP)
+<a name="l00299"></a>00299 .addReg(ARM::SP, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa9ddde91ef09476d28a088fe57f8e2921">RegState::Kill</a>)
+<a name="l00300"></a>00300 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(MaxAlign-1)));
+<a name="l00301"></a>00301 } <span class="keywordflow">else</span> {
+<a name="l00302"></a>00302 <span class="comment">// We cannot use sp as source/dest register here, thus we're emitting the</span>
+<a name="l00303"></a>00303 <span class="comment">// following sequence:</span>
+<a name="l00304"></a>00304 <span class="comment">// mov r4, sp</span>
+<a name="l00305"></a>00305 <span class="comment">// bic r4, r4, MaxAlign</span>
+<a name="l00306"></a>00306 <span class="comment">// mov sp, r4</span>
+<a name="l00307"></a>00307 <span class="comment">// FIXME: It will be better just to find spare register here.</span>
+<a name="l00308"></a>00308 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
+<a name="l00309"></a>00309 .addReg(ARM::SP, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa9ddde91ef09476d28a088fe57f8e2921">RegState::Kill</a>));
+<a name="l00310"></a>00310 <a class="code" href="namespacellvm.html#a8b9edb9ece6ca4b10c73ae93a487c600">AddDefaultCC</a>(<a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl,
+<a name="l00311"></a>00311 TII.get(ARM::t2BICri), ARM::R4)
+<a name="l00312"></a>00312 .addReg(ARM::R4, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa9ddde91ef09476d28a088fe57f8e2921">RegState::Kill</a>)
+<a name="l00313"></a>00313 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(MaxAlign-1)));
+<a name="l00314"></a>00314 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
+<a name="l00315"></a>00315 .addReg(ARM::R4, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa9ddde91ef09476d28a088fe57f8e2921">RegState::Kill</a>));
+<a name="l00316"></a>00316 }
+<a name="l00317"></a>00317
+<a name="l00318"></a>00318 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#aeebbc8bb36d06a4c62b09481cd3d94cb">setShouldRestoreSPFromFP</a>(<span class="keyword">true</span>);
+<a name="l00319"></a>00319 }
+<a name="l00320"></a>00320
+<a name="l00321"></a>00321 <span class="comment">// If we need a base pointer, set it up here. It's whatever the value</span>
+<a name="l00322"></a>00322 <span class="comment">// of the stack pointer is at this point. Any variable size objects</span>
+<a name="l00323"></a>00323 <span class="comment">// will be allocated after this, so we can still use the base pointer</span>
+<a name="l00324"></a>00324 <span class="comment">// to reference locals.</span>
+<a name="l00325"></a>00325 <span class="comment">// FIXME: Clarify FrameSetup flags here.</span>
+<a name="l00326"></a>00326 <span class="keywordflow">if</span> (RegInfo->hasBasePointer(MF)) {
+<a name="l00327"></a>00327 <span class="keywordflow">if</span> (isARM)
+<a name="l00328"></a>00328 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl,
+<a name="l00329"></a>00329 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
+<a name="l00330"></a>00330 .addReg(ARM::SP)
+<a name="l00331"></a>00331 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>((<span class="keywordtype">unsigned</span>)<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6a8b2ef77967dee1220cc6ee5aee595e11">ARMCC::AL</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(0);
+<a name="l00332"></a>00332 <span class="keywordflow">else</span>
+<a name="l00333"></a>00333 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl, TII.get(ARM::tMOVr),
+<a name="l00334"></a>00334 RegInfo->getBaseRegister())
+<a name="l00335"></a>00335 .addReg(ARM::SP));
+<a name="l00336"></a>00336 }
+<a name="l00337"></a>00337
+<a name="l00338"></a>00338 <span class="comment">// If the frame has variable sized objects then the epilogue must restore</span>
+<a name="l00339"></a>00339 <span class="comment">// the sp from fp. We can assume there's an FP here since hasFP already</span>
+<a name="l00340"></a>00340 <span class="comment">// checks for hasVarSizedObjects.</span>
+<a name="l00341"></a>00341 <span class="keywordflow">if</span> (MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a5cd76eb2aeed3ae46da1bb1b132f1831">hasVarSizedObjects</a>())
+<a name="l00342"></a>00342 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#aeebbc8bb36d06a4c62b09481cd3d94cb">setShouldRestoreSPFromFP</a>(<span class="keyword">true</span>);
+<a name="l00343"></a>00343 }
+<a name="l00344"></a>00344
+<a name="l00345"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#af2a875a7727b4d11c868a51b51524e73">00345</a> <span class="keywordtype">void</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#af2a875a7727b4d11c868a51b51524e73">ARMFrameLowering::emitEpilogue</a>(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF,
+<a name="l00346"></a>00346 <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB)<span class="keyword"> const </span>{
+<a name="l00347"></a>00347 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MBBI = MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#a4c711446100d52415f8e142855c223e1">getLastNonDebugInstr</a>();
+<a name="l00348"></a>00348 assert(MBBI->isReturn() && <span class="stringliteral">"Can only insert epilog into returning blocks"</span>);
+<a name="l00349"></a>00349 <span class="keywordtype">unsigned</span> RetOpcode = MBBI->getOpcode();
+<a name="l00350"></a>00350 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = MBBI->getDebugLoc();
+<a name="l00351"></a>00351 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l00352"></a>00352 <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l00353"></a>00353 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *RegInfo = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a70b47eca6a99c87b81f4c1b1455dc090">getRegisterInfo</a>();
+<a name="l00354"></a>00354 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a> &TII =
+<a name="l00355"></a>00355 *<span class="keyword">static_cast<</span><span class="keyword">const </span><a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a>*<span class="keyword">></span>(MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>());
+<a name="l00356"></a>00356 assert(!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>() &&
+<a name="l00357"></a>00357 <span class="stringliteral">"This emitEpilogue does not support Thumb1!"</span>);
+<a name="l00358"></a>00358 <span class="keywordtype">bool</span> isARM = !AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>();
+<a name="l00359"></a>00359
+<a name="l00360"></a>00360 <span class="keywordtype">unsigned</span> VARegSaveSize = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a81e3b6570ae669e775597d683027deea">getVarArgsRegSaveSize</a>();
+<a name="l00361"></a>00361 <span class="keywordtype">int</span> NumBytes = (int)MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a34874094b3ba8b56fd68801250f77183">getStackSize</a>();
+<a name="l00362"></a>00362 <span class="keywordtype">unsigned</span> FramePtr = RegInfo->getFrameRegister(MF);
+<a name="l00363"></a>00363
+<a name="l00364"></a>00364 <span class="comment">// All calls are tail calls in GHC calling conv, and functions have no</span>
+<a name="l00365"></a>00365 <span class="comment">// prologue/epilogue.</span>
+<a name="l00366"></a>00366 <span class="keywordflow">if</span> (MF.<a class="code" href="classllvm_1_1MachineFunction.html#ad784a6594990530bffb2018aeeed56f3">getFunction</a>()-><a class="code" href="classllvm_1_1Function.html#af4d5ada526cdf057f5f29047e058187d">getCallingConv</a>() == <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974a8e8dc64aad833bd23d07d3384522575e">CallingConv::GHC</a>)
+<a name="l00367"></a>00367 <span class="keywordflow">return</span>;
+<a name="l00368"></a>00368
+<a name="l00369"></a>00369 <span class="keywordflow">if</span> (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ac39b5595d3a23db77d972ba5b37c4348">hasStackFrame</a>()) {
+<a name="l00370"></a>00370 <span class="keywordflow">if</span> (NumBytes != 0)
+<a name="l00371"></a>00371 <a class="code" href="ARMFrameLowering_8cpp.html#a9ab4b7db48660c4412dcd120e7e13648">emitSPUpdate</a>(isARM, MBB, MBBI, dl, TII, NumBytes);
+<a name="l00372"></a>00372 } <span class="keywordflow">else</span> {
+<a name="l00373"></a>00373 <span class="comment">// Unwind MBBI to point to first LDR / VLDRD.</span>
+<a name="l00374"></a>00374 <span class="keyword">const</span> uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
+<a name="l00375"></a>00375 <span class="keywordflow">if</span> (MBBI != MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>()) {
+<a name="l00376"></a>00376 <span class="keywordflow">do</span>
+<a name="l00377"></a>00377 --MBBI;
+<a name="l00378"></a>00378 <span class="keywordflow">while</span> (MBBI != MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>() && <a class="code" href="ARMFrameLowering_8cpp.html#adcf1477a493b2d105f7f298b145bb188">isCSRestore</a>(MBBI, TII, CSRegs));
+<a name="l00379"></a>00379 <span class="keywordflow">if</span> (!<a class="code" href="ARMFrameLowering_8cpp.html#adcf1477a493b2d105f7f298b145bb188">isCSRestore</a>(MBBI, TII, CSRegs))
+<a name="l00380"></a>00380 ++MBBI;
+<a name="l00381"></a>00381 }
+<a name="l00382"></a>00382
+<a name="l00383"></a>00383 <span class="comment">// Move SP to start of FP callee save spill area.</span>
+<a name="l00384"></a>00384 NumBytes -= (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#adc208d17d2a07b48129f07131f199fc4">getGPRCalleeSavedArea1Size</a>() +
+<a name="l00385"></a>00385 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9f3ec749e16a8d9de6ff3826724ca33e">getGPRCalleeSavedArea2Size</a>() +
+<a name="l00386"></a>00386 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a36c6a3dd33fe945b3ab1cfa542f36074">getDPRCalleeSavedAreaSize</a>());
+<a name="l00387"></a>00387
+<a name="l00388"></a>00388 <span class="comment">// Reset SP based on frame pointer only if the stack frame extends beyond</span>
+<a name="l00389"></a>00389 <span class="comment">// frame pointer stack slot or target is ELF and the function has FP.</span>
+<a name="l00390"></a>00390 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#afffb0b39dfb932ed9180cef81453abc0">shouldRestoreSPFromFP</a>()) {
+<a name="l00391"></a>00391 NumBytes = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a5b7bcbb91305fd94fd5200fdb37d444b">getFramePtrSpillOffset</a>() - NumBytes;
+<a name="l00392"></a>00392 <span class="keywordflow">if</span> (NumBytes) {
+<a name="l00393"></a>00393 <span class="keywordflow">if</span> (isARM)
+<a name="l00394"></a>00394 <a class="code" href="namespacellvm.html#a402aa8ec2571af98e3b5871721c6f642">emitARMRegPlusImmediate</a>(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
+<a name="l00395"></a>00395 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6a8b2ef77967dee1220cc6ee5aee595e11">ARMCC::AL</a>, 0, TII);
+<a name="l00396"></a>00396 <span class="keywordflow">else</span> {
+<a name="l00397"></a>00397 <span class="comment">// It's not possible to restore SP from FP in a single instruction.</span>
+<a name="l00398"></a>00398 <span class="comment">// For iOS, this looks like:</span>
+<a name="l00399"></a>00399 <span class="comment">// mov sp, r7</span>
+<a name="l00400"></a>00400 <span class="comment">// sub sp, #24</span>
+<a name="l00401"></a>00401 <span class="comment">// This is bad, if an interrupt is taken after the mov, sp is in an</span>
+<a name="l00402"></a>00402 <span class="comment">// inconsistent state.</span>
+<a name="l00403"></a>00403 <span class="comment">// Use the first callee-saved register as a scratch register.</span>
+<a name="l00404"></a>00404 assert(MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#abe3c98b9803fa6a21eca279173c27b12">isPhysRegUsed</a>(ARM::R4) &&
+<a name="l00405"></a>00405 <span class="stringliteral">"No scratch register to restore SP from FP!"</span>);
+<a name="l00406"></a>00406 <a class="code" href="namespacellvm.html#ae59f84da43ddc1b247716625b3b31dfb">emitT2RegPlusImmediate</a>(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
+<a name="l00407"></a>00407 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6a8b2ef77967dee1220cc6ee5aee595e11">ARMCC::AL</a>, 0, TII);
+<a name="l00408"></a>00408 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl, TII.get(ARM::tMOVr),
+<a name="l00409"></a>00409 ARM::SP)
+<a name="l00410"></a>00410 .addReg(ARM::R4));
+<a name="l00411"></a>00411 }
+<a name="l00412"></a>00412 } <span class="keywordflow">else</span> {
+<a name="l00413"></a>00413 <span class="comment">// Thumb2 or ARM.</span>
+<a name="l00414"></a>00414 <span class="keywordflow">if</span> (isARM)
+<a name="l00415"></a>00415 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
+<a name="l00416"></a>00416 .addReg(FramePtr).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>((<span class="keywordtype">unsigned</span>)<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6a8b2ef77967dee1220cc6ee5aee595e11">ARMCC::AL</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(0).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(0);
+<a name="l00417"></a>00417 <span class="keywordflow">else</span>
+<a name="l00418"></a>00418 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl, TII.get(ARM::tMOVr),
+<a name="l00419"></a>00419 ARM::SP)
+<a name="l00420"></a>00420 .addReg(FramePtr));
+<a name="l00421"></a>00421 }
+<a name="l00422"></a>00422 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (NumBytes)
+<a name="l00423"></a>00423 <a class="code" href="ARMFrameLowering_8cpp.html#a9ab4b7db48660c4412dcd120e7e13648">emitSPUpdate</a>(isARM, MBB, MBBI, dl, TII, NumBytes);
+<a name="l00424"></a>00424
+<a name="l00425"></a>00425 <span class="comment">// Increment past our save areas.</span>
+<a name="l00426"></a>00426 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a36c6a3dd33fe945b3ab1cfa542f36074">getDPRCalleeSavedAreaSize</a>()) {
+<a name="l00427"></a>00427 MBBI++;
+<a name="l00428"></a>00428 <span class="comment">// Since vpop register list cannot have gaps, there may be multiple vpop</span>
+<a name="l00429"></a>00429 <span class="comment">// instructions in the epilogue.</span>
+<a name="l00430"></a>00430 <span class="keywordflow">while</span> (MBBI->getOpcode() == ARM::VLDMDIA_UPD)
+<a name="l00431"></a>00431 MBBI++;
+<a name="l00432"></a>00432 }
+<a name="l00433"></a>00433 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9f3ec749e16a8d9de6ff3826724ca33e">getGPRCalleeSavedArea2Size</a>()) MBBI++;
+<a name="l00434"></a>00434 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#adc208d17d2a07b48129f07131f199fc4">getGPRCalleeSavedArea1Size</a>()) MBBI++;
+<a name="l00435"></a>00435 }
+<a name="l00436"></a>00436
+<a name="l00437"></a>00437 <span class="keywordflow">if</span> (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri) {
+<a name="l00438"></a>00438 <span class="comment">// Tail call return: adjust the stack pointer and jump to callee.</span>
+<a name="l00439"></a>00439 MBBI = MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#a4c711446100d52415f8e142855c223e1">getLastNonDebugInstr</a>();
+<a name="l00440"></a>00440 <a class="code" href="classllvm_1_1MachineOperand.html">MachineOperand</a> &JumpTarget = MBBI->getOperand(0);
+<a name="l00441"></a>00441
+<a name="l00442"></a>00442 <span class="comment">// Jump to label or value in register.</span>
+<a name="l00443"></a>00443 <span class="keywordflow">if</span> (RetOpcode == ARM::TCRETURNdi) {
+<a name="l00444"></a>00444 <span class="keywordtype">unsigned</span> TCOpcode = <a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a3ceb25cf21483ee4aae7948d98401170">isThumb</a>() ?
+<a name="l00445"></a>00445 (<a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a80f7cdbc91b73599f8319c4a88c7ca18">isTargetIOS</a>() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) :
+<a name="l00446"></a>00446 ARM::TAILJMPd;
+<a name="l00447"></a>00447 <a class="code" href="classllvm_1_1MachineInstrBuilder.html">MachineInstrBuilder</a> MIB = <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl, TII.get(TCOpcode));
+<a name="l00448"></a>00448 <span class="keywordflow">if</span> (JumpTarget.<a class="code" href="classllvm_1_1MachineOperand.html#a58048141ed81d581f3fb9a797f3186ee" title="isGlobal - Tests if this is a MO_GlobalAddress operand.">isGlobal</a>())
+<a name="l00449"></a>00449 MIB.<a class="code" href="classllvm_1_1MachineInstrBuilder.html#aec72fc7a6cc79a1ef53e5d5dbccb846c">addGlobalAddress</a>(JumpTarget.<a class="code" href="classllvm_1_1MachineOperand.html#a0c3a2a5a49795f8750ebd02dc0e6e11e">getGlobal</a>(), JumpTarget.<a class="code" href="classllvm_1_1MachineOperand.html#ae73de4f077ea9862af9611652396202b">getOffset</a>(),
+<a name="l00450"></a>00450 JumpTarget.<a class="code" href="classllvm_1_1MachineOperand.html#a66e5034087365ccc871f5b6cae30d00c">getTargetFlags</a>());
+<a name="l00451"></a>00451 <span class="keywordflow">else</span> {
+<a name="l00452"></a>00452 assert(JumpTarget.<a class="code" href="classllvm_1_1MachineOperand.html#a312ddf2fd2162ef0c552d913369cd57f" title="isSymbol - Tests if this is a MO_ExternalSymbol operand.">isSymbol</a>());
+<a name="l00453"></a>00453 MIB.<a class="code" href="classllvm_1_1MachineInstrBuilder.html#ace690c220f3b141bdf98c86635783d8f">addExternalSymbol</a>(JumpTarget.<a class="code" href="classllvm_1_1MachineOperand.html#ad9456ef14a72da4e4def5d8747c41a09">getSymbolName</a>(),
+<a name="l00454"></a>00454 JumpTarget.<a class="code" href="classllvm_1_1MachineOperand.html#a66e5034087365ccc871f5b6cae30d00c">getTargetFlags</a>());
+<a name="l00455"></a>00455 }
+<a name="l00456"></a>00456
+<a name="l00457"></a>00457 <span class="comment">// Add the default predicate in Thumb mode.</span>
+<a name="l00458"></a>00458 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a3ceb25cf21483ee4aae7948d98401170">isThumb</a>()) MIB.<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6a8b2ef77967dee1220cc6ee5aee595e11">ARMCC::AL</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(0);
+<a name="l00459"></a>00459 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (RetOpcode == ARM::TCRETURNri) {
+<a name="l00460"></a>00460 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MBBI, dl,
+<a name="l00461"></a>00461 TII.get(<a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a3ceb25cf21483ee4aae7948d98401170">isThumb</a>() ? ARM::tTAILJMPr : ARM::TAILJMPr)).
+<a name="l00462"></a>00462 addReg(JumpTarget.<a class="code" href="classllvm_1_1MachineOperand.html#ab75f703d251cc0ce0206fe00a999db86" title="getReg - Returns the register number.">getReg</a>(), <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa9ddde91ef09476d28a088fe57f8e2921">RegState::Kill</a>);
+<a name="l00463"></a>00463 }
+<a name="l00464"></a>00464
+<a name="l00465"></a>00465 <a class="code" href="classllvm_1_1MachineInstr.html">MachineInstr</a> *NewMI = <a class="code" href="namespacellvm.html#a7923e3e207de8bc1d0d6a5091316ddde">prior</a>(MBBI);
+<a name="l00466"></a>00466 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 1, e = MBBI->getNumOperands(); i != e; ++i)
+<a name="l00467"></a>00467 NewMI-><a class="code" href="classllvm_1_1MachineInstr.html#aabf3514a1ace5d142cc33b48f3eb3f63">addOperand</a>(MBBI->getOperand(i));
+<a name="l00468"></a>00468
+<a name="l00469"></a>00469 <span class="comment">// Delete the pseudo instruction TCRETURN.</span>
+<a name="l00470"></a>00470 MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#a537a9265c55392ab47d44954f27db538">erase</a>(MBBI);
+<a name="l00471"></a>00471 MBBI = NewMI;
+<a name="l00472"></a>00472 }
+<a name="l00473"></a>00473
+<a name="l00474"></a>00474 <span class="keywordflow">if</span> (VARegSaveSize)
+<a name="l00475"></a>00475 <a class="code" href="ARMFrameLowering_8cpp.html#a9ab4b7db48660c4412dcd120e7e13648">emitSPUpdate</a>(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
+<a name="l00476"></a>00476 }
+<a name="l00477"></a>00477 <span class="comment"></span>
+<a name="l00478"></a>00478 <span class="comment">/// getFrameIndexReference - Provide a base+offset reference to an FI slot for</span>
+<a name="l00479"></a>00479 <span class="comment">/// debug info. It's the same as what we use for resolving the code-gen</span>
+<a name="l00480"></a>00480 <span class="comment">/// references for now. FIXME: This can go wrong when references are</span>
+<a name="l00481"></a>00481 <span class="comment">/// SP-relative and simple call frames aren't used.</span>
+<a name="l00482"></a>00482 <span class="comment"></span><span class="keywordtype">int</span>
+<a name="l00483"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#a6478f03c6bd2e44b785356dd2af29860">00483</a> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a6478f03c6bd2e44b785356dd2af29860">ARMFrameLowering::getFrameIndexReference</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF, <span class="keywordtype">int</span> FI,
+<a name="l00484"></a>00484 <span class="keywordtype">unsigned</span> &FrameReg)<span class="keyword"> const </span>{
+<a name="l00485"></a>00485 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a9f4bd45d0a817adf290a5055a6e3e956">ResolveFrameIndexReference</a>(MF, FI, FrameReg, 0);
+<a name="l00486"></a>00486 }
+<a name="l00487"></a>00487
+<a name="l00488"></a>00488 <span class="keywordtype">int</span>
+<a name="l00489"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#a9f4bd45d0a817adf290a5055a6e3e956">00489</a> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a9f4bd45d0a817adf290a5055a6e3e956">ARMFrameLowering::ResolveFrameIndexReference</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF,
+<a name="l00490"></a>00490 <span class="keywordtype">int</span> FI, <span class="keywordtype">unsigned</span> &FrameReg,
+<a name="l00491"></a>00491 <span class="keywordtype">int</span> SPAdj)<span class="keyword"> const </span>{
+<a name="l00492"></a>00492 <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l00493"></a>00493 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html">ARMBaseRegisterInfo</a> *RegInfo =
+<a name="l00494"></a>00494 <span class="keyword">static_cast<</span><span class="keyword">const </span><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html">ARMBaseRegisterInfo</a>*<span class="keyword">></span>(MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a70b47eca6a99c87b81f4c1b1455dc090">getRegisterInfo</a>());
+<a name="l00495"></a>00495 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l00496"></a>00496 <span class="keywordtype">int</span> Offset = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#aefac52e417d31959e35868879aba672b">getObjectOffset</a>(FI) + MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a34874094b3ba8b56fd68801250f77183">getStackSize</a>();
+<a name="l00497"></a>00497 <span class="keywordtype">int</span> FPOffset = Offset - AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a5b7bcbb91305fd94fd5200fdb37d444b">getFramePtrSpillOffset</a>();
+<a name="l00498"></a>00498 <span class="keywordtype">bool</span> isFixed = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#abd98297b61062a9bf2bc306aa87a4039">isFixedObjectIndex</a>(FI);
+<a name="l00499"></a>00499
+<a name="l00500"></a>00500 FrameReg = ARM::SP;
+<a name="l00501"></a>00501 Offset += SPAdj;
+<a name="l00502"></a>00502 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a646ec7d2b190b6fed3423823a5811b4d">isGPRCalleeSavedArea1Frame</a>(FI))
+<a name="l00503"></a>00503 <span class="keywordflow">return</span> Offset - AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a861583bfb23c2268e0878af24b36a60c">getGPRCalleeSavedArea1Offset</a>();
+<a name="l00504"></a>00504 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a1aa6518d2671c01f35fa894d13ceacca">isGPRCalleeSavedArea2Frame</a>(FI))
+<a name="l00505"></a>00505 <span class="keywordflow">return</span> Offset - AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#aa85f1f3b5a239912bf5c48f3f7122787">getGPRCalleeSavedArea2Offset</a>();
+<a name="l00506"></a>00506 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a6d8466e6ac018ab1834dfb1a99477e19">isDPRCalleeSavedAreaFrame</a>(FI))
+<a name="l00507"></a>00507 <span class="keywordflow">return</span> Offset - AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#adb11c4e7fb12a6b300c7030c2aa6f947">getDPRCalleeSavedAreaOffset</a>();
+<a name="l00508"></a>00508
+<a name="l00509"></a>00509 <span class="comment">// SP can move around if there are allocas. We may also lose track of SP</span>
+<a name="l00510"></a>00510 <span class="comment">// when emergency spilling inside a non-reserved call frame setup.</span>
+<a name="l00511"></a>00511 <span class="keywordtype">bool</span> hasMovingSP = !<a class="code" href="classllvm_1_1ARMFrameLowering.html#a8f1ddf69e36ed0354ae69fedd3fed9a5">hasReservedCallFrame</a>(MF);
+<a name="l00512"></a>00512
+<a name="l00513"></a>00513 <span class="comment">// When dynamically realigning the stack, use the frame pointer for</span>
+<a name="l00514"></a>00514 <span class="comment">// parameters, and the stack/base pointer for locals.</span>
+<a name="l00515"></a>00515 <span class="keywordflow">if</span> (RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a01ecb9dfd78defd2dee58c89c443463a">needsStackRealignment</a>(MF)) {
+<a name="l00516"></a>00516 assert (<a class="code" href="classllvm_1_1ARMFrameLowering.html#a9c8349fdf1c2f7ed13cd1a1bd1aeb19e">hasFP</a>(MF) && <span class="stringliteral">"dynamic stack realignment without a FP!"</span>);
+<a name="l00517"></a>00517 <span class="keywordflow">if</span> (isFixed) {
+<a name="l00518"></a>00518 FrameReg = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a47e108ecd9a21cb626ea629490f45e25">getFrameRegister</a>(MF);
+<a name="l00519"></a>00519 Offset = FPOffset;
+<a name="l00520"></a>00520 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hasMovingSP) {
+<a name="l00521"></a>00521 assert(RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a0e3e26dbde5eb40a63a5ed4220cf6211">hasBasePointer</a>(MF) &&
+<a name="l00522"></a>00522 <span class="stringliteral">"VLAs and dynamic stack alignment, but missing base pointer!"</span>);
+<a name="l00523"></a>00523 FrameReg = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a4682c4f655dfb10da71ef7d649465d58">getBaseRegister</a>();
+<a name="l00524"></a>00524 }
+<a name="l00525"></a>00525 <span class="keywordflow">return</span> Offset;
+<a name="l00526"></a>00526 }
+<a name="l00527"></a>00527
+<a name="l00528"></a>00528 <span class="comment">// If there is a frame pointer, use it when we can.</span>
+<a name="l00529"></a>00529 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ARMFrameLowering.html#a9c8349fdf1c2f7ed13cd1a1bd1aeb19e">hasFP</a>(MF) && AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ac39b5595d3a23db77d972ba5b37c4348">hasStackFrame</a>()) {
+<a name="l00530"></a>00530 <span class="comment">// Use frame pointer to reference fixed objects. Use it for locals if</span>
+<a name="l00531"></a>00531 <span class="comment">// there are VLAs (and thus the SP isn't reliable as a base).</span>
+<a name="l00532"></a>00532 <span class="keywordflow">if</span> (isFixed || (hasMovingSP && !RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a0e3e26dbde5eb40a63a5ed4220cf6211">hasBasePointer</a>(MF))) {
+<a name="l00533"></a>00533 FrameReg = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a47e108ecd9a21cb626ea629490f45e25">getFrameRegister</a>(MF);
+<a name="l00534"></a>00534 <span class="keywordflow">return</span> FPOffset;
+<a name="l00535"></a>00535 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (hasMovingSP) {
+<a name="l00536"></a>00536 assert(RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a0e3e26dbde5eb40a63a5ed4220cf6211">hasBasePointer</a>(MF) && <span class="stringliteral">"missing base pointer!"</span>);
+<a name="l00537"></a>00537 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a07c23410c7430f86085eadea31db3ee2">isThumb2Function</a>()) {
+<a name="l00538"></a>00538 <span class="comment">// Try to use the frame pointer if we can, else use the base pointer</span>
+<a name="l00539"></a>00539 <span class="comment">// since it's available. This is handy for the emergency spill slot, in</span>
+<a name="l00540"></a>00540 <span class="comment">// particular.</span>
+<a name="l00541"></a>00541 <span class="keywordflow">if</span> (FPOffset >= -255 && FPOffset < 0) {
+<a name="l00542"></a>00542 FrameReg = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a47e108ecd9a21cb626ea629490f45e25">getFrameRegister</a>(MF);
+<a name="l00543"></a>00543 <span class="keywordflow">return</span> FPOffset;
+<a name="l00544"></a>00544 }
+<a name="l00545"></a>00545 }
+<a name="l00546"></a>00546 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a07c23410c7430f86085eadea31db3ee2">isThumb2Function</a>()) {
+<a name="l00547"></a>00547 <span class="comment">// Use add <rd>, sp, #<imm8></span>
+<a name="l00548"></a>00548 <span class="comment">// ldr <rd>, [sp, #<imm8>]</span>
+<a name="l00549"></a>00549 <span class="comment">// if at all possible to save space.</span>
+<a name="l00550"></a>00550 <span class="keywordflow">if</span> (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
+<a name="l00551"></a>00551 <span class="keywordflow">return</span> Offset;
+<a name="l00552"></a>00552 <span class="comment">// In Thumb2 mode, the negative offset is very limited. Try to avoid</span>
+<a name="l00553"></a>00553 <span class="comment">// out of range references. ldr <rt>,[<rn>, #-<imm8>]</span>
+<a name="l00554"></a>00554 <span class="keywordflow">if</span> (FPOffset >= -255 && FPOffset < 0) {
+<a name="l00555"></a>00555 FrameReg = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a47e108ecd9a21cb626ea629490f45e25">getFrameRegister</a>(MF);
+<a name="l00556"></a>00556 <span class="keywordflow">return</span> FPOffset;
+<a name="l00557"></a>00557 }
+<a name="l00558"></a>00558 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
+<a name="l00559"></a>00559 <span class="comment">// Otherwise, use SP or FP, whichever is closer to the stack slot.</span>
+<a name="l00560"></a>00560 FrameReg = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a47e108ecd9a21cb626ea629490f45e25">getFrameRegister</a>(MF);
+<a name="l00561"></a>00561 <span class="keywordflow">return</span> FPOffset;
+<a name="l00562"></a>00562 }
+<a name="l00563"></a>00563 }
+<a name="l00564"></a>00564 <span class="comment">// Use the base pointer if we have one.</span>
+<a name="l00565"></a>00565 <span class="keywordflow">if</span> (RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a0e3e26dbde5eb40a63a5ed4220cf6211">hasBasePointer</a>(MF))
+<a name="l00566"></a>00566 FrameReg = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a4682c4f655dfb10da71ef7d649465d58">getBaseRegister</a>();
+<a name="l00567"></a>00567 <span class="keywordflow">return</span> Offset;
+<a name="l00568"></a>00568 }
+<a name="l00569"></a>00569
+<a name="l00570"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#ae09d53e8ec1de0218c59cf2da6060653">00570</a> <span class="keywordtype">int</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#ae09d53e8ec1de0218c59cf2da6060653">ARMFrameLowering::getFrameIndexOffset</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF,
+<a name="l00571"></a>00571 <span class="keywordtype">int</span> FI)<span class="keyword"> const </span>{
+<a name="l00572"></a>00572 <span class="keywordtype">unsigned</span> FrameReg;
+<a name="l00573"></a>00573 <span class="keywordflow">return</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a6478f03c6bd2e44b785356dd2af29860">getFrameIndexReference</a>(MF, FI, FrameReg);
+<a name="l00574"></a>00574 }
+<a name="l00575"></a>00575
+<a name="l00576"></a>00576 <span class="keywordtype">void</span> ARMFrameLowering::emitPushInst(<a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB,
+<a name="l00577"></a>00577 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>,
+<a name="l00578"></a>00578 <span class="keyword">const</span> std::vector<CalleeSavedInfo> &CSI,
+<a name="l00579"></a>00579 <span class="keywordtype">unsigned</span> StmOpc, <span class="keywordtype">unsigned</span> StrOpc,
+<a name="l00580"></a>00580 <span class="keywordtype">bool</span> NoGap,
+<a name="l00581"></a>00581 <span class="keywordtype">bool</span>(*<a class="code" href="namespacellvm_1_1LibFunc.html#abf8f6830387f338fed0bce2e65108c6f">Func</a>)(<span class="keywordtype">unsigned</span>, <span class="keywordtype">bool</span>),
+<a name="l00582"></a>00582 <span class="keywordtype">unsigned</span> NumAlignedDPRCS2Regs,
+<a name="l00583"></a>00583 <span class="keywordtype">unsigned</span> MIFlags)<span class="keyword"> const </span>{
+<a name="l00584"></a>00584 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = *MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l00585"></a>00585 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> &TII = *MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>();
+<a name="l00586"></a>00586
+<a name="l00587"></a>00587 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> DL;
+<a name="l00588"></a>00588 <span class="keywordflow">if</span> (MI != MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#acbc921830578e2741be6549db716c0ce">end</a>()) DL = MI->getDebugLoc();
+<a name="l00589"></a>00589
+<a name="l00590"></a>00590 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<std::pair<unsigned,bool></a>, 4> Regs;
+<a name="l00591"></a>00591 <span class="keywordtype">unsigned</span> i = CSI.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>();
+<a name="l00592"></a>00592 <span class="keywordflow">while</span> (i != 0) {
+<a name="l00593"></a>00593 <span class="keywordtype">unsigned</span> LastReg = 0;
+<a name="l00594"></a>00594 <span class="keywordflow">for</span> (; i != 0; --i) {
+<a name="l00595"></a>00595 <span class="keywordtype">unsigned</span> <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a> = CSI[i-1].getReg();
+<a name="l00596"></a>00596 <span class="keywordflow">if</span> (!(<a class="code" href="namespacellvm_1_1LibFunc.html#abf8f6830387f338fed0bce2e65108c6f">Func</a>)(Reg, <a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a80f7cdbc91b73599f8319c4a88c7ca18">isTargetIOS</a>())) <span class="keywordflow">continue</span>;
+<a name="l00597"></a>00597
+<a name="l00598"></a>00598 <span class="comment">// D-registers in the aligned area DPRCS2 are NOT spilled here.</span>
+<a name="l00599"></a>00599 <span class="keywordflow">if</span> (Reg >= <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a> && Reg < <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a> + NumAlignedDPRCS2Regs)
+<a name="l00600"></a>00600 <span class="keywordflow">continue</span>;
+<a name="l00601"></a>00601
+<a name="l00602"></a>00602 <span class="comment">// Add the callee-saved register as live-in unless it's LR and</span>
+<a name="l00603"></a>00603 <span class="comment">// @llvm.returnaddress is called. If LR is returned for</span>
+<a name="l00604"></a>00604 <span class="comment">// @llvm.returnaddress then it's already added to the function and</span>
+<a name="l00605"></a>00605 <span class="comment">// entry block live-in sets.</span>
+<a name="l00606"></a>00606 <span class="keywordtype">bool</span> isKill = <span class="keyword">true</span>;
+<a name="l00607"></a>00607 <span class="keywordflow">if</span> (Reg == ARM::LR) {
+<a name="l00608"></a>00608 <span class="keywordflow">if</span> (MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a6ea0bba3d9f50696c9610f6e7ce10f10">isReturnAddressTaken</a>() &&
+<a name="l00609"></a>00609 MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a5e4b09e8d0f31b43fd5a912ed288bccb">isLiveIn</a>(Reg))
+<a name="l00610"></a>00610 isKill = <span class="keyword">false</span>;
+<a name="l00611"></a>00611 }
+<a name="l00612"></a>00612
+<a name="l00613"></a>00613 <span class="keywordflow">if</span> (isKill)
+<a name="l00614"></a>00614 MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ae26efdb76d5c56388c65dc5b02a2ae6f">addLiveIn</a>(Reg);
+<a name="l00615"></a>00615
+<a name="l00616"></a>00616 <span class="comment">// If NoGap is true, push consecutive registers and then leave the rest</span>
+<a name="l00617"></a>00617 <span class="comment">// for other instructions. e.g.</span>
+<a name="l00618"></a>00618 <span class="comment">// vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}</span>
+<a name="l00619"></a>00619 <span class="keywordflow">if</span> (NoGap && LastReg && LastReg != Reg-1)
+<a name="l00620"></a>00620 <span class="keywordflow">break</span>;
+<a name="l00621"></a>00621 LastReg = <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>;
+<a name="l00622"></a>00622 Regs.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(std::make_pair(Reg, isKill));
+<a name="l00623"></a>00623 }
+<a name="l00624"></a>00624
+<a name="l00625"></a>00625 <span class="keywordflow">if</span> (Regs.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l00626"></a>00626 <span class="keywordflow">continue</span>;
+<a name="l00627"></a>00627 <span class="keywordflow">if</span> (Regs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>() > 1 || StrOpc== 0) {
+<a name="l00628"></a>00628 <a class="code" href="classllvm_1_1MachineInstrBuilder.html">MachineInstrBuilder</a> MIB =
+<a name="l00629"></a>00629 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(StmOpc), ARM::SP)
+<a name="l00630"></a>00630 .addReg(ARM::SP).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#aabc17a35420fd0015b8cc5e6e51112fc">setMIFlags</a>(MIFlags));
+<a name="l00631"></a>00631 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = Regs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i < e; ++i)
+<a name="l00632"></a>00632 MIB.<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(Regs[i].first, <a class="code" href="namespacellvm.html#aac57d4100e9a9d02522fbd724568397d">getKillRegState</a>(Regs[i].second));
+<a name="l00633"></a>00633 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Regs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>() == 1) {
+<a name="l00634"></a>00634 <a class="code" href="classllvm_1_1MachineInstrBuilder.html">MachineInstrBuilder</a> MIB = <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(StrOpc),
+<a name="l00635"></a>00635 ARM::SP)
+<a name="l00636"></a>00636 .addReg(Regs[0].first, <a class="code" href="namespacellvm.html#aac57d4100e9a9d02522fbd724568397d">getKillRegState</a>(Regs[0].second))
+<a name="l00637"></a>00637 .addReg(ARM::SP).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#aabc17a35420fd0015b8cc5e6e51112fc">setMIFlags</a>(MIFlags)
+<a name="l00638"></a>00638 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(-4);
+<a name="l00639"></a>00639 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(MIB);
+<a name="l00640"></a>00640 }
+<a name="l00641"></a>00641 Regs.<a class="code" href="classllvm_1_1SmallVectorImpl.html#aac0ea55010b7b1a301e65a0baea057aa">clear</a>();
+<a name="l00642"></a>00642 }
+<a name="l00643"></a>00643 }
+<a name="l00644"></a>00644
+<a name="l00645"></a>00645 <span class="keywordtype">void</span> ARMFrameLowering::emitPopInst(<a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB,
+<a name="l00646"></a>00646 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MI,
+<a name="l00647"></a>00647 <span class="keyword">const</span> std::vector<CalleeSavedInfo> &CSI,
+<a name="l00648"></a>00648 <span class="keywordtype">unsigned</span> LdmOpc, <span class="keywordtype">unsigned</span> LdrOpc,
+<a name="l00649"></a>00649 <span class="keywordtype">bool</span> isVarArg, <span class="keywordtype">bool</span> NoGap,
+<a name="l00650"></a>00650 <span class="keywordtype">bool</span>(*<a class="code" href="namespacellvm_1_1LibFunc.html#abf8f6830387f338fed0bce2e65108c6f">Func</a>)(<span class="keywordtype">unsigned</span>, <span class="keywordtype">bool</span>),
+<a name="l00651"></a>00651 <span class="keywordtype">unsigned</span> NumAlignedDPRCS2Regs)<span class="keyword"> const </span>{
+<a name="l00652"></a>00652 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = *MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l00653"></a>00653 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> &TII = *MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>();
+<a name="l00654"></a>00654 <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l00655"></a>00655 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> DL = MI->getDebugLoc();
+<a name="l00656"></a>00656 <span class="keywordtype">unsigned</span> RetOpcode = MI->getOpcode();
+<a name="l00657"></a>00657 <span class="keywordtype">bool</span> isTailCall = (RetOpcode == ARM::TCRETURNdi ||
+<a name="l00658"></a>00658 RetOpcode == ARM::TCRETURNri);
+<a name="l00659"></a>00659
+<a name="l00660"></a>00660 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<unsigned, 4></a> Regs;
+<a name="l00661"></a>00661 <span class="keywordtype">unsigned</span> i = CSI.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>();
+<a name="l00662"></a>00662 <span class="keywordflow">while</span> (i != 0) {
+<a name="l00663"></a>00663 <span class="keywordtype">unsigned</span> LastReg = 0;
+<a name="l00664"></a>00664 <span class="keywordtype">bool</span> DeleteRet = <span class="keyword">false</span>;
+<a name="l00665"></a>00665 <span class="keywordflow">for</span> (; i != 0; --i) {
+<a name="l00666"></a>00666 <span class="keywordtype">unsigned</span> Reg = CSI[i-1].getReg();
+<a name="l00667"></a>00667 <span class="keywordflow">if</span> (!(<a class="code" href="namespacellvm_1_1LibFunc.html#abf8f6830387f338fed0bce2e65108c6f">Func</a>)(Reg, <a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a80f7cdbc91b73599f8319c4a88c7ca18">isTargetIOS</a>())) <span class="keywordflow">continue</span>;
+<a name="l00668"></a>00668
+<a name="l00669"></a>00669 <span class="comment">// The aligned reloads from area DPRCS2 are not inserted here.</span>
+<a name="l00670"></a>00670 <span class="keywordflow">if</span> (Reg >= <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a> && Reg < <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a> + NumAlignedDPRCS2Regs)
+<a name="l00671"></a>00671 <span class="keywordflow">continue</span>;
+<a name="l00672"></a>00672
+<a name="l00673"></a>00673 <span class="keywordflow">if</span> (Reg == ARM::LR && !isTailCall && !isVarArg && <a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a41db1260fa1ac571916b808a001b6149">hasV5TOps</a>()) {
+<a name="l00674"></a>00674 Reg = ARM::PC;
+<a name="l00675"></a>00675 LdmOpc = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
+<a name="l00676"></a>00676 <span class="comment">// Fold the return instruction into the LDM.</span>
+<a name="l00677"></a>00677 DeleteRet = <span class="keyword">true</span>;
+<a name="l00678"></a>00678 }
+<a name="l00679"></a>00679
+<a name="l00680"></a>00680 <span class="comment">// If NoGap is true, pop consecutive registers and then leave the rest</span>
+<a name="l00681"></a>00681 <span class="comment">// for other instructions. e.g.</span>
+<a name="l00682"></a>00682 <span class="comment">// vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}</span>
+<a name="l00683"></a>00683 <span class="keywordflow">if</span> (NoGap && LastReg && LastReg != Reg-1)
+<a name="l00684"></a>00684 <span class="keywordflow">break</span>;
+<a name="l00685"></a>00685
+<a name="l00686"></a>00686 LastReg = <a class="code" href="X86DisassemblerDecoder_8h.html#a546839a5c4bcf9f9450967155f48de41">Reg</a>;
+<a name="l00687"></a>00687 Regs.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg);
+<a name="l00688"></a>00688 }
+<a name="l00689"></a>00689
+<a name="l00690"></a>00690 <span class="keywordflow">if</span> (Regs.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>())
+<a name="l00691"></a>00691 <span class="keywordflow">continue</span>;
+<a name="l00692"></a>00692 <span class="keywordflow">if</span> (Regs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>() > 1 || LdrOpc == 0) {
+<a name="l00693"></a>00693 <a class="code" href="classllvm_1_1MachineInstrBuilder.html">MachineInstrBuilder</a> MIB =
+<a name="l00694"></a>00694 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(LdmOpc), ARM::SP)
+<a name="l00695"></a>00695 .addReg(ARM::SP));
+<a name="l00696"></a>00696 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = Regs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i < e; ++i)
+<a name="l00697"></a>00697 MIB.<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(Regs[i], <a class="code" href="namespacellvm.html#aa5e4d7acf58e87826a15b94d37144f2b">getDefRegState</a>(<span class="keyword">true</span>));
+<a name="l00698"></a>00698 <span class="keywordflow">if</span> (DeleteRet) {
+<a name="l00699"></a>00699 MIB->copyImplicitOps(&*MI);
+<a name="l00700"></a>00700 MI->eraseFromParent();
+<a name="l00701"></a>00701 }
+<a name="l00702"></a>00702 MI = MIB;
+<a name="l00703"></a>00703 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Regs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>() == 1) {
+<a name="l00704"></a>00704 <span class="comment">// If we adjusted the reg to PC from LR above, switch it back here. We</span>
+<a name="l00705"></a>00705 <span class="comment">// only do that for LDM.</span>
+<a name="l00706"></a>00706 <span class="keywordflow">if</span> (Regs[0] == ARM::PC)
+<a name="l00707"></a>00707 Regs[0] = ARM::LR;
+<a name="l00708"></a>00708 <a class="code" href="classllvm_1_1MachineInstrBuilder.html">MachineInstrBuilder</a> MIB =
+<a name="l00709"></a>00709 <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(LdrOpc), Regs[0])
+<a name="l00710"></a>00710 .addReg(ARM::SP, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa72c17e2ff2d5af62a30e56ac152aa8d5">RegState::Define</a>)
+<a name="l00711"></a>00711 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ARM::SP);
+<a name="l00712"></a>00712 <span class="comment">// ARM mode needs an extra reg0 here due to addrmode2. Will go away once</span>
+<a name="l00713"></a>00713 <span class="comment">// that refactoring is complete (eventually).</span>
+<a name="l00714"></a>00714 <span class="keywordflow">if</span> (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
+<a name="l00715"></a>00715 MIB.<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(0);
+<a name="l00716"></a>00716 MIB.<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>, 4, <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>));
+<a name="l00717"></a>00717 } <span class="keywordflow">else</span>
+<a name="l00718"></a>00718 MIB.<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(4);
+<a name="l00719"></a>00719 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(MIB);
+<a name="l00720"></a>00720 }
+<a name="l00721"></a>00721 Regs.<a class="code" href="classllvm_1_1SmallVectorImpl.html#aac0ea55010b7b1a301e65a0baea057aa">clear</a>();
+<a name="l00722"></a>00722 }
+<a name="l00723"></a>00723 }
+<a name="l00724"></a>00724 <span class="comment"></span>
+<a name="l00725"></a>00725 <span class="comment">/// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers</span>
+<a name="l00726"></a>00726 <span class="comment">/// starting from d8. Also insert stack realignment code and leave the stack</span>
+<a name="l00727"></a>00727 <span class="comment">/// pointer pointing to the d8 spill slot.</span>
+<a name="l00728"></a><a class="code" href="ARMFrameLowering_8cpp.html#a4f2dfb3dbdcb5fd0d650cf3ea1402de4">00728</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="ARMFrameLowering_8cpp.html#a4f2dfb3dbdcb5fd0d650cf3ea1402de4">emitAlignedDPRCS2Spills</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB,
+<a name="l00729"></a>00729 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MI,
+<a name="l00730"></a>00730 <span class="keywordtype">unsigned</span> NumAlignedDPRCS2Regs,
+<a name="l00731"></a>00731 <span class="keyword">const</span> std::vector<CalleeSavedInfo> &CSI,
+<a name="l00732"></a>00732 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI) {
+<a name="l00733"></a>00733 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = *MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l00734"></a>00734 <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l00735"></a>00735 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> DL = MI->getDebugLoc();
+<a name="l00736"></a>00736 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> &TII = *MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>();
+<a name="l00737"></a>00737 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> &MFI = *MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l00738"></a>00738
+<a name="l00739"></a>00739 <span class="comment">// Mark the D-register spill slots as properly aligned. Since MFI computes</span>
+<a name="l00740"></a>00740 <span class="comment">// stack slot layout backwards, this can actually mean that the d-reg stack</span>
+<a name="l00741"></a>00741 <span class="comment">// slot offsets can be wrong. The offset for d8 will always be correct.</span>
+<a name="l00742"></a>00742 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = CSI.size(); i != e; ++i) {
+<a name="l00743"></a>00743 <span class="keywordtype">unsigned</span> DNum = CSI[i].getReg() - <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a>;
+<a name="l00744"></a>00744 <span class="keywordflow">if</span> (DNum >= 8)
+<a name="l00745"></a>00745 <span class="keywordflow">continue</span>;
+<a name="l00746"></a>00746 <span class="keywordtype">int</span> FI = CSI[i].getFrameIdx();
+<a name="l00747"></a>00747 <span class="comment">// The even-numbered registers will be 16-byte aligned, the odd-numbered</span>
+<a name="l00748"></a>00748 <span class="comment">// registers will be 8-byte aligned.</span>
+<a name="l00749"></a>00749 MFI.<a class="code" href="classllvm_1_1MachineFrameInfo.html#a51ea0ff0ba0a43cc30affb68aae1314c" title="setObjectAlignment - Change the alignment of the specified stack object.">setObjectAlignment</a>(FI, DNum % 2 ? 8 : 16);
+<a name="l00750"></a>00750
+<a name="l00751"></a>00751 <span class="comment">// The stack slot for D8 needs to be maximally aligned because this is</span>
+<a name="l00752"></a>00752 <span class="comment">// actually the point where we align the stack pointer. MachineFrameInfo</span>
+<a name="l00753"></a>00753 <span class="comment">// computes all offsets relative to the incoming stack pointer which is a</span>
+<a name="l00754"></a>00754 <span class="comment">// bit weird when realigning the stack. Any extra padding for this</span>
+<a name="l00755"></a>00755 <span class="comment">// over-alignment is not realized because the code inserted below adjusts</span>
+<a name="l00756"></a>00756 <span class="comment">// the stack pointer by numregs * 8 before aligning the stack pointer.</span>
+<a name="l00757"></a>00757 <span class="keywordflow">if</span> (DNum == 0)
+<a name="l00758"></a>00758 MFI.<a class="code" href="classllvm_1_1MachineFrameInfo.html#a51ea0ff0ba0a43cc30affb68aae1314c" title="setObjectAlignment - Change the alignment of the specified stack object.">setObjectAlignment</a>(FI, MFI.<a class="code" href="classllvm_1_1MachineFrameInfo.html#a0af0a11b8eda54e79422c199cb687f5c">getMaxAlignment</a>());
+<a name="l00759"></a>00759 }
+<a name="l00760"></a>00760
+<a name="l00761"></a>00761 <span class="comment">// Move the stack pointer to the d8 spill slot, and align it at the same</span>
+<a name="l00762"></a>00762 <span class="comment">// time. Leave the stack slot address in the scratch register r4.</span>
+<a name="l00763"></a>00763 <span class="comment">//</span>
+<a name="l00764"></a>00764 <span class="comment">// sub r4, sp, #numregs * 8</span>
+<a name="l00765"></a>00765 <span class="comment">// bic r4, r4, #align - 1</span>
+<a name="l00766"></a>00766 <span class="comment">// mov sp, r4</span>
+<a name="l00767"></a>00767 <span class="comment">//</span>
+<a name="l00768"></a>00768 <span class="keywordtype">bool</span> isThumb = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>();
+<a name="l00769"></a>00769 assert(!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>() && <span class="stringliteral">"Can't realign stack for thumb1"</span>);
+<a name="l00770"></a>00770 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#aeebbc8bb36d06a4c62b09481cd3d94cb">setShouldRestoreSPFromFP</a>(<span class="keyword">true</span>);
+<a name="l00771"></a>00771
+<a name="l00772"></a>00772 <span class="comment">// sub r4, sp, #numregs * 8</span>
+<a name="l00773"></a>00773 <span class="comment">// The immediate is <= 64, so it doesn't need any special encoding.</span>
+<a name="l00774"></a>00774 <span class="keywordtype">unsigned</span> Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
+<a name="l00775"></a>00775 <a class="code" href="namespacellvm.html#a8b9edb9ece6ca4b10c73ae93a487c600">AddDefaultCC</a>(<a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(Opc), ARM::R4)
+<a name="l00776"></a>00776 .addReg(ARM::SP)
+<a name="l00777"></a>00777 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(8 * NumAlignedDPRCS2Regs)));
+<a name="l00778"></a>00778
+<a name="l00779"></a>00779 <span class="comment">// bic r4, r4, #align-1</span>
+<a name="l00780"></a>00780 Opc = isThumb ? ARM::t2BICri : ARM::BICri;
+<a name="l00781"></a>00781 <span class="keywordtype">unsigned</span> MaxAlign = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>()-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a0af0a11b8eda54e79422c199cb687f5c">getMaxAlignment</a>();
+<a name="l00782"></a>00782 <a class="code" href="namespacellvm.html#a8b9edb9ece6ca4b10c73ae93a487c600">AddDefaultCC</a>(<a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(Opc), ARM::R4)
+<a name="l00783"></a>00783 .addReg(ARM::R4, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa9ddde91ef09476d28a088fe57f8e2921">RegState::Kill</a>)
+<a name="l00784"></a>00784 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(MaxAlign - 1)));
+<a name="l00785"></a>00785
+<a name="l00786"></a>00786 <span class="comment">// mov sp, r4</span>
+<a name="l00787"></a>00787 <span class="comment">// The stack pointer must be adjusted before spilling anything, otherwise</span>
+<a name="l00788"></a>00788 <span class="comment">// the stack slots could be clobbered by an interrupt handler.</span>
+<a name="l00789"></a>00789 <span class="comment">// Leave r4 live, it is used below.</span>
+<a name="l00790"></a>00790 Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
+<a name="l00791"></a>00791 <a class="code" href="classllvm_1_1MachineInstrBuilder.html">MachineInstrBuilder</a> MIB = <a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(Opc), ARM::SP)
+<a name="l00792"></a>00792 .addReg(ARM::R4);
+<a name="l00793"></a>00793 MIB = <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(MIB);
+<a name="l00794"></a>00794 <span class="keywordflow">if</span> (!isThumb)
+<a name="l00795"></a>00795 <a class="code" href="namespacellvm.html#a8b9edb9ece6ca4b10c73ae93a487c600">AddDefaultCC</a>(MIB);
+<a name="l00796"></a>00796
+<a name="l00797"></a>00797 <span class="comment">// Now spill NumAlignedDPRCS2Regs registers starting from d8.</span>
+<a name="l00798"></a>00798 <span class="comment">// r4 holds the stack slot address.</span>
+<a name="l00799"></a>00799 <span class="keywordtype">unsigned</span> NextReg = <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a>;
+<a name="l00800"></a>00800
+<a name="l00801"></a>00801 <span class="comment">// 16-byte aligned vst1.64 with 4 d-regs and address writeback.</span>
+<a name="l00802"></a>00802 <span class="comment">// The writeback is only needed when emitting two vst1.64 instructions.</span>
+<a name="l00803"></a>00803 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs >= 6) {
+<a name="l00804"></a>00804 <span class="keywordtype">unsigned</span> SupReg = TRI-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#ac2112296600ed4c01c2554d6dfb79f4c">getMatchingSuperReg</a>(NextReg, ARM::dsub_0,
+<a name="l00805"></a>00805 &ARM::QQPRRegClass);
+<a name="l00806"></a>00806 MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ae26efdb76d5c56388c65dc5b02a2ae6f">addLiveIn</a>(SupReg);
+<a name="l00807"></a>00807 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(ARM::VST1d64Qwb_fixed),
+<a name="l00808"></a>00808 ARM::R4)
+<a name="l00809"></a>00809 .addReg(ARM::R4, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa9ddde91ef09476d28a088fe57f8e2921">RegState::Kill</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(16)
+<a name="l00810"></a>00810 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(NextReg)
+<a name="l00811"></a>00811 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(SupReg, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daacff74dc04327bef6824ecb2e3648d0f0">RegState::ImplicitKill</a>));
+<a name="l00812"></a>00812 NextReg += 4;
+<a name="l00813"></a>00813 NumAlignedDPRCS2Regs -= 4;
+<a name="l00814"></a>00814 }
+<a name="l00815"></a>00815
+<a name="l00816"></a>00816 <span class="comment">// We won't modify r4 beyond this point. It currently points to the next</span>
+<a name="l00817"></a>00817 <span class="comment">// register to be spilled.</span>
+<a name="l00818"></a>00818 <span class="keywordtype">unsigned</span> R4BaseReg = NextReg;
+<a name="l00819"></a>00819
+<a name="l00820"></a>00820 <span class="comment">// 16-byte aligned vst1.64 with 4 d-regs, no writeback.</span>
+<a name="l00821"></a>00821 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs >= 4) {
+<a name="l00822"></a>00822 <span class="keywordtype">unsigned</span> SupReg = TRI-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#ac2112296600ed4c01c2554d6dfb79f4c">getMatchingSuperReg</a>(NextReg, ARM::dsub_0,
+<a name="l00823"></a>00823 &ARM::QQPRRegClass);
+<a name="l00824"></a>00824 MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ae26efdb76d5c56388c65dc5b02a2ae6f">addLiveIn</a>(SupReg);
+<a name="l00825"></a>00825 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(ARM::VST1d64Q))
+<a name="l00826"></a>00826 .addReg(ARM::R4).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(16).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(NextReg)
+<a name="l00827"></a>00827 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(SupReg, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daacff74dc04327bef6824ecb2e3648d0f0">RegState::ImplicitKill</a>));
+<a name="l00828"></a>00828 NextReg += 4;
+<a name="l00829"></a>00829 NumAlignedDPRCS2Regs -= 4;
+<a name="l00830"></a>00830 }
+<a name="l00831"></a>00831
+<a name="l00832"></a>00832 <span class="comment">// 16-byte aligned vst1.64 with 2 d-regs.</span>
+<a name="l00833"></a>00833 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs >= 2) {
+<a name="l00834"></a>00834 <span class="keywordtype">unsigned</span> SupReg = TRI-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#ac2112296600ed4c01c2554d6dfb79f4c">getMatchingSuperReg</a>(NextReg, ARM::dsub_0,
+<a name="l00835"></a>00835 &ARM::QPRRegClass);
+<a name="l00836"></a>00836 MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ae26efdb76d5c56388c65dc5b02a2ae6f">addLiveIn</a>(SupReg);
+<a name="l00837"></a>00837 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(ARM::VST1q64))
+<a name="l00838"></a>00838 .addReg(ARM::R4).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(16).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(SupReg));
+<a name="l00839"></a>00839 NextReg += 2;
+<a name="l00840"></a>00840 NumAlignedDPRCS2Regs -= 2;
+<a name="l00841"></a>00841 }
+<a name="l00842"></a>00842
+<a name="l00843"></a>00843 <span class="comment">// Finally, use a vanilla vstr.64 for the odd last register.</span>
+<a name="l00844"></a>00844 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs) {
+<a name="l00845"></a>00845 MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ae26efdb76d5c56388c65dc5b02a2ae6f">addLiveIn</a>(NextReg);
+<a name="l00846"></a>00846 <span class="comment">// vstr.64 uses addrmode5 which has an offset scale of 4.</span>
+<a name="l00847"></a>00847 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(ARM::VSTRD))
+<a name="l00848"></a>00848 .addReg(NextReg)
+<a name="l00849"></a>00849 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ARM::R4).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>((NextReg-R4BaseReg)*2));
+<a name="l00850"></a>00850 }
+<a name="l00851"></a>00851
+<a name="l00852"></a>00852 <span class="comment">// The last spill instruction inserted should kill the scratch register r4.</span>
+<a name="l00853"></a>00853 <a class="code" href="namespacellvm.html#a7923e3e207de8bc1d0d6a5091316ddde">llvm::prior</a>(MI)->addRegisterKilled(ARM::R4, TRI);
+<a name="l00854"></a>00854 }
+<a name="l00855"></a>00855 <span class="comment"></span>
+<a name="l00856"></a>00856 <span class="comment">/// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an</span>
+<a name="l00857"></a>00857 <span class="comment">/// iterator to the following instruction.</span>
+<a name="l00858"></a>00858 <span class="comment"></span><span class="keyword">static</span> <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a>
+<a name="l00859"></a><a class="code" href="ARMFrameLowering_8cpp.html#a0409e368b6e75e93e77f9c29a03edbe9">00859</a> <a class="code" href="ARMFrameLowering_8cpp.html#a0409e368b6e75e93e77f9c29a03edbe9">skipAlignedDPRCS2Spills</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MI,
+<a name="l00860"></a>00860 <span class="keywordtype">unsigned</span> NumAlignedDPRCS2Regs) {
+<a name="l00861"></a>00861 <span class="comment">// sub r4, sp, #numregs * 8</span>
+<a name="l00862"></a>00862 <span class="comment">// bic r4, r4, #align - 1</span>
+<a name="l00863"></a>00863 <span class="comment">// mov sp, r4</span>
+<a name="l00864"></a>00864 ++<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>; ++<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>; ++<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>;
+<a name="l00865"></a>00865 assert(MI->mayStore() && <span class="stringliteral">"Expecting spill instruction"</span>);
+<a name="l00866"></a>00866
+<a name="l00867"></a>00867 <span class="comment">// These switches all fall through.</span>
+<a name="l00868"></a>00868 <span class="keywordflow">switch</span>(NumAlignedDPRCS2Regs) {
+<a name="l00869"></a>00869 <span class="keywordflow">case</span> 7:
+<a name="l00870"></a>00870 ++<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>;
+<a name="l00871"></a>00871 assert(MI->mayStore() && <span class="stringliteral">"Expecting spill instruction"</span>);
+<a name="l00872"></a>00872 <span class="keywordflow">default</span>:
+<a name="l00873"></a>00873 ++<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>;
+<a name="l00874"></a>00874 assert(MI->mayStore() && <span class="stringliteral">"Expecting spill instruction"</span>);
+<a name="l00875"></a>00875 <span class="keywordflow">case</span> 1:
+<a name="l00876"></a>00876 <span class="keywordflow">case</span> 2:
+<a name="l00877"></a>00877 <span class="keywordflow">case</span> 4:
+<a name="l00878"></a>00878 assert(MI->killsRegister(ARM::R4) && <span class="stringliteral">"Missed kill flag"</span>);
+<a name="l00879"></a>00879 ++<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>;
+<a name="l00880"></a>00880 }
+<a name="l00881"></a>00881 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6af6284b830f5e4fe2a8ddb9ff1a25ee46">MI</a>;
+<a name="l00882"></a>00882 }
+<a name="l00883"></a>00883 <span class="comment"></span>
+<a name="l00884"></a>00884 <span class="comment">/// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers</span>
+<a name="l00885"></a>00885 <span class="comment">/// starting from d8. These instructions are assumed to execute while the</span>
+<a name="l00886"></a>00886 <span class="comment">/// stack is still aligned, unlike the code inserted by emitPopInst.</span>
+<a name="l00887"></a><a class="code" href="ARMFrameLowering_8cpp.html#adae3a472b94f467a206557a490dcfc18">00887</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="ARMFrameLowering_8cpp.html#adae3a472b94f467a206557a490dcfc18">emitAlignedDPRCS2Restores</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB,
+<a name="l00888"></a>00888 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MI,
+<a name="l00889"></a>00889 <span class="keywordtype">unsigned</span> NumAlignedDPRCS2Regs,
+<a name="l00890"></a>00890 <span class="keyword">const</span> std::vector<CalleeSavedInfo> &CSI,
+<a name="l00891"></a>00891 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI) {
+<a name="l00892"></a>00892 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = *MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l00893"></a>00893 <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l00894"></a>00894 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> DL = MI->getDebugLoc();
+<a name="l00895"></a>00895 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetInstrInfo.html">TargetInstrInfo</a> &TII = *MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>();
+<a name="l00896"></a>00896
+<a name="l00897"></a>00897 <span class="comment">// Find the frame index assigned to d8.</span>
+<a name="l00898"></a>00898 <span class="keywordtype">int</span> D8SpillFI = 0;
+<a name="l00899"></a>00899 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = CSI.size(); i != e; ++i)
+<a name="l00900"></a>00900 <span class="keywordflow">if</span> (CSI[i].<a class="code" href="MipsDisassembler_8cpp.html#a30bccd0ebacd9892c243f7bd520e4aa0">getReg</a>() == <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a>) {
+<a name="l00901"></a>00901 D8SpillFI = CSI[i].getFrameIdx();
+<a name="l00902"></a>00902 <span class="keywordflow">break</span>;
+<a name="l00903"></a>00903 }
+<a name="l00904"></a>00904
+<a name="l00905"></a>00905 <span class="comment">// Materialize the address of the d8 spill slot into the scratch register r4.</span>
+<a name="l00906"></a>00906 <span class="comment">// This can be fairly complicated if the stack frame is large, so just use</span>
+<a name="l00907"></a>00907 <span class="comment">// the normal frame index elimination mechanism to do it. This code runs as</span>
+<a name="l00908"></a>00908 <span class="comment">// the initial part of the epilog where the stack and base pointers haven't</span>
+<a name="l00909"></a>00909 <span class="comment">// been changed yet.</span>
+<a name="l00910"></a>00910 <span class="keywordtype">bool</span> isThumb = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>();
+<a name="l00911"></a>00911 assert(!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>() && <span class="stringliteral">"Can't realign stack for thumb1"</span>);
+<a name="l00912"></a>00912
+<a name="l00913"></a>00913 <span class="keywordtype">unsigned</span> Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
+<a name="l00914"></a>00914 <a class="code" href="namespacellvm.html#a8b9edb9ece6ca4b10c73ae93a487c600">AddDefaultCC</a>(<a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(Opc), ARM::R4)
+<a name="l00915"></a>00915 .addFrameIndex(D8SpillFI).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(0)));
+<a name="l00916"></a>00916
+<a name="l00917"></a>00917 <span class="comment">// Now restore NumAlignedDPRCS2Regs registers starting from d8.</span>
+<a name="l00918"></a>00918 <span class="keywordtype">unsigned</span> NextReg = <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a>;
+<a name="l00919"></a>00919
+<a name="l00920"></a>00920 <span class="comment">// 16-byte aligned vld1.64 with 4 d-regs and writeback.</span>
+<a name="l00921"></a>00921 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs >= 6) {
+<a name="l00922"></a>00922 <span class="keywordtype">unsigned</span> SupReg = TRI-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#ac2112296600ed4c01c2554d6dfb79f4c">getMatchingSuperReg</a>(NextReg, ARM::dsub_0,
+<a name="l00923"></a>00923 &ARM::QQPRRegClass);
+<a name="l00924"></a>00924 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(ARM::VLD1d64Qwb_fixed), NextReg)
+<a name="l00925"></a>00925 .addReg(ARM::R4, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa72c17e2ff2d5af62a30e56ac152aa8d5">RegState::Define</a>)
+<a name="l00926"></a>00926 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(ARM::R4, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa9ddde91ef09476d28a088fe57f8e2921">RegState::Kill</a>).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(16)
+<a name="l00927"></a>00927 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(SupReg, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa833922eca2ad0eab70573ba1f5fba9af">RegState::ImplicitDefine</a>));
+<a name="l00928"></a>00928 NextReg += 4;
+<a name="l00929"></a>00929 NumAlignedDPRCS2Regs -= 4;
+<a name="l00930"></a>00930 }
+<a name="l00931"></a>00931
+<a name="l00932"></a>00932 <span class="comment">// We won't modify r4 beyond this point. It currently points to the next</span>
+<a name="l00933"></a>00933 <span class="comment">// register to be spilled.</span>
+<a name="l00934"></a>00934 <span class="keywordtype">unsigned</span> R4BaseReg = NextReg;
+<a name="l00935"></a>00935
+<a name="l00936"></a>00936 <span class="comment">// 16-byte aligned vld1.64 with 4 d-regs, no writeback.</span>
+<a name="l00937"></a>00937 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs >= 4) {
+<a name="l00938"></a>00938 <span class="keywordtype">unsigned</span> SupReg = TRI-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#ac2112296600ed4c01c2554d6dfb79f4c">getMatchingSuperReg</a>(NextReg, ARM::dsub_0,
+<a name="l00939"></a>00939 &ARM::QQPRRegClass);
+<a name="l00940"></a>00940 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(ARM::VLD1d64Q), NextReg)
+<a name="l00941"></a>00941 .addReg(ARM::R4).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(16)
+<a name="l00942"></a>00942 .<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a5125cce72b214df09ca8f93dcbbf4c3a">addReg</a>(SupReg, <a class="code" href="namespacellvm_1_1RegState.html#a079b254e749130fbe5d740f314ca92daa833922eca2ad0eab70573ba1f5fba9af">RegState::ImplicitDefine</a>));
+<a name="l00943"></a>00943 NextReg += 4;
+<a name="l00944"></a>00944 NumAlignedDPRCS2Regs -= 4;
+<a name="l00945"></a>00945 }
+<a name="l00946"></a>00946
+<a name="l00947"></a>00947 <span class="comment">// 16-byte aligned vld1.64 with 2 d-regs.</span>
+<a name="l00948"></a>00948 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs >= 2) {
+<a name="l00949"></a>00949 <span class="keywordtype">unsigned</span> SupReg = TRI-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#ac2112296600ed4c01c2554d6dfb79f4c">getMatchingSuperReg</a>(NextReg, ARM::dsub_0,
+<a name="l00950"></a>00950 &ARM::QPRRegClass);
+<a name="l00951"></a>00951 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(ARM::VLD1q64), SupReg)
+<a name="l00952"></a>00952 .addReg(ARM::R4).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(16));
+<a name="l00953"></a>00953 NextReg += 2;
+<a name="l00954"></a>00954 NumAlignedDPRCS2Regs -= 2;
+<a name="l00955"></a>00955 }
+<a name="l00956"></a>00956
+<a name="l00957"></a>00957 <span class="comment">// Finally, use a vanilla vldr.64 for the remaining odd register.</span>
+<a name="l00958"></a>00958 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs)
+<a name="l00959"></a>00959 <a class="code" href="namespacellvm.html#abf7336821a22d9da733af010b2f39089">AddDefaultPred</a>(<a class="code" href="namespacellvm.html#a980570dc1410d4ef53806f82028ca381">BuildMI</a>(MBB, MI, DL, TII.<a class="code" href="classllvm_1_1MCInstrInfo.html#ab16f5a81fccfe4b7f645ba5a74ffad02">get</a>(ARM::VLDRD), NextReg)
+<a name="l00960"></a>00960 .addReg(ARM::R4).<a class="code" href="classllvm_1_1MachineInstrBuilder.html#a9f1fae6a5dbb6e378ca85df1fded8515">addImm</a>(2*(NextReg-R4BaseReg)));
+<a name="l00961"></a>00961
+<a name="l00962"></a>00962 <span class="comment">// Last store kills r4.</span>
+<a name="l00963"></a>00963 <a class="code" href="namespacellvm.html#a7923e3e207de8bc1d0d6a5091316ddde">llvm::prior</a>(MI)->addRegisterKilled(ARM::R4, TRI);
+<a name="l00964"></a>00964 }
+<a name="l00965"></a>00965
+<a name="l00966"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#a640a2dc975accf2c9e8b30f01b1af2d7">00966</a> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a640a2dc975accf2c9e8b30f01b1af2d7">ARMFrameLowering::spillCalleeSavedRegisters</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB,
+<a name="l00967"></a>00967 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MI,
+<a name="l00968"></a>00968 <span class="keyword">const</span> std::vector<CalleeSavedInfo> &CSI,
+<a name="l00969"></a>00969 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI)<span class="keyword"> const </span>{
+<a name="l00970"></a>00970 <span class="keywordflow">if</span> (CSI.empty())
+<a name="l00971"></a>00971 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00972"></a>00972
+<a name="l00973"></a>00973 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = *MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l00974"></a>00974 <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l00975"></a>00975
+<a name="l00976"></a>00976 <span class="keywordtype">unsigned</span> PushOpc = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
+<a name="l00977"></a>00977 <span class="keywordtype">unsigned</span> PushOneOpc = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>() ?
+<a name="l00978"></a>00978 ARM::t2STR_PRE : ARM::STR_PRE_IMM;
+<a name="l00979"></a>00979 <span class="keywordtype">unsigned</span> FltOpc = ARM::VSTMDDB_UPD;
+<a name="l00980"></a>00980 <span class="keywordtype">unsigned</span> NumAlignedDPRCS2Regs = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a70543217b38bd2e8dc926e315a78c930">getNumAlignedDPRCS2Regs</a>();
+<a name="l00981"></a>00981 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, <span class="keyword">false</span>, &<a class="code" href="namespacellvm.html#a80a02a405bb8c0f971331f47ce2efa68">isARMArea1Register</a>, 0,
+<a name="l00982"></a>00982 <a class="code" href="classllvm_1_1MachineInstr.html#aafacf84de1cb994a92dc045f4aa1d518a78f1067d270179dff7915b90a03ce237">MachineInstr::FrameSetup</a>);
+<a name="l00983"></a>00983 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, <span class="keyword">false</span>, &<a class="code" href="namespacellvm.html#a95342556e3188a7e86d532e22f0df8ed">isARMArea2Register</a>, 0,
+<a name="l00984"></a>00984 <a class="code" href="classllvm_1_1MachineInstr.html#aafacf84de1cb994a92dc045f4aa1d518a78f1067d270179dff7915b90a03ce237">MachineInstr::FrameSetup</a>);
+<a name="l00985"></a>00985 emitPushInst(MBB, MI, CSI, FltOpc, 0, <span class="keyword">true</span>, &<a class="code" href="namespacellvm.html#a19c74ab0c04f4300eb23ebc2d1bc338e">isARMArea3Register</a>,
+<a name="l00986"></a>00986 NumAlignedDPRCS2Regs, <a class="code" href="classllvm_1_1MachineInstr.html#aafacf84de1cb994a92dc045f4aa1d518a78f1067d270179dff7915b90a03ce237">MachineInstr::FrameSetup</a>);
+<a name="l00987"></a>00987
+<a name="l00988"></a>00988 <span class="comment">// The code above does not insert spill code for the aligned DPRCS2 registers.</span>
+<a name="l00989"></a>00989 <span class="comment">// The stack realignment code will be inserted between the push instructions</span>
+<a name="l00990"></a>00990 <span class="comment">// and these spills.</span>
+<a name="l00991"></a>00991 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs)
+<a name="l00992"></a>00992 <a class="code" href="ARMFrameLowering_8cpp.html#a4f2dfb3dbdcb5fd0d650cf3ea1402de4">emitAlignedDPRCS2Spills</a>(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
+<a name="l00993"></a>00993
+<a name="l00994"></a>00994 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00995"></a>00995 }
+<a name="l00996"></a>00996
+<a name="l00997"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#a1d0f519b2a4b9e7cd2c2b645ce3496a6">00997</a> <span class="keywordtype">bool</span> <a class="code" href="classllvm_1_1ARMFrameLowering.html#a1d0f519b2a4b9e7cd2c2b645ce3496a6">ARMFrameLowering::restoreCalleeSavedRegisters</a>(<a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB,
+<a name="l00998"></a>00998 <a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> MI,
+<a name="l00999"></a>00999 <span class="keyword">const</span> std::vector<CalleeSavedInfo> &CSI,
+<a name="l01000"></a>01000 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *TRI)<span class="keyword"> const </span>{
+<a name="l01001"></a>01001 <span class="keywordflow">if</span> (CSI.empty())
+<a name="l01002"></a>01002 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01003"></a>01003
+<a name="l01004"></a>01004 <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF = *MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#af2e482ff2a9253ec6bc2285491496bd6">getParent</a>();
+<a name="l01005"></a>01005 <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l01006"></a>01006 <span class="keywordtype">bool</span> isVarArg = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a81e3b6570ae669e775597d683027deea">getVarArgsRegSaveSize</a>() > 0;
+<a name="l01007"></a>01007 <span class="keywordtype">unsigned</span> NumAlignedDPRCS2Regs = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a70543217b38bd2e8dc926e315a78c930">getNumAlignedDPRCS2Regs</a>();
+<a name="l01008"></a>01008
+<a name="l01009"></a>01009 <span class="comment">// The emitPopInst calls below do not insert reloads for the aligned DPRCS2</span>
+<a name="l01010"></a>01010 <span class="comment">// registers. Do that here instead.</span>
+<a name="l01011"></a>01011 <span class="keywordflow">if</span> (NumAlignedDPRCS2Regs)
+<a name="l01012"></a>01012 <a class="code" href="ARMFrameLowering_8cpp.html#adae3a472b94f467a206557a490dcfc18">emitAlignedDPRCS2Restores</a>(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
+<a name="l01013"></a>01013
+<a name="l01014"></a>01014 <span class="keywordtype">unsigned</span> PopOpc = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
+<a name="l01015"></a>01015 <span class="keywordtype">unsigned</span> LdrOpc = AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ae898a405bf69c3021cd998257390494e">isThumbFunction</a>() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM;
+<a name="l01016"></a>01016 <span class="keywordtype">unsigned</span> FltOpc = ARM::VLDMDIA_UPD;
+<a name="l01017"></a>01017 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, <span class="keyword">true</span>, &<a class="code" href="namespacellvm.html#a19c74ab0c04f4300eb23ebc2d1bc338e">isARMArea3Register</a>,
+<a name="l01018"></a>01018 NumAlignedDPRCS2Regs);
+<a name="l01019"></a>01019 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, <span class="keyword">false</span>,
+<a name="l01020"></a>01020 &<a class="code" href="namespacellvm.html#a95342556e3188a7e86d532e22f0df8ed">isARMArea2Register</a>, 0);
+<a name="l01021"></a>01021 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, <span class="keyword">false</span>,
+<a name="l01022"></a>01022 &<a class="code" href="namespacellvm.html#a80a02a405bb8c0f971331f47ce2efa68">isARMArea1Register</a>, 0);
+<a name="l01023"></a>01023
+<a name="l01024"></a>01024 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01025"></a>01025 }
+<a name="l01026"></a>01026
+<a name="l01027"></a>01027 <span class="comment">// FIXME: Make generic?</span>
+<a name="l01028"></a><a class="code" href="ARMFrameLowering_8cpp.html#a740c0449e8ade45d30ba4a00af9e6902">01028</a> <span class="keyword">static</span> <span class="keywordtype">unsigned</span> <a class="code" href="ARMFrameLowering_8cpp.html#a740c0449e8ade45d30ba4a00af9e6902">GetFunctionSizeInBytes</a>(<span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF,
+<a name="l01029"></a>01029 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a> &TII) {
+<a name="l01030"></a>01030 <span class="keywordtype">unsigned</span> FnSize = 0;
+<a name="l01031"></a>01031 <span class="keywordflow">for</span> (<a class="code" href="classllvm_1_1ilist__iterator.html">MachineFunction::const_iterator</a> MBBI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab0789854909cf47f640a85fa2bac29c7">begin</a>(), E = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a9d017af749f76484cb9aec9ff6e4330c">end</a>();
+<a name="l01032"></a>01032 MBBI != E; ++MBBI) {
+<a name="l01033"></a>01033 <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineBasicBlock.html">MachineBasicBlock</a> &MBB = *MBBI;
+<a name="l01034"></a>01034 <span class="keywordflow">for</span> (<a class="code" href="classllvm_1_1MachineBasicBlock.html#a654b11787ac7c4344084d98bea7cf626">MachineBasicBlock::const_iterator</a> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> = MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#ab2d91e7bec944efcbc39d8e30644f111">begin</a>(),E = MBB.<a class="code" href="classllvm_1_1MachineBasicBlock.html#acbc921830578e2741be6549db716c0ce">end</a>();
+<a name="l01035"></a>01035 <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> != E; ++<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>)
+<a name="l01036"></a>01036 FnSize += TII.<a class="code" href="classllvm_1_1ARMBaseInstrInfo.html#aa68427c1132a2d221976f7fb33892dbb">GetInstSizeInBytes</a>(<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>);
+<a name="l01037"></a>01037 }
+<a name="l01038"></a>01038 <span class="keywordflow">return</span> FnSize;
+<a name="l01039"></a>01039 }
+<a name="l01040"></a>01040 <span class="comment"></span>
+<a name="l01041"></a>01041 <span class="comment">/// estimateStackSize - Estimate and return the size of the frame.</span>
+<a name="l01042"></a>01042 <span class="comment">/// FIXME: Make generic?</span>
+<a name="l01043"></a><a class="code" href="ARMFrameLowering_8cpp.html#ad691b80d861c2af67201ff5a21e833cd">01043</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">unsigned</span> <a class="code" href="ARMFrameLowering_8cpp.html#ad691b80d861c2af67201ff5a21e833cd">estimateStackSize</a>(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF) {
+<a name="l01044"></a>01044 <span class="keyword">const</span> <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l01045"></a>01045 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetFrameLowering.html">TargetFrameLowering</a> *TFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a02aa9d4cbd6ffcc70dfe1143ec0995ef">getFrameLowering</a>();
+<a name="l01046"></a>01046 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterInfo.html">TargetRegisterInfo</a> *RegInfo = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a70b47eca6a99c87b81f4c1b1455dc090">getRegisterInfo</a>();
+<a name="l01047"></a>01047 <span class="keywordtype">unsigned</span> MaxAlign = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a0af0a11b8eda54e79422c199cb687f5c">getMaxAlignment</a>();
+<a name="l01048"></a>01048 <span class="keywordtype">int</span> Offset = 0;
+<a name="l01049"></a>01049
+<a name="l01050"></a>01050 <span class="comment">// This code is very, very similar to PEI::calculateFrameObjectOffsets().</span>
+<a name="l01051"></a>01051 <span class="comment">// It really should be refactored to share code. Until then, changes</span>
+<a name="l01052"></a>01052 <span class="comment">// should keep in mind that there's tight coupling between the two.</span>
+<a name="l01053"></a>01053
+<a name="l01054"></a>01054 <span class="keywordflow">for</span> (<span class="keywordtype">int</span> i = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#aefab860460ca482a381a508d36cd9f01">getObjectIndexBegin</a>(); i != 0; ++i) {
+<a name="l01055"></a>01055 <span class="keywordtype">int</span> FixedOff = -MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#aefac52e417d31959e35868879aba672b">getObjectOffset</a>(i);
+<a name="l01056"></a>01056 <span class="keywordflow">if</span> (FixedOff > Offset) Offset = FixedOff;
+<a name="l01057"></a>01057 }
+<a name="l01058"></a>01058 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#ab127d56f832dc4400f58707a37ed5c6b">getObjectIndexEnd</a>(); i != e; ++i) {
+<a name="l01059"></a>01059 <span class="keywordflow">if</span> (MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a639df36670c77819b19f9bdec96634df">isDeadObjectIndex</a>(i))
+<a name="l01060"></a>01060 <span class="keywordflow">continue</span>;
+<a name="l01061"></a>01061 Offset += MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a43386af65581b8de506f3b57ba6c05b0">getObjectSize</a>(i);
+<a name="l01062"></a>01062 <span class="keywordtype">unsigned</span> Align = MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#ae146d6827dae2ff77fc65b7fd319dbb8" title="getObjectAlignment - Return the alignment of the specified stack object.">getObjectAlignment</a>(i);
+<a name="l01063"></a>01063 <span class="comment">// Adjust to alignment boundary</span>
+<a name="l01064"></a>01064 Offset = (Offset+Align-1)/Align*Align;
+<a name="l01065"></a>01065
+<a name="l01066"></a>01066 MaxAlign = std::max(Align, MaxAlign);
+<a name="l01067"></a>01067 }
+<a name="l01068"></a>01068
+<a name="l01069"></a>01069 <span class="keywordflow">if</span> (MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a54aab1c41d2657472b4ea7c9935570c7">adjustsStack</a>() && TFI-><a class="code" href="classllvm_1_1TargetFrameLowering.html#a8404705eb7a27e437ac51ca3730bfd7c">hasReservedCallFrame</a>(MF))
+<a name="l01070"></a>01070 Offset += MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a00e048d1d905fa65ee3377d99d4f2ae3">getMaxCallFrameSize</a>();
+<a name="l01071"></a>01071
+<a name="l01072"></a>01072 <span class="comment">// Round up the size to a multiple of the alignment. If the function has</span>
+<a name="l01073"></a>01073 <span class="comment">// any calls or alloca's, align to the target's StackAlignment value to</span>
+<a name="l01074"></a>01074 <span class="comment">// ensure that the callee's frame or the alloca data is suitably aligned;</span>
+<a name="l01075"></a>01075 <span class="comment">// otherwise, for leaf functions, align to the TransientStackAlignment</span>
+<a name="l01076"></a>01076 <span class="comment">// value.</span>
+<a name="l01077"></a>01077 <span class="keywordtype">unsigned</span> StackAlign;
+<a name="l01078"></a>01078 <span class="keywordflow">if</span> (MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a54aab1c41d2657472b4ea7c9935570c7">adjustsStack</a>() || MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#a5cd76eb2aeed3ae46da1bb1b132f1831">hasVarSizedObjects</a>() ||
+<a name="l01079"></a>01079 (RegInfo-><a class="code" href="classllvm_1_1TargetRegisterInfo.html#adf8e30b3e759b1283c5fbda668190ee6">needsStackRealignment</a>(MF) && MFI-><a class="code" href="classllvm_1_1MachineFrameInfo.html#ab127d56f832dc4400f58707a37ed5c6b">getObjectIndexEnd</a>() != 0))
+<a name="l01080"></a>01080 StackAlign = TFI-><a class="code" href="classllvm_1_1TargetFrameLowering.html#a360555ed6db3b28a33fa5449a0335f19">getStackAlignment</a>();
+<a name="l01081"></a>01081 <span class="keywordflow">else</span>
+<a name="l01082"></a>01082 StackAlign = TFI-><a class="code" href="classllvm_1_1TargetFrameLowering.html#ae78236f4d366f90477811e689d491843">getTransientStackAlignment</a>();
+<a name="l01083"></a>01083
+<a name="l01084"></a>01084 <span class="comment">// If the frame pointer is eliminated, all frame offsets will be relative to</span>
+<a name="l01085"></a>01085 <span class="comment">// SP not FP. Align to MaxAlign so this works.</span>
+<a name="l01086"></a>01086 StackAlign = std::max(StackAlign, MaxAlign);
+<a name="l01087"></a>01087 <span class="keywordtype">unsigned</span> AlignMask = StackAlign - 1;
+<a name="l01088"></a>01088 Offset = (Offset + AlignMask) & ~uint64_t(AlignMask);
+<a name="l01089"></a>01089
+<a name="l01090"></a>01090 <span class="keywordflow">return</span> (<span class="keywordtype">unsigned</span>)Offset;
+<a name="l01091"></a>01091 }
+<a name="l01092"></a>01092 <span class="comment"></span>
+<a name="l01093"></a>01093 <span class="comment">/// estimateRSStackSizeLimit - Look at each instruction that references stack</span>
+<a name="l01094"></a>01094 <span class="comment">/// frames and return the stack size limit beyond which some of these</span>
+<a name="l01095"></a>01095 <span class="comment">/// instructions will require a scratch register during their expansion later.</span>
+<a name="l01096"></a>01096 <span class="comment"></span><span class="comment">// FIXME: Move to TII?</span>
+<a name="l01097"></a><a class="code" href="ARMFrameLowering_8cpp.html#a7df1a51b08978b0d9847f14a0ea0c11b">01097</a> <span class="keyword">static</span> <span class="keywordtype">unsigned</span> <a class="code" href="ARMFrameLowering_8cpp.html#a7df1a51b08978b0d9847f14a0ea0c11b">estimateRSStackSizeLimit</a>(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF,
+<a name="l01098"></a>01098 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetFrameLowering.html">TargetFrameLowering</a> *TFI) {
+<a name="l01099"></a>01099 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l01100"></a>01100 <span class="keywordtype">unsigned</span> Limit = (1 << 12) - 1;
+<a name="l01101"></a>01101 <span class="keywordflow">for</span> (<a class="code" href="classllvm_1_1MachineFunction.html#a340712de3e78fec11c338735cab17df7">MachineFunction::iterator</a> BB = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab0789854909cf47f640a85fa2bac29c7">begin</a>(),E = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a9d017af749f76484cb9aec9ff6e4330c">end</a>(); BB != E; ++BB) {
+<a name="l01102"></a>01102 <span class="keywordflow">for</span> (<a class="code" href="classllvm_1_1MachineBasicBlock.html#ac51be7ff80fe8d6ae5e8c0acb194908a">MachineBasicBlock::iterator</a> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> = BB->begin(), E = BB->end();
+<a name="l01103"></a>01103 <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> != E; ++<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>) {
+<a name="l01104"></a>01104 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>->getNumOperands(); i != e; ++i) {
+<a name="l01105"></a>01105 <span class="keywordflow">if</span> (!<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>->getOperand(i).isFI()) <span class="keywordflow">continue</span>;
+<a name="l01106"></a>01106
+<a name="l01107"></a>01107 <span class="comment">// When using ADDri to get the address of a stack object, 255 is the</span>
+<a name="l01108"></a>01108 <span class="comment">// largest offset guaranteed to fit in the immediate offset.</span>
+<a name="l01109"></a>01109 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>->getOpcode() == ARM::ADDri) {
+<a name="l01110"></a>01110 Limit = std::min(Limit, (1U << 8) - 1);
+<a name="l01111"></a>01111 <span class="keywordflow">break</span>;
+<a name="l01112"></a>01112 }
+<a name="l01113"></a>01113
+<a name="l01114"></a>01114 <span class="comment">// Otherwise check the addressing mode.</span>
+<a name="l01115"></a>01115 <span class="keywordflow">switch</span> (<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>->getDesc().TSFlags & <a class="code" href="namespacellvm_1_1ARMII.html#af4453bdd6e0c946535fe8e8dcc28e784aeda154c828d692cd52ca6cce8765f9ae">ARMII::AddrModeMask</a>) {
+<a name="l01116"></a>01116 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMII.html#ace99f086a3cd38c7477a8f038dae7ff4a3e943d975799a4c55333c54eac1a7991">ARMII::AddrMode3</a>:
+<a name="l01117"></a>01117 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMII.html#ace99f086a3cd38c7477a8f038dae7ff4a976ddbecac99af6819d058790e33e137">ARMII::AddrModeT2_i8</a>:
+<a name="l01118"></a>01118 Limit = std::min(Limit, (1U << 8) - 1);
+<a name="l01119"></a>01119 <span class="keywordflow">break</span>;
+<a name="l01120"></a>01120 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMII.html#ace99f086a3cd38c7477a8f038dae7ff4a0209ae669364c237e24dbc0c4df6036e">ARMII::AddrMode5</a>:
+<a name="l01121"></a>01121 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMII.html#ace99f086a3cd38c7477a8f038dae7ff4af3a6218c9c9bd03381633c799e5226d9">ARMII::AddrModeT2_i8s4</a>:
+<a name="l01122"></a>01122 Limit = std::min(Limit, ((1U << 8) - 1) * 4);
+<a name="l01123"></a>01123 <span class="keywordflow">break</span>;
+<a name="l01124"></a>01124 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMII.html#ace99f086a3cd38c7477a8f038dae7ff4a4f27c00983ba7efdb7177e52c27584b9">ARMII::AddrModeT2_i12</a>:
+<a name="l01125"></a>01125 <span class="comment">// i12 supports only positive offset so these will be converted to</span>
+<a name="l01126"></a>01126 <span class="comment">// i8 opcodes. See llvm::rewriteT2FrameIndex.</span>
+<a name="l01127"></a>01127 <span class="keywordflow">if</span> (TFI-><a class="code" href="classllvm_1_1TargetFrameLowering.html#a59182730437bdb0a45a274261a7ea84b">hasFP</a>(MF) && AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ac39b5595d3a23db77d972ba5b37c4348">hasStackFrame</a>())
+<a name="l01128"></a>01128 Limit = std::min(Limit, (1U << 8) - 1);
+<a name="l01129"></a>01129 <span class="keywordflow">break</span>;
+<a name="l01130"></a>01130 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMII.html#ace99f086a3cd38c7477a8f038dae7ff4a9dbb177d004cae6c3474b6aadc8ae07e">ARMII::AddrMode4</a>:
+<a name="l01131"></a>01131 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMII.html#ace99f086a3cd38c7477a8f038dae7ff4a8388bb748b26edbdb8bb5d5ab6f16853">ARMII::AddrMode6</a>:
+<a name="l01132"></a>01132 <span class="comment">// Addressing modes 4 & 6 (load/store) instructions can't encode an</span>
+<a name="l01133"></a>01133 <span class="comment">// immediate offset for stack references.</span>
+<a name="l01134"></a>01134 <span class="keywordflow">return</span> 0;
+<a name="l01135"></a>01135 <span class="keywordflow">default</span>:
+<a name="l01136"></a>01136 <span class="keywordflow">break</span>;
+<a name="l01137"></a>01137 }
+<a name="l01138"></a>01138 <span class="keywordflow">break</span>; <span class="comment">// At most one FI per instruction</span>
+<a name="l01139"></a>01139 }
+<a name="l01140"></a>01140 }
+<a name="l01141"></a>01141 }
+<a name="l01142"></a>01142
+<a name="l01143"></a>01143 <span class="keywordflow">return</span> Limit;
+<a name="l01144"></a>01144 }
+<a name="l01145"></a>01145
+<a name="l01146"></a>01146 <span class="comment">// In functions that realign the stack, it can be an advantage to spill the</span>
+<a name="l01147"></a>01147 <span class="comment">// callee-saved vector registers after realigning the stack. The vst1 and vld1</span>
+<a name="l01148"></a>01148 <span class="comment">// instructions take alignment hints that can improve performance.</span>
+<a name="l01149"></a>01149 <span class="comment">//</span>
+<a name="l01150"></a><a class="code" href="ARMFrameLowering_8cpp.html#a78730f85f8616e9a8d2361c6e1b79083">01150</a> <span class="keyword">static</span> <span class="keywordtype">void</span> <a class="code" href="ARMFrameLowering_8cpp.html#a78730f85f8616e9a8d2361c6e1b79083">checkNumAlignedDPRCS2Regs</a>(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF) {
+<a name="l01151"></a>01151 MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>()->setNumAlignedDPRCS2Regs(0);
+<a name="l01152"></a>01152 <span class="keywordflow">if</span> (!<a class="code" href="ARMFrameLowering_8cpp.html#a714d5787e4c9238659853436e5fcd83e">SpillAlignedNEONRegs</a>)
+<a name="l01153"></a>01153 <span class="keywordflow">return</span>;
+<a name="l01154"></a>01154
+<a name="l01155"></a>01155 <span class="comment">// Naked functions don't spill callee-saved registers.</span>
+<a name="l01156"></a>01156 <span class="keywordflow">if</span> (MF.<a class="code" href="classllvm_1_1MachineFunction.html#ad784a6594990530bffb2018aeeed56f3">getFunction</a>()-><a class="code" href="classllvm_1_1Function.html#aceca681da32da537bfd9f00dcf371278">getFnAttributes</a>().<a class="code" href="classllvm_1_1Attributes.html#ad68a7be4af7d92f3df681e13acbacc13" title="Return true if the attribute is present.">hasAttribute</a>(<a class="code" href="classllvm_1_1Attributes.html#a92f64dbb86772103c557c491dc1ebbe9a13a346330e03a91a877e4ae938ff10ce" title="Naked function.">Attributes::Naked</a>))
+<a name="l01157"></a>01157 <span class="keywordflow">return</span>;
+<a name="l01158"></a>01158
+<a name="l01159"></a>01159 <span class="comment">// We are planning to use NEON instructions vst1 / vld1.</span>
+<a name="l01160"></a>01160 <span class="keywordflow">if</span> (!MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a5af2fed99951774b6a14d30ec6e73792">getSubtarget</a><<a class="code" href="classllvm_1_1ARMSubtarget.html">ARMSubtarget</a>>().hasNEON())
+<a name="l01161"></a>01161 <span class="keywordflow">return</span>;
+<a name="l01162"></a>01162
+<a name="l01163"></a>01163 <span class="comment">// Don't bother if the default stack alignment is sufficiently high.</span>
+<a name="l01164"></a>01164 <span class="keywordflow">if</span> (MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a02aa9d4cbd6ffcc70dfe1143ec0995ef">getFrameLowering</a>()-><a class="code" href="classllvm_1_1TargetFrameLowering.html#a360555ed6db3b28a33fa5449a0335f19">getStackAlignment</a>() >= 8)
+<a name="l01165"></a>01165 <span class="keywordflow">return</span>;
+<a name="l01166"></a>01166
+<a name="l01167"></a>01167 <span class="comment">// Aligned spills require stack realignment.</span>
+<a name="l01168"></a>01168 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html">ARMBaseRegisterInfo</a> *RegInfo =
+<a name="l01169"></a>01169 <span class="keyword">static_cast<</span><span class="keyword">const </span><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html">ARMBaseRegisterInfo</a>*<span class="keyword">></span>(MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a70b47eca6a99c87b81f4c1b1455dc090">getRegisterInfo</a>());
+<a name="l01170"></a>01170 <span class="keywordflow">if</span> (!RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#acb882a567e74f592cbac2ca930b7bf73">canRealignStack</a>(MF))
+<a name="l01171"></a>01171 <span class="keywordflow">return</span>;
+<a name="l01172"></a>01172
+<a name="l01173"></a>01173 <span class="comment">// We always spill contiguous d-registers starting from d8. Count how many</span>
+<a name="l01174"></a>01174 <span class="comment">// needs spilling. The register allocator will almost always use the</span>
+<a name="l01175"></a>01175 <span class="comment">// callee-saved registers in order, but it can happen that there are holes in</span>
+<a name="l01176"></a>01176 <span class="comment">// the range. Registers above the hole will be spilled to the standard DPRCS</span>
+<a name="l01177"></a>01177 <span class="comment">// area.</span>
+<a name="l01178"></a>01178 <a class="code" href="classllvm_1_1MachineRegisterInfo.html">MachineRegisterInfo</a> &MRI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>();
+<a name="l01179"></a>01179 <span class="keywordtype">unsigned</span> NumSpills = 0;
+<a name="l01180"></a>01180 <span class="keywordflow">for</span> (; NumSpills < 8; ++NumSpills)
+<a name="l01181"></a>01181 <span class="keywordflow">if</span> (!MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#abe3c98b9803fa6a21eca279173c27b12">isPhysRegUsed</a>(<a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933a07946dc85f27c45b26fd857ce791f74a">ARM::D8</a> + NumSpills))
+<a name="l01182"></a>01182 <span class="keywordflow">break</span>;
+<a name="l01183"></a>01183
+<a name="l01184"></a>01184 <span class="comment">// Don't do this for just one d-register. It's not worth it.</span>
+<a name="l01185"></a>01185 <span class="keywordflow">if</span> (NumSpills < 2)
+<a name="l01186"></a>01186 <span class="keywordflow">return</span>;
+<a name="l01187"></a>01187
+<a name="l01188"></a>01188 <span class="comment">// Spill the first NumSpills D-registers after realigning the stack.</span>
+<a name="l01189"></a>01189 MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>()->setNumAlignedDPRCS2Regs(NumSpills);
+<a name="l01190"></a>01190
+<a name="l01191"></a>01191 <span class="comment">// A scratch register is required for the vst1 / vld1 instructions.</span>
+<a name="l01192"></a>01192 MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>().<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(ARM::R4);
+<a name="l01193"></a>01193 }
+<a name="l01194"></a>01194
+<a name="l01195"></a>01195 <span class="keywordtype">void</span>
+<a name="l01196"></a><a class="code" href="classllvm_1_1ARMFrameLowering.html#ab34b589c79a85cd7182f9f979ce368cc">01196</a> <a class="code" href="classllvm_1_1ARMFrameLowering.html#ab34b589c79a85cd7182f9f979ce368cc">ARMFrameLowering::processFunctionBeforeCalleeSavedScan</a>(<a class="code" href="classllvm_1_1MachineFunction.html">MachineFunction</a> &MF,
+<a name="l01197"></a>01197 <a class="code" href="classllvm_1_1RegScavenger.html">RegScavenger</a> *RS)<span class="keyword"> const </span>{
+<a name="l01198"></a>01198 <span class="comment">// This tells PEI to spill the FP as if it is any other callee-save register</span>
+<a name="l01199"></a>01199 <span class="comment">// to take advantage the eliminateFrameIndex machinery. This also ensures it</span>
+<a name="l01200"></a>01200 <span class="comment">// is spilled in the order specified by getCalleeSavedRegs() to make it easier</span>
+<a name="l01201"></a>01201 <span class="comment">// to combine multiple loads / stores.</span>
+<a name="l01202"></a>01202 <span class="keywordtype">bool</span> CanEliminateFrame = <span class="keyword">true</span>;
+<a name="l01203"></a>01203 <span class="keywordtype">bool</span> CS1Spilled = <span class="keyword">false</span>;
+<a name="l01204"></a>01204 <span class="keywordtype">bool</span> LRSpilled = <span class="keyword">false</span>;
+<a name="l01205"></a>01205 <span class="keywordtype">unsigned</span> NumGPRSpills = 0;
+<a name="l01206"></a>01206 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<unsigned, 4></a> UnspilledCS1GPRs;
+<a name="l01207"></a>01207 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<unsigned, 4></a> UnspilledCS2GPRs;
+<a name="l01208"></a>01208 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html">ARMBaseRegisterInfo</a> *RegInfo =
+<a name="l01209"></a>01209 <span class="keyword">static_cast<</span><span class="keyword">const </span><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html">ARMBaseRegisterInfo</a>*<span class="keyword">></span>(MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#a70b47eca6a99c87b81f4c1b1455dc090">getRegisterInfo</a>());
+<a name="l01210"></a>01210 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a> &TII =
+<a name="l01211"></a>01211 *<span class="keyword">static_cast<</span><span class="keyword">const </span><a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a>*<span class="keyword">></span>(MF.<a class="code" href="classllvm_1_1MachineFunction.html#a6745c3bfdfc5b0643b078b96df2db252">getTarget</a>().<a class="code" href="classllvm_1_1TargetMachine.html#ac13d0f6f2c915757013b101ef6e8afbc">getInstrInfo</a>());
+<a name="l01212"></a>01212 <a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a> *AFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ac2dc0fa143c9f2127f0501734577a0a0">getInfo</a><<a class="code" href="classllvm_1_1ARMFunctionInfo.html">ARMFunctionInfo</a>>();
+<a name="l01213"></a>01213 <a class="code" href="classllvm_1_1MachineFrameInfo.html" title="Abstract Stack Frame Information.">MachineFrameInfo</a> *MFI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#a4ad4295a88187ea1ae12ecfcfa18a70f">getFrameInfo</a>();
+<a name="l01214"></a>01214 <a class="code" href="classllvm_1_1MachineRegisterInfo.html">MachineRegisterInfo</a> &MRI = MF.<a class="code" href="classllvm_1_1MachineFunction.html#ab4a6ca428289b667dd691a00e9f7e334">getRegInfo</a>();
+<a name="l01215"></a>01215 <span class="keywordtype">unsigned</span> FramePtr = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a47e108ecd9a21cb626ea629490f45e25">getFrameRegister</a>(MF);
+<a name="l01216"></a>01216
+<a name="l01217"></a>01217 <span class="comment">// Spill R4 if Thumb2 function requires stack realignment - it will be used as</span>
+<a name="l01218"></a>01218 <span class="comment">// scratch register. Also spill R4 if Thumb2 function has varsized objects,</span>
+<a name="l01219"></a>01219 <span class="comment">// since it's not always possible to restore sp from fp in a single</span>
+<a name="l01220"></a>01220 <span class="comment">// instruction.</span>
+<a name="l01221"></a>01221 <span class="comment">// FIXME: It will be better just to find spare register here.</span>
+<a name="l01222"></a>01222 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a07c23410c7430f86085eadea31db3ee2">isThumb2Function</a>() &&
+<a name="l01223"></a>01223 (MFI->hasVarSizedObjects() || RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a01ecb9dfd78defd2dee58c89c443463a">needsStackRealignment</a>(MF)))
+<a name="l01224"></a>01224 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(ARM::R4);
+<a name="l01225"></a>01225
+<a name="l01226"></a>01226 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>()) {
+<a name="l01227"></a>01227 <span class="comment">// Spill LR if Thumb1 function uses variable length argument lists.</span>
+<a name="l01228"></a>01228 <span class="keywordflow">if</span> (AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a81e3b6570ae669e775597d683027deea">getVarArgsRegSaveSize</a>() > 0)
+<a name="l01229"></a>01229 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(ARM::LR);
+<a name="l01230"></a>01230
+<a name="l01231"></a>01231 <span class="comment">// Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know</span>
+<a name="l01232"></a>01232 <span class="comment">// for sure what the stack size will be, but for this, an estimate is good</span>
+<a name="l01233"></a>01233 <span class="comment">// enough. If there anything changes it, it'll be a spill, which implies</span>
+<a name="l01234"></a>01234 <span class="comment">// we've used all the registers and so R4 is already used, so not marking</span>
+<a name="l01235"></a>01235 <span class="comment">// it here will be OK.</span>
+<a name="l01236"></a>01236 <span class="comment">// FIXME: It will be better just to find spare register here.</span>
+<a name="l01237"></a>01237 <span class="keywordtype">unsigned</span> StackSize = <a class="code" href="ARMFrameLowering_8cpp.html#ad691b80d861c2af67201ff5a21e833cd">estimateStackSize</a>(MF);
+<a name="l01238"></a>01238 <span class="keywordflow">if</span> (MFI->hasVarSizedObjects() || StackSize > 508)
+<a name="l01239"></a>01239 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(ARM::R4);
+<a name="l01240"></a>01240 }
+<a name="l01241"></a>01241
+<a name="l01242"></a>01242 <span class="comment">// See if we can spill vector registers to aligned stack.</span>
+<a name="l01243"></a>01243 <a class="code" href="ARMFrameLowering_8cpp.html#a78730f85f8616e9a8d2361c6e1b79083">checkNumAlignedDPRCS2Regs</a>(MF);
+<a name="l01244"></a>01244
+<a name="l01245"></a>01245 <span class="comment">// Spill the BasePtr if it's used.</span>
+<a name="l01246"></a>01246 <span class="keywordflow">if</span> (RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a0e3e26dbde5eb40a63a5ed4220cf6211">hasBasePointer</a>(MF))
+<a name="l01247"></a>01247 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a4682c4f655dfb10da71ef7d649465d58">getBaseRegister</a>());
+<a name="l01248"></a>01248
+<a name="l01249"></a>01249 <span class="comment">// Don't spill FP if the frame can be eliminated. This is determined</span>
+<a name="l01250"></a>01250 <span class="comment">// by scanning the callee-save registers to see if any is used.</span>
+<a name="l01251"></a>01251 <span class="keyword">const</span> uint16_t *CSRegs = RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a141fe016bee792f7ad8aca26c4032815" title="Code Generation virtual methods...">getCalleeSavedRegs</a>();
+<a name="l01252"></a>01252 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0; CSRegs[i]; ++i) {
+<a name="l01253"></a>01253 <span class="keywordtype">unsigned</span> Reg = CSRegs[i];
+<a name="l01254"></a>01254 <span class="keywordtype">bool</span> Spilled = <span class="keyword">false</span>;
+<a name="l01255"></a>01255 <span class="keywordflow">if</span> (MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#abe3c98b9803fa6a21eca279173c27b12">isPhysRegUsed</a>(Reg)) {
+<a name="l01256"></a>01256 Spilled = <span class="keyword">true</span>;
+<a name="l01257"></a>01257 CanEliminateFrame = <span class="keyword">false</span>;
+<a name="l01258"></a>01258 }
+<a name="l01259"></a>01259
+<a name="l01260"></a>01260 <span class="keywordflow">if</span> (!ARM::GPRRegClass.contains(Reg))
+<a name="l01261"></a>01261 <span class="keywordflow">continue</span>;
+<a name="l01262"></a>01262
+<a name="l01263"></a>01263 <span class="keywordflow">if</span> (Spilled) {
+<a name="l01264"></a>01264 NumGPRSpills++;
+<a name="l01265"></a>01265
+<a name="l01266"></a>01266 <span class="keywordflow">if</span> (!<a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a80f7cdbc91b73599f8319c4a88c7ca18">isTargetIOS</a>()) {
+<a name="l01267"></a>01267 <span class="keywordflow">if</span> (Reg == ARM::LR)
+<a name="l01268"></a>01268 LRSpilled = <span class="keyword">true</span>;
+<a name="l01269"></a>01269 CS1Spilled = <span class="keyword">true</span>;
+<a name="l01270"></a>01270 <span class="keywordflow">continue</span>;
+<a name="l01271"></a>01271 }
+<a name="l01272"></a>01272
+<a name="l01273"></a>01273 <span class="comment">// Keep track if LR and any of R4, R5, R6, and R7 is spilled.</span>
+<a name="l01274"></a>01274 <span class="keywordflow">switch</span> (Reg) {
+<a name="l01275"></a>01275 <span class="keywordflow">case</span> ARM::LR:
+<a name="l01276"></a>01276 LRSpilled = <span class="keyword">true</span>;
+<a name="l01277"></a>01277 <span class="comment">// Fallthrough</span>
+<a name="l01278"></a>01278 <span class="keywordflow">case</span> ARM::R4: <span class="keywordflow">case</span> ARM::R5:
+<a name="l01279"></a>01279 <span class="keywordflow">case</span> ARM::R6: <span class="keywordflow">case</span> ARM::R7:
+<a name="l01280"></a>01280 CS1Spilled = <span class="keyword">true</span>;
+<a name="l01281"></a>01281 <span class="keywordflow">break</span>;
+<a name="l01282"></a>01282 <span class="keywordflow">default</span>:
+<a name="l01283"></a>01283 <span class="keywordflow">break</span>;
+<a name="l01284"></a>01284 }
+<a name="l01285"></a>01285 } <span class="keywordflow">else</span> {
+<a name="l01286"></a>01286 <span class="keywordflow">if</span> (!<a class="code" href="classllvm_1_1ARMFrameLowering.html#adc26971dee5e964321b8ea6daa72639d">STI</a>.<a class="code" href="classllvm_1_1ARMSubtarget.html#a80f7cdbc91b73599f8319c4a88c7ca18">isTargetIOS</a>()) {
+<a name="l01287"></a>01287 UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg);
+<a name="l01288"></a>01288 <span class="keywordflow">continue</span>;
+<a name="l01289"></a>01289 }
+<a name="l01290"></a>01290
+<a name="l01291"></a>01291 <span class="keywordflow">switch</span> (Reg) {
+<a name="l01292"></a>01292 <span class="keywordflow">case</span> ARM::R4: <span class="keywordflow">case</span> ARM::R5:
+<a name="l01293"></a>01293 <span class="keywordflow">case</span> ARM::R6: <span class="keywordflow">case</span> ARM::R7:
+<a name="l01294"></a>01294 <span class="keywordflow">case</span> ARM::LR:
+<a name="l01295"></a>01295 UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg);
+<a name="l01296"></a>01296 <span class="keywordflow">break</span>;
+<a name="l01297"></a>01297 <span class="keywordflow">default</span>:
+<a name="l01298"></a>01298 UnspilledCS2GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg);
+<a name="l01299"></a>01299 <span class="keywordflow">break</span>;
+<a name="l01300"></a>01300 }
+<a name="l01301"></a>01301 }
+<a name="l01302"></a>01302 }
+<a name="l01303"></a>01303
+<a name="l01304"></a>01304 <span class="keywordtype">bool</span> ForceLRSpill = <span class="keyword">false</span>;
+<a name="l01305"></a>01305 <span class="keywordflow">if</span> (!LRSpilled && AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>()) {
+<a name="l01306"></a>01306 <span class="keywordtype">unsigned</span> FnSize = <a class="code" href="ARMFrameLowering_8cpp.html#a740c0449e8ade45d30ba4a00af9e6902">GetFunctionSizeInBytes</a>(MF, TII);
+<a name="l01307"></a>01307 <span class="comment">// Force LR to be spilled if the Thumb function size is > 2048. This enables</span>
+<a name="l01308"></a>01308 <span class="comment">// use of BL to implement far jump. If it turns out that it's not needed</span>
+<a name="l01309"></a>01309 <span class="comment">// then the branch fix up path will undo it.</span>
+<a name="l01310"></a>01310 <span class="keywordflow">if</span> (FnSize >= (1 << 11)) {
+<a name="l01311"></a>01311 CanEliminateFrame = <span class="keyword">false</span>;
+<a name="l01312"></a>01312 ForceLRSpill = <span class="keyword">true</span>;
+<a name="l01313"></a>01313 }
+<a name="l01314"></a>01314 }
+<a name="l01315"></a>01315
+<a name="l01316"></a>01316 <span class="comment">// If any of the stack slot references may be out of range of an immediate</span>
+<a name="l01317"></a>01317 <span class="comment">// offset, make sure a register (or a spill slot) is available for the</span>
+<a name="l01318"></a>01318 <span class="comment">// register scavenger. Note that if we're indexing off the frame pointer, the</span>
+<a name="l01319"></a>01319 <span class="comment">// effective stack size is 4 bytes larger since the FP points to the stack</span>
+<a name="l01320"></a>01320 <span class="comment">// slot of the previous FP. Also, if we have variable sized objects in the</span>
+<a name="l01321"></a>01321 <span class="comment">// function, stack slot references will often be negative, and some of</span>
+<a name="l01322"></a>01322 <span class="comment">// our instructions are positive-offset only, so conservatively consider</span>
+<a name="l01323"></a>01323 <span class="comment">// that case to want a spill slot (or register) as well. Similarly, if</span>
+<a name="l01324"></a>01324 <span class="comment">// the function adjusts the stack pointer during execution and the</span>
+<a name="l01325"></a>01325 <span class="comment">// adjustments aren't already part of our stack size estimate, our offset</span>
+<a name="l01326"></a>01326 <span class="comment">// calculations may be off, so be conservative.</span>
+<a name="l01327"></a>01327 <span class="comment">// FIXME: We could add logic to be more precise about negative offsets</span>
+<a name="l01328"></a>01328 <span class="comment">// and which instructions will need a scratch register for them. Is it</span>
+<a name="l01329"></a>01329 <span class="comment">// worth the effort and added fragility?</span>
+<a name="l01330"></a>01330 <span class="keywordtype">bool</span> BigStack =
+<a name="l01331"></a>01331 (RS &&
+<a name="l01332"></a>01332 (<a class="code" href="ARMFrameLowering_8cpp.html#ad691b80d861c2af67201ff5a21e833cd">estimateStackSize</a>(MF) + ((<a class="code" href="classllvm_1_1ARMFrameLowering.html#a9c8349fdf1c2f7ed13cd1a1bd1aeb19e">hasFP</a>(MF) && AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#ac39b5595d3a23db77d972ba5b37c4348">hasStackFrame</a>()) ? 4:0) >=
+<a name="l01333"></a>01333 <a class="code" href="ARMFrameLowering_8cpp.html#a7df1a51b08978b0d9847f14a0ea0c11b">estimateRSStackSizeLimit</a>(MF, <span class="keyword">this</span>)))
+<a name="l01334"></a>01334 || MFI->hasVarSizedObjects()
+<a name="l01335"></a>01335 || (MFI->adjustsStack() && !<a class="code" href="classllvm_1_1ARMFrameLowering.html#a68fb321e1ddcf431572aa4d374c3baad">canSimplifyCallFramePseudos</a>(MF));
+<a name="l01336"></a>01336
+<a name="l01337"></a>01337 <span class="keywordtype">bool</span> ExtraCSSpill = <span class="keyword">false</span>;
+<a name="l01338"></a>01338 <span class="keywordflow">if</span> (BigStack || !CanEliminateFrame || RegInfo-><a class="code" href="classllvm_1_1ARMBaseRegisterInfo.html#a77cbba4423b35e9f705d45d70085cec2">cannotEliminateFrame</a>(MF)) {
+<a name="l01339"></a>01339 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a5e9f6fe4d5ecd84c637b458a75dcc845">setHasStackFrame</a>(<span class="keyword">true</span>);
+<a name="l01340"></a>01340
+<a name="l01341"></a>01341 <span class="comment">// If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.</span>
+<a name="l01342"></a>01342 <span class="comment">// Spill LR as well so we can fold BX_RET to the registers restore (LDM).</span>
+<a name="l01343"></a>01343 <span class="keywordflow">if</span> (!LRSpilled && CS1Spilled) {
+<a name="l01344"></a>01344 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(ARM::LR);
+<a name="l01345"></a>01345 NumGPRSpills++;
+<a name="l01346"></a>01346 UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorImpl.html#a18c110c35e9133222a37b28d30f8a90f">erase</a>(std::find(UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a8a045d250952c0867382a9840ee18fdf">begin</a>(),
+<a name="l01347"></a>01347 UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a075e34e98605d0e7c289763a104869ac">end</a>(), (<a class="code" href="classunsigned.html">unsigned</a>)ARM::LR));
+<a name="l01348"></a>01348 ForceLRSpill = <span class="keyword">false</span>;
+<a name="l01349"></a>01349 ExtraCSSpill = <span class="keyword">true</span>;
+<a name="l01350"></a>01350 }
+<a name="l01351"></a>01351
+<a name="l01352"></a>01352 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ARMFrameLowering.html#a9c8349fdf1c2f7ed13cd1a1bd1aeb19e">hasFP</a>(MF)) {
+<a name="l01353"></a>01353 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(FramePtr);
+<a name="l01354"></a>01354 NumGPRSpills++;
+<a name="l01355"></a>01355 }
+<a name="l01356"></a>01356
+<a name="l01357"></a>01357 <span class="comment">// If stack and double are 8-byte aligned and we are spilling an odd number</span>
+<a name="l01358"></a>01358 <span class="comment">// of GPRs, spill one extra callee save GPR so we won't have to pad between</span>
+<a name="l01359"></a>01359 <span class="comment">// the integer and double callee save areas.</span>
+<a name="l01360"></a>01360 <span class="keywordtype">unsigned</span> TargetAlign = <a class="code" href="classllvm_1_1TargetFrameLowering.html#a360555ed6db3b28a33fa5449a0335f19">getStackAlignment</a>();
+<a name="l01361"></a>01361 <span class="keywordflow">if</span> (TargetAlign == 8 && (NumGPRSpills & 1)) {
+<a name="l01362"></a>01362 <span class="keywordflow">if</span> (CS1Spilled && !UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>()) {
+<a name="l01363"></a>01363 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i != e; ++i) {
+<a name="l01364"></a>01364 <span class="keywordtype">unsigned</span> Reg = UnspilledCS1GPRs[i];
+<a name="l01365"></a>01365 <span class="comment">// Don't spill high register if the function is thumb1</span>
+<a name="l01366"></a>01366 <span class="keywordflow">if</span> (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>() ||
+<a name="l01367"></a>01367 <a class="code" href="namespacellvm.html#a69b805d50f05b869ab969f6853b8531c">isARMLowRegister</a>(Reg) || Reg == ARM::LR) {
+<a name="l01368"></a>01368 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(Reg);
+<a name="l01369"></a>01369 <span class="keywordflow">if</span> (!MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a008f499ae277e4936b5b897ddb4bcb7e">isReserved</a>(Reg))
+<a name="l01370"></a>01370 ExtraCSSpill = <span class="keyword">true</span>;
+<a name="l01371"></a>01371 <span class="keywordflow">break</span>;
+<a name="l01372"></a>01372 }
+<a name="l01373"></a>01373 }
+<a name="l01374"></a>01374 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (!UnspilledCS2GPRs.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>() && !AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>()) {
+<a name="l01375"></a>01375 <span class="keywordtype">unsigned</span> Reg = UnspilledCS2GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a58dc840fc84420b7f0b773794b8101c1">front</a>();
+<a name="l01376"></a>01376 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(Reg);
+<a name="l01377"></a>01377 <span class="keywordflow">if</span> (!MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a008f499ae277e4936b5b897ddb4bcb7e">isReserved</a>(Reg))
+<a name="l01378"></a>01378 ExtraCSSpill = <span class="keyword">true</span>;
+<a name="l01379"></a>01379 }
+<a name="l01380"></a>01380 }
+<a name="l01381"></a>01381
+<a name="l01382"></a>01382 <span class="comment">// Estimate if we might need to scavenge a register at some point in order</span>
+<a name="l01383"></a>01383 <span class="comment">// to materialize a stack offset. If so, either spill one additional</span>
+<a name="l01384"></a>01384 <span class="comment">// callee-saved register or reserve a special spill slot to facilitate</span>
+<a name="l01385"></a>01385 <span class="comment">// register scavenging. Thumb1 needs a spill slot for stack pointer</span>
+<a name="l01386"></a>01386 <span class="comment">// adjustments also, even when the frame itself is small.</span>
+<a name="l01387"></a>01387 <span class="keywordflow">if</span> (BigStack && !ExtraCSSpill) {
+<a name="l01388"></a>01388 <span class="comment">// If any non-reserved CS register isn't spilled, just spill one or two</span>
+<a name="l01389"></a>01389 <span class="comment">// extra. That should take care of it!</span>
+<a name="l01390"></a>01390 <span class="keywordtype">unsigned</span> NumExtras = TargetAlign / 4;
+<a name="l01391"></a>01391 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<unsigned, 2></a> Extras;
+<a name="l01392"></a>01392 <span class="keywordflow">while</span> (NumExtras && !UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>()) {
+<a name="l01393"></a>01393 <span class="keywordtype">unsigned</span> Reg = UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#acd9e771a3296c6b24146955754620557">back</a>();
+<a name="l01394"></a>01394 UnspilledCS1GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#a1f2303df9bbee2233c11d61c2f6f7930">pop_back</a>();
+<a name="l01395"></a>01395 <span class="keywordflow">if</span> (!MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a008f499ae277e4936b5b897ddb4bcb7e">isReserved</a>(Reg) &&
+<a name="l01396"></a>01396 (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>() || <a class="code" href="namespacellvm.html#a69b805d50f05b869ab969f6853b8531c">isARMLowRegister</a>(Reg) ||
+<a name="l01397"></a>01397 Reg == ARM::LR)) {
+<a name="l01398"></a>01398 Extras.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg);
+<a name="l01399"></a>01399 NumExtras--;
+<a name="l01400"></a>01400 }
+<a name="l01401"></a>01401 }
+<a name="l01402"></a>01402 <span class="comment">// For non-Thumb1 functions, also check for hi-reg CS registers</span>
+<a name="l01403"></a>01403 <span class="keywordflow">if</span> (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>()) {
+<a name="l01404"></a>01404 <span class="keywordflow">while</span> (NumExtras && !UnspilledCS2GPRs.<a class="code" href="classllvm_1_1SmallVectorBase.html#afdecfccba9b1fd8c9fd8eb27ae69e9a0">empty</a>()) {
+<a name="l01405"></a>01405 <span class="keywordtype">unsigned</span> Reg = UnspilledCS2GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#acd9e771a3296c6b24146955754620557">back</a>();
+<a name="l01406"></a>01406 UnspilledCS2GPRs.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#a1f2303df9bbee2233c11d61c2f6f7930">pop_back</a>();
+<a name="l01407"></a>01407 <span class="keywordflow">if</span> (!MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a008f499ae277e4936b5b897ddb4bcb7e">isReserved</a>(Reg)) {
+<a name="l01408"></a>01408 Extras.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg);
+<a name="l01409"></a>01409 NumExtras--;
+<a name="l01410"></a>01410 }
+<a name="l01411"></a>01411 }
+<a name="l01412"></a>01412 }
+<a name="l01413"></a>01413 <span class="keywordflow">if</span> (Extras.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>() && NumExtras == 0) {
+<a name="l01414"></a>01414 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> i = 0, e = Extras.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>(); i != e; ++i) {
+<a name="l01415"></a>01415 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(Extras[i]);
+<a name="l01416"></a>01416 }
+<a name="l01417"></a>01417 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (!AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a9fc3ff683e379f509b4d04ae1d5ace8a">isThumb1OnlyFunction</a>()) {
+<a name="l01418"></a>01418 <span class="comment">// note: Thumb1 functions spill to R12, not the stack. Reserve a slot</span>
+<a name="l01419"></a>01419 <span class="comment">// closest to SP or frame pointer.</span>
+<a name="l01420"></a>01420 <span class="keyword">const</span> <a class="code" href="classllvm_1_1TargetRegisterClass.html">TargetRegisterClass</a> *RC = &ARM::GPRRegClass;
+<a name="l01421"></a>01421 RS-><a class="code" href="classllvm_1_1RegScavenger.html#aa0230958e154a761beabce131f0ab33a">setScavengingFrameIndex</a>(MFI->CreateStackObject(RC-><a class="code" href="classllvm_1_1TargetRegisterClass.html#ae220352610e3badb61763dcbae9b7a6f">getSize</a>(),
+<a name="l01422"></a>01422 RC-><a class="code" href="classllvm_1_1TargetRegisterClass.html#a4a1a710a4decff4f7ffe926b10045d74">getAlignment</a>(),
+<a name="l01423"></a>01423 <span class="keyword">false</span>));
+<a name="l01424"></a>01424 }
+<a name="l01425"></a>01425 }
+<a name="l01426"></a>01426 }
+<a name="l01427"></a>01427
+<a name="l01428"></a>01428 <span class="keywordflow">if</span> (ForceLRSpill) {
+<a name="l01429"></a>01429 MRI.<a class="code" href="classllvm_1_1MachineRegisterInfo.html#a8102e337f77143271ef8ccd4ea2546b3">setPhysRegUsed</a>(ARM::LR);
+<a name="l01430"></a>01430 AFI-><a class="code" href="classllvm_1_1ARMFunctionInfo.html#a2cc370b8de4fd1b5595af34acccf5887">setLRIsSpilledForFarJump</a>(<span class="keyword">true</span>);
+<a name="l01431"></a>01431 }
+<a name="l01432"></a>01432 }
+</pre></div></div>
+</div>
+<hr>
+<p class="footer">
+Generated on Fri Dec 21 2012 00:32:43 for <a href="http://llvm.org/">LLVM</a> by
+<a href="http://www.doxygen.org"><img src="doxygen.png" alt="Doxygen"
+align="middle" border="0"/>1.7.5.1</a><br>
+Copyright © 2003-2012 University of Illinois at Urbana-Champaign.
+All Rights Reserved.</p>
+
+<hr>
+<!--#include virtual="/attrib.incl" -->
+
+</body>
+</html>
Added: www-releases/trunk/3.2/docs/doxygen/html/ARMFrameLowering_8h__incl.map
URL: http://llvm.org/viewvc/llvm-project/www-releases/trunk/3.2/docs/doxygen/html/ARMFrameLowering_8h__incl.map?rev=170845&view=auto
==============================================================================
--- www-releases/trunk/3.2/docs/doxygen/html/ARMFrameLowering_8h__incl.map (added)
+++ www-releases/trunk/3.2/docs/doxygen/html/ARMFrameLowering_8h__incl.map Fri Dec 21 00:57:24 2012
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+ <li class="navelem"><a class="el" href="dir_b41d254693bea6e92988e5bb1ad97e02.html">llvm-3.2.src</a> </li>
+ <li class="navelem"><a class="el" href="dir_74e9364f374e99e3aeab4fae4e196292.html">lib</a> </li>
+ <li class="navelem"><a class="el" href="dir_8a55ec9894173378e0d08f27f306eeee.html">Target</a> </li>
+ <li class="navelem"><a class="el" href="dir_579de1806e7c3f5ec4b2837753e33796.html">ARM</a> </li>
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+<div class="title">ARMISelDAGToDAG.cpp</div> </div>
+</div>
+<div class="contents">
+<a href="ARMISelDAGToDAG_8cpp.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="comment">//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//</span>
+<a name="l00002"></a>00002 <span class="comment">//</span>
+<a name="l00003"></a>00003 <span class="comment">// The LLVM Compiler Infrastructure</span>
+<a name="l00004"></a>00004 <span class="comment">//</span>
+<a name="l00005"></a>00005 <span class="comment">// This file is distributed under the University of Illinois Open Source</span>
+<a name="l00006"></a>00006 <span class="comment">// License. See LICENSE.TXT for details.</span>
+<a name="l00007"></a>00007 <span class="comment">//</span>
+<a name="l00008"></a>00008 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00009"></a>00009 <span class="comment">//</span>
+<a name="l00010"></a>00010 <span class="comment">// This file defines an instruction selector for the ARM target.</span>
+<a name="l00011"></a>00011 <span class="comment">//</span>
+<a name="l00012"></a>00012 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00013"></a>00013
+<a name="l00014"></a><a class="code" href="ARMISelDAGToDAG_8cpp.html#ad78e062f62e0d6e453941fb4ca843e4d">00014</a> <span class="preprocessor">#define DEBUG_TYPE "arm-isel"</span>
+<a name="l00015"></a>00015 <span class="preprocessor"></span><span class="preprocessor">#include "<a class="code" href="ARM_8h.html">ARM.h</a>"</span>
+<a name="l00016"></a>00016 <span class="preprocessor">#include "<a class="code" href="ARMBaseInstrInfo_8h.html">ARMBaseInstrInfo.h</a>"</span>
+<a name="l00017"></a>00017 <span class="preprocessor">#include "<a class="code" href="ARMTargetMachine_8h.html">ARMTargetMachine.h</a>"</span>
+<a name="l00018"></a>00018 <span class="preprocessor">#include "<a class="code" href="ARMAddressingModes_8h.html">MCTargetDesc/ARMAddressingModes.h</a>"</span>
+<a name="l00019"></a>00019 <span class="preprocessor">#include "<a class="code" href="CallingConv_8h.html">llvm/CallingConv.h</a>"</span>
+<a name="l00020"></a>00020 <span class="preprocessor">#include "<a class="code" href="Constants_8h.html">llvm/Constants.h</a>"</span>
+<a name="l00021"></a>00021 <span class="preprocessor">#include "<a class="code" href="DerivedTypes_8h.html">llvm/DerivedTypes.h</a>"</span>
+<a name="l00022"></a>00022 <span class="preprocessor">#include "<a class="code" href="Function_8h.html">llvm/Function.h</a>"</span>
+<a name="l00023"></a>00023 <span class="preprocessor">#include "<a class="code" href="Intrinsics_8h.html">llvm/Intrinsics.h</a>"</span>
+<a name="l00024"></a>00024 <span class="preprocessor">#include "<a class="code" href="LLVMContext_8h.html">llvm/LLVMContext.h</a>"</span>
+<a name="l00025"></a>00025 <span class="preprocessor">#include "<a class="code" href="MachineFrameInfo_8h.html">llvm/CodeGen/MachineFrameInfo.h</a>"</span>
+<a name="l00026"></a>00026 <span class="preprocessor">#include "<a class="code" href="MachineFunction_8h.html">llvm/CodeGen/MachineFunction.h</a>"</span>
+<a name="l00027"></a>00027 <span class="preprocessor">#include "<a class="code" href="MachineInstrBuilder_8h.html">llvm/CodeGen/MachineInstrBuilder.h</a>"</span>
+<a name="l00028"></a>00028 <span class="preprocessor">#include "<a class="code" href="SelectionDAG_8h.html">llvm/CodeGen/SelectionDAG.h</a>"</span>
+<a name="l00029"></a>00029 <span class="preprocessor">#include "<a class="code" href="SelectionDAGISel_8h.html">llvm/CodeGen/SelectionDAGISel.h</a>"</span>
+<a name="l00030"></a>00030 <span class="preprocessor">#include "<a class="code" href="TargetLowering_8h.html">llvm/Target/TargetLowering.h</a>"</span>
+<a name="l00031"></a>00031 <span class="preprocessor">#include "<a class="code" href="TargetOptions_8h.html">llvm/Target/TargetOptions.h</a>"</span>
+<a name="l00032"></a>00032 <span class="preprocessor">#include "<a class="code" href="CommandLine_8h.html">llvm/Support/CommandLine.h</a>"</span>
+<a name="l00033"></a>00033 <span class="preprocessor">#include "<a class="code" href="Compiler_8h.html">llvm/Support/Compiler.h</a>"</span>
+<a name="l00034"></a>00034 <span class="preprocessor">#include "<a class="code" href="Debug_8h.html">llvm/Support/Debug.h</a>"</span>
+<a name="l00035"></a>00035 <span class="preprocessor">#include "<a class="code" href="ErrorHandling_8h.html">llvm/Support/ErrorHandling.h</a>"</span>
+<a name="l00036"></a>00036 <span class="preprocessor">#include "<a class="code" href="raw__ostream_8h.html">llvm/Support/raw_ostream.h</a>"</span>
+<a name="l00037"></a>00037
+<a name="l00038"></a>00038 <span class="keyword">using namespace </span>llvm;
+<a name="l00039"></a>00039
+<a name="l00040"></a>00040 <span class="keyword">static</span> <a class="code" href="classllvm_1_1cl_1_1opt.html">cl::opt<bool></a>
+<a name="l00041"></a>00041 <a class="code" href="ARMISelDAGToDAG_8cpp.html#a775cda86be29a0e990bbeb92f84f57bb">DisableShifterOp</a>(<span class="stringliteral">"disable-shifter-op"</span>, <a class="code" href="namespacellvm_1_1cl.html#a68075925a54790e71ca790e1d4f21a40a263ac008d8d31f13ce460395fc4cf7e6">cl::Hidden</a>,
+<a name="l00042"></a>00042 <a class="code" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>(<span class="stringliteral">"Disable isel of shifter-op"</span>),
+<a name="l00043"></a>00043 <a class="code" href="namespacellvm_1_1cl.html#a10a041239ae1870cfcc064bfaa79fb65">cl::init</a>(<span class="keyword">false</span>));
+<a name="l00044"></a>00044
+<a name="l00045"></a>00045 <span class="keyword">static</span> <a class="code" href="classllvm_1_1cl_1_1opt.html">cl::opt<bool></a>
+<a name="l00046"></a>00046 <a class="code" href="ARMISelDAGToDAG_8cpp.html#a21ae1406e4ef16188b77355281fb22ae">CheckVMLxHazard</a>(<span class="stringliteral">"check-vmlx-hazard"</span>, <a class="code" href="namespacellvm_1_1cl.html#a68075925a54790e71ca790e1d4f21a40a263ac008d8d31f13ce460395fc4cf7e6">cl::Hidden</a>,
+<a name="l00047"></a>00047 <a class="code" href="structllvm_1_1cl_1_1desc.html">cl::desc</a>(<span class="stringliteral">"Check fp vmla / vmls hazard at isel time"</span>),
+<a name="l00048"></a>00048 <a class="code" href="namespacellvm_1_1cl.html#a10a041239ae1870cfcc064bfaa79fb65">cl::init</a>(<span class="keyword">true</span>));
+<a name="l00049"></a>00049
+<a name="l00050"></a>00050 <span class="comment">//===--------------------------------------------------------------------===//</span><span class="comment"></span>
+<a name="l00051"></a>00051 <span class="comment">/// ARMDAGToDAGISel - ARM specific code to select ARM machine</span>
+<a name="l00052"></a>00052 <span class="comment">/// instructions for SelectionDAG operations.</span>
+<a name="l00053"></a>00053 <span class="comment">///</span>
+<a name="l00054"></a>00054 <span class="comment"></span><span class="keyword">namespace </span>{
+<a name="l00055"></a>00055
+<a name="l00056"></a><a class="code" href="ARMISelDAGToDAG_8cpp.html#a2ca19b37fd491c1953a3c531f84cb97e">00056</a> <span class="keyword">enum</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a2ca19b37fd491c1953a3c531f84cb97e">AddrMode2Type</a> {
+<a name="l00057"></a>00057 AM2_BASE, <span class="comment">// Simple AM2 (+-imm12)</span>
+<a name="l00058"></a>00058 AM2_SHOP <span class="comment">// Shifter-op AM2</span>
+<a name="l00059"></a>00059 };
+<a name="l00060"></a>00060
+<a name="l00061"></a>00061 <span class="keyword">class </span>ARMDAGToDAGISel : <span class="keyword">public</span> <a class="code" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a> {
+<a name="l00062"></a>00062 <a class="code" href="classllvm_1_1ARMBaseTargetMachine.html">ARMBaseTargetMachine</a> &TM;
+<a name="l00063"></a>00063 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a> *TII;
+<a name="l00064"></a>00064 <span class="comment"></span>
+<a name="l00065"></a>00065 <span class="comment"> /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can</span>
+<a name="l00066"></a>00066 <span class="comment"> /// make the right decision when generating code for different targets.</span>
+<a name="l00067"></a>00067 <span class="comment"></span> <span class="keyword">const</span> <a class="code" href="classllvm_1_1ARMSubtarget.html">ARMSubtarget</a> *Subtarget;
+<a name="l00068"></a>00068
+<a name="l00069"></a>00069 <span class="keyword">public</span>:
+<a name="l00070"></a>00070 <span class="keyword">explicit</span> ARMDAGToDAGISel(<a class="code" href="classllvm_1_1ARMBaseTargetMachine.html">ARMBaseTargetMachine</a> &tm,
+<a name="l00071"></a>00071 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a> OptLevel)
+<a name="l00072"></a>00072 : <a class="code" href="classllvm_1_1SelectionDAGISel.html">SelectionDAGISel</a>(tm, OptLevel), TM(tm),
+<a name="l00073"></a>00073 TII(static_cast<const <a class="code" href="classllvm_1_1ARMBaseInstrInfo.html">ARMBaseInstrInfo</a>*>(TM.getInstrInfo())),
+<a name="l00074"></a>00074 Subtarget(&TM.getSubtarget<<a class="code" href="classllvm_1_1ARMSubtarget.html">ARMSubtarget</a>>()) {
+<a name="l00075"></a>00075 }
+<a name="l00076"></a>00076
+<a name="l00077"></a>00077 <span class="keyword">virtual</span> <span class="keyword">const</span> <span class="keywordtype">char</span> *getPassName()<span class="keyword"> const </span>{
+<a name="l00078"></a>00078 <span class="keywordflow">return</span> <span class="stringliteral">"ARM Instruction Selection"</span>;
+<a name="l00079"></a>00079 }
+<a name="l00080"></a>00080 <span class="comment"></span>
+<a name="l00081"></a>00081 <span class="comment"> /// getI32Imm - Return a target constant of type i32 with the specified</span>
+<a name="l00082"></a>00082 <span class="comment"> /// value.</span>
+<a name="l00083"></a>00083 <span class="comment"></span> <span class="keyword">inline</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> getI32Imm(<span class="keywordtype">unsigned</span> Imm) {
+<a name="l00084"></a>00084 <span class="keywordflow">return</span> CurDAG->getTargetConstant(Imm, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00085"></a>00085 }
+<a name="l00086"></a>00086
+<a name="l00087"></a>00087 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="namespacellvm.html#af3ab12efdd6b4902d711e72b7a81f13b">Select</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00088"></a>00088
+<a name="l00089"></a>00089
+<a name="l00090"></a>00090 <span class="keywordtype">bool</span> hasNoVMLxHazardUse(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) <span class="keyword">const</span>;
+<a name="l00091"></a>00091 <span class="keywordtype">bool</span> isShifterOpProfitable(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Shift,
+<a name="l00092"></a>00092 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal, <span class="keywordtype">unsigned</span> ShAmt);
+<a name="l00093"></a>00093 <span class="keywordtype">bool</span> SelectRegShifterOperand(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11bad9577456b5bb7a03b7f42a710e122ab5">A</a>,
+<a name="l00094"></a>00094 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &B, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &<a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">C</a>,
+<a name="l00095"></a>00095 <span class="keywordtype">bool</span> CheckProfitability = <span class="keyword">true</span>);
+<a name="l00096"></a>00096 <span class="keywordtype">bool</span> SelectImmShifterOperand(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11bad9577456b5bb7a03b7f42a710e122ab5">A</a>,
+<a name="l00097"></a>00097 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &B, <span class="keywordtype">bool</span> CheckProfitability = <span class="keyword">true</span>);
+<a name="l00098"></a>00098 <span class="keywordtype">bool</span> SelectShiftRegShifterOperand(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11bad9577456b5bb7a03b7f42a710e122ab5">A</a>,
+<a name="l00099"></a>00099 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &B, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &<a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">C</a>) {
+<a name="l00100"></a>00100 <span class="comment">// Don't apply the profitability check</span>
+<a name="l00101"></a>00101 <span class="keywordflow">return</span> SelectRegShifterOperand(N, A, B, C, <span class="keyword">false</span>);
+<a name="l00102"></a>00102 }
+<a name="l00103"></a>00103 <span class="keywordtype">bool</span> SelectShiftImmShifterOperand(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11bad9577456b5bb7a03b7f42a710e122ab5">A</a>,
+<a name="l00104"></a>00104 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &B) {
+<a name="l00105"></a>00105 <span class="comment">// Don't apply the profitability check</span>
+<a name="l00106"></a>00106 <span class="keywordflow">return</span> SelectImmShifterOperand(N, A, B, <span class="keyword">false</span>);
+<a name="l00107"></a>00107 }
+<a name="l00108"></a>00108
+<a name="l00109"></a>00109 <span class="keywordtype">bool</span> SelectAddrModeImm12(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00110"></a>00110 <span class="keywordtype">bool</span> SelectLdStSOReg(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc);
+<a name="l00111"></a>00111
+<a name="l00112"></a>00112 <a class="code" href="ARMISelDAGToDAG_8cpp.html#a2ca19b37fd491c1953a3c531f84cb97e">AddrMode2Type</a> SelectAddrMode2Worker(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00113"></a>00113 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc);
+<a name="l00114"></a>00114 <span class="keywordtype">bool</span> SelectAddrMode2Base(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset,
+<a name="l00115"></a>00115 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00116"></a>00116 <span class="keywordflow">return</span> SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
+<a name="l00117"></a>00117 }
+<a name="l00118"></a>00118
+<a name="l00119"></a>00119 <span class="keywordtype">bool</span> SelectAddrMode2ShOp(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset,
+<a name="l00120"></a>00120 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00121"></a>00121 <span class="keywordflow">return</span> SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
+<a name="l00122"></a>00122 }
+<a name="l00123"></a>00123
+<a name="l00124"></a>00124 <span class="keywordtype">bool</span> SelectAddrMode2(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset,
+<a name="l00125"></a>00125 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00126"></a>00126 SelectAddrMode2Worker(N, Base, Offset, Opc);
+<a name="l00127"></a>00127 <span class="comment">// return SelectAddrMode2ShOp(N, Base, Offset, Opc);</span>
+<a name="l00128"></a>00128 <span class="comment">// This always matches one way or another.</span>
+<a name="l00129"></a>00129 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00130"></a>00130 }
+<a name="l00131"></a>00131
+<a name="l00132"></a>00132 <span class="keywordtype">bool</span> SelectAddrMode2OffsetReg(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00133"></a>00133 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc);
+<a name="l00134"></a>00134 <span class="keywordtype">bool</span> SelectAddrMode2OffsetImm(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00135"></a>00135 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc);
+<a name="l00136"></a>00136 <span class="keywordtype">bool</span> SelectAddrMode2OffsetImmPre(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00137"></a>00137 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc);
+<a name="l00138"></a>00138 <span class="keywordtype">bool</span> SelectAddrOffsetNone(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base);
+<a name="l00139"></a>00139 <span class="keywordtype">bool</span> SelectAddrMode3(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00140"></a>00140 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc);
+<a name="l00141"></a>00141 <span class="keywordtype">bool</span> SelectAddrMode3Offset(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00142"></a>00142 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc);
+<a name="l00143"></a>00143 <span class="keywordtype">bool</span> SelectAddrMode5(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00144"></a>00144 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset);
+<a name="l00145"></a>00145 <span class="keywordtype">bool</span> SelectAddrMode6(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Parent, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Addr,<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Align);
+<a name="l00146"></a>00146 <span class="keywordtype">bool</span> SelectAddrMode6Offset(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset);
+<a name="l00147"></a>00147
+<a name="l00148"></a>00148 <span class="keywordtype">bool</span> SelectAddrModePC(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Label);
+<a name="l00149"></a>00149
+<a name="l00150"></a>00150 <span class="comment">// Thumb Addressing Modes:</span>
+<a name="l00151"></a>00151 <span class="keywordtype">bool</span> SelectThumbAddrModeRR(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset);
+<a name="l00152"></a>00152 <span class="keywordtype">bool</span> SelectThumbAddrModeRI(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset,
+<a name="l00153"></a>00153 <span class="keywordtype">unsigned</span> Scale);
+<a name="l00154"></a>00154 <span class="keywordtype">bool</span> SelectThumbAddrModeRI5S1(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset);
+<a name="l00155"></a>00155 <span class="keywordtype">bool</span> SelectThumbAddrModeRI5S2(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset);
+<a name="l00156"></a>00156 <span class="keywordtype">bool</span> SelectThumbAddrModeRI5S4(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset);
+<a name="l00157"></a>00157 <span class="keywordtype">bool</span> SelectThumbAddrModeImm5S(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <span class="keywordtype">unsigned</span> Scale, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00158"></a>00158 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00159"></a>00159 <span class="keywordtype">bool</span> SelectThumbAddrModeImm5S1(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00160"></a>00160 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00161"></a>00161 <span class="keywordtype">bool</span> SelectThumbAddrModeImm5S2(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00162"></a>00162 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00163"></a>00163 <span class="keywordtype">bool</span> SelectThumbAddrModeImm5S4(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00164"></a>00164 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00165"></a>00165 <span class="keywordtype">bool</span> SelectThumbAddrModeSP(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00166"></a>00166
+<a name="l00167"></a>00167 <span class="comment">// Thumb 2 Addressing Modes:</span>
+<a name="l00168"></a>00168 <span class="keywordtype">bool</span> SelectT2ShifterOperandReg(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00169"></a>00169 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &BaseReg, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc);
+<a name="l00170"></a>00170 <span class="keywordtype">bool</span> SelectT2AddrModeImm12(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00171"></a>00171 <span class="keywordtype">bool</span> SelectT2AddrModeImm8(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00172"></a>00172 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00173"></a>00173 <span class="keywordtype">bool</span> SelectT2AddrModeImm8Offset(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00174"></a>00174 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm);
+<a name="l00175"></a>00175 <span class="keywordtype">bool</span> SelectT2AddrModeSoReg(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00176"></a>00176 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffReg, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &ShImm);
+<a name="l00177"></a>00177
+<a name="l00178"></a>00178 <span class="keyword">inline</span> <span class="keywordtype">bool</span> is_so_imm(<span class="keywordtype">unsigned</span> Imm)<span class="keyword"> const </span>{
+<a name="l00179"></a>00179 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARM__AM.html#ab18b193058b463093ad2a5701710bece">ARM_AM::getSOImmVal</a>(Imm) != -1;
+<a name="l00180"></a>00180 }
+<a name="l00181"></a>00181
+<a name="l00182"></a>00182 <span class="keyword">inline</span> <span class="keywordtype">bool</span> is_so_imm_not(<span class="keywordtype">unsigned</span> Imm)<span class="keyword"> const </span>{
+<a name="l00183"></a>00183 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARM__AM.html#ab18b193058b463093ad2a5701710bece">ARM_AM::getSOImmVal</a>(~Imm) != -1;
+<a name="l00184"></a>00184 }
+<a name="l00185"></a>00185
+<a name="l00186"></a>00186 <span class="keyword">inline</span> <span class="keywordtype">bool</span> is_t2_so_imm(<span class="keywordtype">unsigned</span> Imm)<span class="keyword"> const </span>{
+<a name="l00187"></a>00187 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARM__AM.html#a70b6f0b420385853a70713cb288c3292">ARM_AM::getT2SOImmVal</a>(Imm) != -1;
+<a name="l00188"></a>00188 }
+<a name="l00189"></a>00189
+<a name="l00190"></a>00190 <span class="keyword">inline</span> <span class="keywordtype">bool</span> is_t2_so_imm_not(<span class="keywordtype">unsigned</span> Imm)<span class="keyword"> const </span>{
+<a name="l00191"></a>00191 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARM__AM.html#a70b6f0b420385853a70713cb288c3292">ARM_AM::getT2SOImmVal</a>(~Imm) != -1;
+<a name="l00192"></a>00192 }
+<a name="l00193"></a>00193
+<a name="l00194"></a>00194 <span class="comment">// Include the pieces autogenerated from the target description.</span>
+<a name="l00195"></a>00195 <span class="preprocessor">#include "ARMGenDAGISel.inc"</span>
+<a name="l00196"></a>00196
+<a name="l00197"></a>00197 <span class="keyword">private</span>:<span class="comment"></span>
+<a name="l00198"></a>00198 <span class="comment"> /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for</span>
+<a name="l00199"></a>00199 <span class="comment"> /// ARM.</span>
+<a name="l00200"></a>00200 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectARMIndexedLoad(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00201"></a>00201 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectT2IndexedLoad(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00202"></a>00202 <span class="comment"></span>
+<a name="l00203"></a>00203 <span class="comment"> /// SelectVLD - Select NEON load intrinsics. NumVecs should be</span>
+<a name="l00204"></a>00204 <span class="comment"> /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for</span>
+<a name="l00205"></a>00205 <span class="comment"> /// loads of D registers and even subregs and odd subregs of Q registers.</span>
+<a name="l00206"></a>00206 <span class="comment"> /// For NumVecs <= 2, QOpcodes1 is not used.</span>
+<a name="l00207"></a>00207 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectVLD(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> isUpdating, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l00208"></a>00208 <span class="keyword">const</span> uint16_t *DOpcodes,
+<a name="l00209"></a>00209 <span class="keyword">const</span> uint16_t *QOpcodes0, <span class="keyword">const</span> uint16_t *QOpcodes1);
+<a name="l00210"></a>00210 <span class="comment"></span>
+<a name="l00211"></a>00211 <span class="comment"> /// SelectVST - Select NEON store intrinsics. NumVecs should</span>
+<a name="l00212"></a>00212 <span class="comment"> /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for</span>
+<a name="l00213"></a>00213 <span class="comment"> /// stores of D registers and even subregs and odd subregs of Q registers.</span>
+<a name="l00214"></a>00214 <span class="comment"> /// For NumVecs <= 2, QOpcodes1 is not used.</span>
+<a name="l00215"></a>00215 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectVST(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> isUpdating, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l00216"></a>00216 <span class="keyword">const</span> uint16_t *DOpcodes,
+<a name="l00217"></a>00217 <span class="keyword">const</span> uint16_t *QOpcodes0, <span class="keyword">const</span> uint16_t *QOpcodes1);
+<a name="l00218"></a>00218 <span class="comment"></span>
+<a name="l00219"></a>00219 <span class="comment"> /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should</span>
+<a name="l00220"></a>00220 <span class="comment"> /// be 2, 3 or 4. The opcode arrays specify the instructions used for</span>
+<a name="l00221"></a>00221 <span class="comment"> /// load/store of D registers and Q registers.</span>
+<a name="l00222"></a>00222 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectVLDSTLane(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> IsLoad,
+<a name="l00223"></a>00223 <span class="keywordtype">bool</span> isUpdating, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l00224"></a>00224 <span class="keyword">const</span> uint16_t *DOpcodes, <span class="keyword">const</span> uint16_t *QOpcodes);
+<a name="l00225"></a>00225 <span class="comment"></span>
+<a name="l00226"></a>00226 <span class="comment"> /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs</span>
+<a name="l00227"></a>00227 <span class="comment"> /// should be 2, 3 or 4. The opcode array specifies the instructions used</span>
+<a name="l00228"></a>00228 <span class="comment"> /// for loading D registers. (Q registers are not supported.)</span>
+<a name="l00229"></a>00229 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectVLDDup(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> isUpdating, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l00230"></a>00230 <span class="keyword">const</span> uint16_t *Opcodes);
+<a name="l00231"></a>00231 <span class="comment"></span>
+<a name="l00232"></a>00232 <span class="comment"> /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,</span>
+<a name="l00233"></a>00233 <span class="comment"> /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be</span>
+<a name="l00234"></a>00234 <span class="comment"> /// generated to force the table registers to be consecutive.</span>
+<a name="l00235"></a>00235 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectVTBL(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> IsExt, <span class="keywordtype">unsigned</span> NumVecs, <span class="keywordtype">unsigned</span> Opc);
+<a name="l00236"></a>00236 <span class="comment"></span>
+<a name="l00237"></a>00237 <span class="comment"> /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.</span>
+<a name="l00238"></a>00238 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectV6T2BitfieldExtractOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> isSigned);
+<a name="l00239"></a>00239 <span class="comment"></span>
+<a name="l00240"></a>00240 <span class="comment"> /// SelectCMOVOp - Select CMOV instructions for ARM.</span>
+<a name="l00241"></a>00241 <span class="comment"></span> <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectCMOVOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00242"></a>00242 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectT2CMOVShiftOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal,
+<a name="l00243"></a>00243 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR,
+<a name="l00244"></a>00244 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag);
+<a name="l00245"></a>00245 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectARMCMOVShiftOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal,
+<a name="l00246"></a>00246 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR,
+<a name="l00247"></a>00247 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag);
+<a name="l00248"></a>00248 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectT2CMOVImmOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal,
+<a name="l00249"></a>00249 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR,
+<a name="l00250"></a>00250 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag);
+<a name="l00251"></a>00251 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectARMCMOVImmOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal,
+<a name="l00252"></a>00252 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR,
+<a name="l00253"></a>00253 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag);
+<a name="l00254"></a>00254
+<a name="l00255"></a>00255 <span class="comment">// Select special operations if node forms integer ABS pattern</span>
+<a name="l00256"></a>00256 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectABSOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00257"></a>00257
+<a name="l00258"></a>00258 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectConcatVector(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N);
+<a name="l00259"></a>00259
+<a name="l00260"></a>00260 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *SelectAtomic64(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Node, <span class="keywordtype">unsigned</span> Opc);
+<a name="l00261"></a>00261 <span class="comment"></span>
+<a name="l00262"></a>00262 <span class="comment"> /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for</span>
+<a name="l00263"></a>00263 <span class="comment"> /// inline asm expressions.</span>
+<a name="l00264"></a>00264 <span class="comment"></span> <span class="keyword">virtual</span> <span class="keywordtype">bool</span> SelectInlineAsmMemoryOperand(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Op,
+<a name="l00265"></a>00265 <span class="keywordtype">char</span> ConstraintCode,
+<a name="l00266"></a>00266 std::vector<SDValue> &OutOps);
+<a name="l00267"></a>00267
+<a name="l00268"></a>00268 <span class="comment">// Form pairs of consecutive S, D, or Q registers.</span>
+<a name="l00269"></a>00269 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *PairSRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1);
+<a name="l00270"></a>00270 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *PairDRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1);
+<a name="l00271"></a>00271 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *PairQRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1);
+<a name="l00272"></a>00272
+<a name="l00273"></a>00273 <span class="comment">// Form sequences of 4 consecutive S, D, or Q registers.</span>
+<a name="l00274"></a>00274 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *QuadSRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a>, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3);
+<a name="l00275"></a>00275 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *QuadDRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a>, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3);
+<a name="l00276"></a>00276 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *QuadQRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a>, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3);
+<a name="l00277"></a>00277
+<a name="l00278"></a>00278 <span class="comment">// Get the alignment operand for a NEON VLD or VST instruction.</span>
+<a name="l00279"></a>00279 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> GetVLDSTAlign(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Align, <span class="keywordtype">unsigned</span> NumVecs, <span class="keywordtype">bool</span> is64BitVector);
+<a name="l00280"></a>00280 };
+<a name="l00281"></a>00281 }
+<a name="l00282"></a>00282 <span class="comment"></span>
+<a name="l00283"></a>00283 <span class="comment">/// isInt32Immediate - This method tests to see if the node is a 32-bit constant</span>
+<a name="l00284"></a>00284 <span class="comment">/// operand. If so Imm will receive the 32-bit value.</span>
+<a name="l00285"></a><a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">00285</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">unsigned</span> &Imm) {
+<a name="l00286"></a>00286 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a> && N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0) == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>) {
+<a name="l00287"></a>00287 Imm = cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l00288"></a>00288 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00289"></a>00289 }
+<a name="l00290"></a>00290 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00291"></a>00291 }
+<a name="l00292"></a>00292
+<a name="l00293"></a>00293 <span class="comment">// isInt32Immediate - This method tests to see if a constant operand.</span>
+<a name="l00294"></a>00294 <span class="comment">// If so Imm will receive the 32 bit value.</span>
+<a name="l00295"></a><a class="code" href="ARMISelDAGToDAG_8cpp.html#ace33718e35b67e1af759c3ec4c8f8443">00295</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <span class="keywordtype">unsigned</span> &Imm) {
+<a name="l00296"></a>00296 <span class="keywordflow">return</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm);
+<a name="l00297"></a>00297 }
+<a name="l00298"></a>00298
+<a name="l00299"></a>00299 <span class="comment">// isOpcWithIntImmediate - This method tests to see if the node is a specific</span>
+<a name="l00300"></a>00300 <span class="comment">// opcode and that it has a immediate integer right operand.</span>
+<a name="l00301"></a>00301 <span class="comment">// If so Imm will receive the 32 bit value.</span>
+<a name="l00302"></a><a class="code" href="ARMISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">00302</a> <span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">isOpcWithIntImmediate</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">unsigned</span> Opc, <span class="keywordtype">unsigned</span>& Imm) {
+<a name="l00303"></a>00303 <span class="keywordflow">return</span> N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() == Opc &&
+<a name="l00304"></a>00304 <a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Imm);
+<a name="l00305"></a>00305 }
+<a name="l00306"></a>00306 <span class="comment"></span>
+<a name="l00307"></a>00307 <span class="comment">/// \brief Check whether a particular node is a constant value representable as</span>
+<a name="l00308"></a>00308 <span class="comment">/// (N * Scale) where (N in [\p RangeMin, \p RangeMax).</span>
+<a name="l00309"></a>00309 <span class="comment">///</span>
+<a name="l00310"></a>00310 <span class="comment">/// \param ScaledConstant [out] - On success, the pre-scaled constant value.</span>
+<a name="l00311"></a><a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2">00311</a> <span class="comment"></span><span class="keyword">static</span> <span class="keywordtype">bool</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Node, <span class="keywordtype">int</span> Scale,
+<a name="l00312"></a>00312 <span class="keywordtype">int</span> RangeMin, <span class="keywordtype">int</span> RangeMax,
+<a name="l00313"></a>00313 <span class="keywordtype">int</span> &ScaledConstant) {
+<a name="l00314"></a>00314 assert(Scale > 0 && <span class="stringliteral">"Invalid scale!"</span>);
+<a name="l00315"></a>00315
+<a name="l00316"></a>00316 <span class="comment">// Check that this is a constant.</span>
+<a name="l00317"></a>00317 <span class="keyword">const</span> <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *<a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">C</a> = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(Node);
+<a name="l00318"></a>00318 <span class="keywordflow">if</span> (!C)
+<a name="l00319"></a>00319 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00320"></a>00320
+<a name="l00321"></a>00321 ScaledConstant = (int) C-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l00322"></a>00322 <span class="keywordflow">if</span> ((ScaledConstant % Scale) != 0)
+<a name="l00323"></a>00323 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00324"></a>00324
+<a name="l00325"></a>00325 ScaledConstant /= Scale;
+<a name="l00326"></a>00326 <span class="keywordflow">return</span> ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
+<a name="l00327"></a>00327 }
+<a name="l00328"></a>00328 <span class="comment"></span>
+<a name="l00329"></a>00329 <span class="comment">/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS</span>
+<a name="l00330"></a>00330 <span class="comment">/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at</span>
+<a name="l00331"></a>00331 <span class="comment">/// least on current ARM implementations) which should be avoidded.</span>
+<a name="l00332"></a>00332 <span class="comment"></span><span class="keywordtype">bool</span> ARMDAGToDAGISel::hasNoVMLxHazardUse(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N)<span class="keyword"> const </span>{
+<a name="l00333"></a>00333 <span class="keywordflow">if</span> (OptLevel == <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4a451bbac85aff02d070be3c17a6bef928">CodeGenOpt::None</a>)
+<a name="l00334"></a>00334 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00335"></a>00335
+<a name="l00336"></a>00336 <span class="keywordflow">if</span> (!<a class="code" href="ARMISelDAGToDAG_8cpp.html#a21ae1406e4ef16188b77355281fb22ae">CheckVMLxHazard</a>)
+<a name="l00337"></a>00337 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00338"></a>00338
+<a name="l00339"></a>00339 <span class="keywordflow">if</span> (!Subtarget->isCortexA8() && !Subtarget->isLikeA9() &&
+<a name="l00340"></a>00340 !Subtarget->isSwift())
+<a name="l00341"></a>00341 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00342"></a>00342
+<a name="l00343"></a>00343 <span class="keywordflow">if</span> (!N-><a class="code" href="classllvm_1_1SDNode.html#a52753947fce3a01b1c18dd4713c587e8">hasOneUse</a>())
+<a name="l00344"></a>00344 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00345"></a>00345
+<a name="l00346"></a>00346 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="classllvm_1_1Use.html">Use</a> = *N-><a class="code" href="classllvm_1_1SDNode.html#a8810bf428dcf84d48f39c8f5ba9a8c94">use_begin</a>();
+<a name="l00347"></a>00347 <span class="keywordflow">if</span> (Use-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a93bc27ca4d9e211c54b0d9efb660f080">ISD::CopyToReg</a>)
+<a name="l00348"></a>00348 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00349"></a>00349 <span class="keywordflow">if</span> (Use-><a class="code" href="classllvm_1_1SDNode.html#a7ef138746b04be6d07091b9ba49d74da">isMachineOpcode</a>()) {
+<a name="l00350"></a>00350 <span class="keyword">const</span> <a class="code" href="classllvm_1_1MCInstrDesc.html">MCInstrDesc</a> &MCID = TII->get(Use-><a class="code" href="classllvm_1_1SDNode.html#afe3745334feafa68985dee7caa1a254f">getMachineOpcode</a>());
+<a name="l00351"></a>00351 <span class="keywordflow">if</span> (MCID.<a class="code" href="classllvm_1_1MCInstrDesc.html#a7146d8440bad26a32a80ae4362298783">mayStore</a>())
+<a name="l00352"></a>00352 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00353"></a>00353 <span class="keywordtype">unsigned</span> Opcode = MCID.<a class="code" href="classllvm_1_1MCInstrDesc.html#a084170c688db518f99a4a7aed9cc84a0" title="getOpcode - Return the opcode number for this descriptor.">getOpcode</a>();
+<a name="l00354"></a>00354 <span class="keywordflow">if</span> (Opcode == ARM::VMOVRS || Opcode == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a7f93dc1b4123a3d49e2a544960758ef1">ARM::VMOVRRD</a>)
+<a name="l00355"></a>00355 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00356"></a>00356 <span class="comment">// vmlx feeding into another vmlx. We actually want to unfold</span>
+<a name="l00357"></a>00357 <span class="comment">// the use later in the MLxExpansion pass. e.g.</span>
+<a name="l00358"></a>00358 <span class="comment">// vmla</span>
+<a name="l00359"></a>00359 <span class="comment">// vmla (stall 8 cycles)</span>
+<a name="l00360"></a>00360 <span class="comment">//</span>
+<a name="l00361"></a>00361 <span class="comment">// vmul (5 cycles)</span>
+<a name="l00362"></a>00362 <span class="comment">// vadd (5 cycles)</span>
+<a name="l00363"></a>00363 <span class="comment">// vmla</span>
+<a name="l00364"></a>00364 <span class="comment">// This adds up to about 18 - 19 cycles.</span>
+<a name="l00365"></a>00365 <span class="comment">//</span>
+<a name="l00366"></a>00366 <span class="comment">// vmla</span>
+<a name="l00367"></a>00367 <span class="comment">// vmul (stall 4 cycles)</span>
+<a name="l00368"></a>00368 <span class="comment">// vadd adds up to about 14 cycles.</span>
+<a name="l00369"></a>00369 <span class="keywordflow">return</span> TII->isFpMLxInstruction(Opcode);
+<a name="l00370"></a>00370 }
+<a name="l00371"></a>00371
+<a name="l00372"></a>00372 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00373"></a>00373 }
+<a name="l00374"></a>00374
+<a name="l00375"></a>00375 <span class="keywordtype">bool</span> ARMDAGToDAGISel::isShifterOpProfitable(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Shift,
+<a name="l00376"></a>00376 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal,
+<a name="l00377"></a>00377 <span class="keywordtype">unsigned</span> ShAmt) {
+<a name="l00378"></a>00378 <span class="keywordflow">if</span> (!Subtarget->isLikeA9() && !Subtarget->isSwift())
+<a name="l00379"></a>00379 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00380"></a>00380 <span class="keywordflow">if</span> (Shift.<a class="code" href="classllvm_1_1SDValue.html#a97b0f24f3e52f030830fca6fbfcbd37d">hasOneUse</a>())
+<a name="l00381"></a>00381 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00382"></a>00382 <span class="comment">// R << 2 is free.</span>
+<a name="l00383"></a>00383 <span class="keywordflow">return</span> ShOpcVal == <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a> &&
+<a name="l00384"></a>00384 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
+<a name="l00385"></a>00385 }
+<a name="l00386"></a>00386
+<a name="l00387"></a>00387 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectImmShifterOperand(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00388"></a>00388 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &BaseReg,
+<a name="l00389"></a>00389 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc,
+<a name="l00390"></a>00390 <span class="keywordtype">bool</span> CheckProfitability) {
+<a name="l00391"></a>00391 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a775cda86be29a0e990bbeb92f84f57bb">DisableShifterOp</a>)
+<a name="l00392"></a>00392 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00393"></a>00393
+<a name="l00394"></a>00394 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l00395"></a>00395
+<a name="l00396"></a>00396 <span class="comment">// Don't match base register only case. That is matched to a separate</span>
+<a name="l00397"></a>00397 <span class="comment">// lower complexity pattern with explicit register operand.</span>
+<a name="l00398"></a>00398 <span class="keywordflow">if</span> (ShOpcVal == <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>) <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00399"></a>00399
+<a name="l00400"></a>00400 BaseReg = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00401"></a>00401 <span class="keywordtype">unsigned</span> ShImmVal = 0;
+<a name="l00402"></a>00402 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1));
+<a name="l00403"></a>00403 <span class="keywordflow">if</span> (!RHS) <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00404"></a>00404 ShImmVal = RHS-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>() & 31;
+<a name="l00405"></a>00405 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a257cdd16d16d0a9d9b358b5e5a472258">ARM_AM::getSORegOpc</a>(ShOpcVal, ShImmVal),
+<a name="l00406"></a>00406 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00407"></a>00407 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00408"></a>00408 }
+<a name="l00409"></a>00409
+<a name="l00410"></a>00410 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectRegShifterOperand(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00411"></a>00411 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &BaseReg,
+<a name="l00412"></a>00412 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &ShReg,
+<a name="l00413"></a>00413 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc,
+<a name="l00414"></a>00414 <span class="keywordtype">bool</span> CheckProfitability) {
+<a name="l00415"></a>00415 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a775cda86be29a0e990bbeb92f84f57bb">DisableShifterOp</a>)
+<a name="l00416"></a>00416 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00417"></a>00417
+<a name="l00418"></a>00418 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l00419"></a>00419
+<a name="l00420"></a>00420 <span class="comment">// Don't match base register only case. That is matched to a separate</span>
+<a name="l00421"></a>00421 <span class="comment">// lower complexity pattern with explicit register operand.</span>
+<a name="l00422"></a>00422 <span class="keywordflow">if</span> (ShOpcVal == <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>) <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00423"></a>00423
+<a name="l00424"></a>00424 BaseReg = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00425"></a>00425 <span class="keywordtype">unsigned</span> ShImmVal = 0;
+<a name="l00426"></a>00426 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1));
+<a name="l00427"></a>00427 <span class="keywordflow">if</span> (RHS) <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00428"></a>00428
+<a name="l00429"></a>00429 ShReg = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00430"></a>00430 <span class="keywordflow">if</span> (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
+<a name="l00431"></a>00431 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00432"></a>00432 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a257cdd16d16d0a9d9b358b5e5a472258">ARM_AM::getSORegOpc</a>(ShOpcVal, ShImmVal),
+<a name="l00433"></a>00433 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00434"></a>00434 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00435"></a>00435 }
+<a name="l00436"></a>00436
+<a name="l00437"></a>00437
+<a name="l00438"></a>00438 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrModeImm12(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00439"></a>00439 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00440"></a>00440 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm) {
+<a name="l00441"></a>00441 <span class="comment">// Match simple R + imm12 operands.</span>
+<a name="l00442"></a>00442
+<a name="l00443"></a>00443 <span class="comment">// Base only.</span>
+<a name="l00444"></a>00444 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> && N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> &&
+<a name="l00445"></a>00445 !CurDAG->isBaseWithConstantOffset(N)) {
+<a name="l00446"></a>00446 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l00447"></a>00447 <span class="comment">// Match frame index.</span>
+<a name="l00448"></a>00448 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(N)->getIndex();
+<a name="l00449"></a>00449 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l00450"></a>00450 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00451"></a>00451 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00452"></a>00452 }
+<a name="l00453"></a>00453
+<a name="l00454"></a>00454 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a029f48a0b5e0d471de85baca7745d1a0">ARMISD::Wrapper</a> &&
+<a name="l00455"></a>00455 !(Subtarget->useMovt() &&
+<a name="l00456"></a>00456 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a>)) {
+<a name="l00457"></a>00457 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00458"></a>00458 } <span class="keywordflow">else</span>
+<a name="l00459"></a>00459 Base = N;
+<a name="l00460"></a>00460 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00461"></a>00461 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00462"></a>00462 }
+<a name="l00463"></a>00463
+<a name="l00464"></a>00464 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l00465"></a>00465 <span class="keywordtype">int</span> RHSC = (int)RHS-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l00466"></a>00466 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>)
+<a name="l00467"></a>00467 RHSC = -RHSC;
+<a name="l00468"></a>00468
+<a name="l00469"></a>00469 <span class="keywordflow">if</span> (RHSC >= 0 && RHSC < 0x1000) { <span class="comment">// 12 bits (unsigned)</span>
+<a name="l00470"></a>00470 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00471"></a>00471 <span class="keywordflow">if</span> (Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l00472"></a>00472 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(Base)->getIndex();
+<a name="l00473"></a>00473 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l00474"></a>00474 }
+<a name="l00475"></a>00475 OffImm = CurDAG->getTargetConstant(RHSC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00476"></a>00476 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00477"></a>00477 }
+<a name="l00478"></a>00478 }
+<a name="l00479"></a>00479
+<a name="l00480"></a>00480 <span class="comment">// Base only.</span>
+<a name="l00481"></a>00481 Base = N;
+<a name="l00482"></a>00482 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00483"></a>00483 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00484"></a>00484 }
+<a name="l00485"></a>00485
+<a name="l00486"></a>00486
+<a name="l00487"></a>00487
+<a name="l00488"></a>00488 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectLdStSOReg(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset,
+<a name="l00489"></a>00489 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00490"></a>00490 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a> &&
+<a name="l00491"></a>00491 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.<a class="code" href="classllvm_1_1SDValue.html#a97b0f24f3e52f030830fca6fbfcbd37d">hasOneUse</a>())) {
+<a name="l00492"></a>00492 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l00493"></a>00493 <span class="comment">// X * [3,5,9] -> X + X * [2,4,8] etc.</span>
+<a name="l00494"></a>00494 <span class="keywordtype">int</span> RHSC = (int)RHS-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l00495"></a>00495 <span class="keywordflow">if</span> (RHSC & 1) {
+<a name="l00496"></a>00496 RHSC = RHSC & ~1;
+<a name="l00497"></a>00497 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>;
+<a name="l00498"></a>00498 <span class="keywordflow">if</span> (RHSC < 0) {
+<a name="l00499"></a>00499 AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00500"></a>00500 RHSC = - RHSC;
+<a name="l00501"></a>00501 }
+<a name="l00502"></a>00502 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#af4d1a918800291e75b01ce1447be0e83">isPowerOf2_32</a>(RHSC)) {
+<a name="l00503"></a>00503 <span class="keywordtype">unsigned</span> ShAmt = <a class="code" href="namespacellvm.html#a646986783f35e0fef8988f0f28d2589f">Log2_32</a>(RHSC);
+<a name="l00504"></a>00504 Base = Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00505"></a>00505 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(AddSub, ShAmt,
+<a name="l00506"></a>00506 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a>),
+<a name="l00507"></a>00507 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00508"></a>00508 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00509"></a>00509 }
+<a name="l00510"></a>00510 }
+<a name="l00511"></a>00511 }
+<a name="l00512"></a>00512 }
+<a name="l00513"></a>00513
+<a name="l00514"></a>00514 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> && N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> &&
+<a name="l00515"></a>00515 <span class="comment">// ISD::OR that is equivalent to an ISD::ADD.</span>
+<a name="l00516"></a>00516 !CurDAG->isBaseWithConstantOffset(N))
+<a name="l00517"></a>00517 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00518"></a>00518
+<a name="l00519"></a>00519 <span class="comment">// Leave simple R +/- imm12 operands for LDRi12</span>
+<a name="l00520"></a>00520 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> || N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a>) {
+<a name="l00521"></a>00521 <span class="keywordtype">int</span> RHSC;
+<a name="l00522"></a>00522 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), <span class="comment">/*Scale=*/</span>1,
+<a name="l00523"></a>00523 -0x1000+1, 0x1000, RHSC)) <span class="comment">// 12 bits.</span>
+<a name="l00524"></a>00524 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00525"></a>00525 }
+<a name="l00526"></a>00526
+<a name="l00527"></a>00527 <span class="comment">// Otherwise this is R +/- [possibly shifted] R.</span>
+<a name="l00528"></a>00528 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> ? <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>:<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>;
+<a name="l00529"></a>00529 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal =
+<a name="l00530"></a>00530 <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l00531"></a>00531 <span class="keywordtype">unsigned</span> ShAmt = 0;
+<a name="l00532"></a>00532
+<a name="l00533"></a>00533 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00534"></a>00534 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00535"></a>00535
+<a name="l00536"></a>00536 <span class="keywordflow">if</span> (ShOpcVal != <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>) {
+<a name="l00537"></a>00537 <span class="comment">// Check to see if the RHS of the shift is a constant, if not, we can't fold</span>
+<a name="l00538"></a>00538 <span class="comment">// it.</span>
+<a name="l00539"></a>00539 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *Sh =
+<a name="l00540"></a>00540 dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l00541"></a>00541 ShAmt = Sh->getZExtValue();
+<a name="l00542"></a>00542 <span class="keywordflow">if</span> (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
+<a name="l00543"></a>00543 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00544"></a>00544 <span class="keywordflow">else</span> {
+<a name="l00545"></a>00545 ShAmt = 0;
+<a name="l00546"></a>00546 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00547"></a>00547 }
+<a name="l00548"></a>00548 } <span class="keywordflow">else</span> {
+<a name="l00549"></a>00549 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00550"></a>00550 }
+<a name="l00551"></a>00551 }
+<a name="l00552"></a>00552
+<a name="l00553"></a>00553 <span class="comment">// Try matching (R shl C) + (R).</span>
+<a name="l00554"></a>00554 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> && ShOpcVal == <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a> &&
+<a name="l00555"></a>00555 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
+<a name="l00556"></a>00556 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a97b0f24f3e52f030830fca6fbfcbd37d">hasOneUse</a>())) {
+<a name="l00557"></a>00557 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l00558"></a>00558 <span class="keywordflow">if</span> (ShOpcVal != <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>) {
+<a name="l00559"></a>00559 <span class="comment">// Check to see if the RHS of the shift is a constant, if not, we can't</span>
+<a name="l00560"></a>00560 <span class="comment">// fold it.</span>
+<a name="l00561"></a>00561 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *Sh =
+<a name="l00562"></a>00562 dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l00563"></a>00563 ShAmt = Sh->getZExtValue();
+<a name="l00564"></a>00564 <span class="keywordflow">if</span> (isShifterOpProfitable(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), ShOpcVal, ShAmt)) {
+<a name="l00565"></a>00565 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00566"></a>00566 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00567"></a>00567 } <span class="keywordflow">else</span> {
+<a name="l00568"></a>00568 ShAmt = 0;
+<a name="l00569"></a>00569 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00570"></a>00570 }
+<a name="l00571"></a>00571 } <span class="keywordflow">else</span> {
+<a name="l00572"></a>00572 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00573"></a>00573 }
+<a name="l00574"></a>00574 }
+<a name="l00575"></a>00575 }
+<a name="l00576"></a>00576
+<a name="l00577"></a>00577 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(AddSub, ShAmt, ShOpcVal),
+<a name="l00578"></a>00578 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00579"></a>00579 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00580"></a>00580 }
+<a name="l00581"></a>00581
+<a name="l00582"></a>00582
+<a name="l00583"></a>00583 <span class="comment">//-----</span>
+<a name="l00584"></a>00584
+<a name="l00585"></a>00585 <a class="code" href="ARMISelDAGToDAG_8cpp.html#a2ca19b37fd491c1953a3c531f84cb97e">AddrMode2Type</a> ARMDAGToDAGISel::SelectAddrMode2Worker(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00586"></a>00586 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00587"></a>00587 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset,
+<a name="l00588"></a>00588 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00589"></a>00589 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a> &&
+<a name="l00590"></a>00590 (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.<a class="code" href="classllvm_1_1SDValue.html#a97b0f24f3e52f030830fca6fbfcbd37d">hasOneUse</a>())) {
+<a name="l00591"></a>00591 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l00592"></a>00592 <span class="comment">// X * [3,5,9] -> X + X * [2,4,8] etc.</span>
+<a name="l00593"></a>00593 <span class="keywordtype">int</span> RHSC = (int)RHS-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l00594"></a>00594 <span class="keywordflow">if</span> (RHSC & 1) {
+<a name="l00595"></a>00595 RHSC = RHSC & ~1;
+<a name="l00596"></a>00596 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>;
+<a name="l00597"></a>00597 <span class="keywordflow">if</span> (RHSC < 0) {
+<a name="l00598"></a>00598 AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00599"></a>00599 RHSC = - RHSC;
+<a name="l00600"></a>00600 }
+<a name="l00601"></a>00601 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#af4d1a918800291e75b01ce1447be0e83">isPowerOf2_32</a>(RHSC)) {
+<a name="l00602"></a>00602 <span class="keywordtype">unsigned</span> ShAmt = <a class="code" href="namespacellvm.html#a646986783f35e0fef8988f0f28d2589f">Log2_32</a>(RHSC);
+<a name="l00603"></a>00603 Base = Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00604"></a>00604 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(AddSub, ShAmt,
+<a name="l00605"></a>00605 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a>),
+<a name="l00606"></a>00606 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00607"></a>00607 <span class="keywordflow">return</span> AM2_SHOP;
+<a name="l00608"></a>00608 }
+<a name="l00609"></a>00609 }
+<a name="l00610"></a>00610 }
+<a name="l00611"></a>00611 }
+<a name="l00612"></a>00612
+<a name="l00613"></a>00613 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> && N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> &&
+<a name="l00614"></a>00614 <span class="comment">// ISD::OR that is equivalent to an ADD.</span>
+<a name="l00615"></a>00615 !CurDAG->isBaseWithConstantOffset(N)) {
+<a name="l00616"></a>00616 Base = N;
+<a name="l00617"></a>00617 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l00618"></a>00618 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(N)->getIndex();
+<a name="l00619"></a>00619 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l00620"></a>00620 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a029f48a0b5e0d471de85baca7745d1a0">ARMISD::Wrapper</a> &&
+<a name="l00621"></a>00621 !(Subtarget->useMovt() &&
+<a name="l00622"></a>00622 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a>)) {
+<a name="l00623"></a>00623 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00624"></a>00624 }
+<a name="l00625"></a>00625 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00626"></a>00626 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>, 0,
+<a name="l00627"></a>00627 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>),
+<a name="l00628"></a>00628 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00629"></a>00629 <span class="keywordflow">return</span> AM2_BASE;
+<a name="l00630"></a>00630 }
+<a name="l00631"></a>00631
+<a name="l00632"></a>00632 <span class="comment">// Match simple R +/- imm12 operands.</span>
+<a name="l00633"></a>00633 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>) {
+<a name="l00634"></a>00634 <span class="keywordtype">int</span> RHSC;
+<a name="l00635"></a>00635 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), <span class="comment">/*Scale=*/</span>1,
+<a name="l00636"></a>00636 -0x1000+1, 0x1000, RHSC)) { <span class="comment">// 12 bits.</span>
+<a name="l00637"></a>00637 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00638"></a>00638 <span class="keywordflow">if</span> (Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l00639"></a>00639 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(Base)->getIndex();
+<a name="l00640"></a>00640 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l00641"></a>00641 }
+<a name="l00642"></a>00642 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00643"></a>00643
+<a name="l00644"></a>00644 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>;
+<a name="l00645"></a>00645 <span class="keywordflow">if</span> (RHSC < 0) {
+<a name="l00646"></a>00646 AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00647"></a>00647 RHSC = - RHSC;
+<a name="l00648"></a>00648 }
+<a name="l00649"></a>00649 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(AddSub, RHSC,
+<a name="l00650"></a>00650 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>),
+<a name="l00651"></a>00651 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00652"></a>00652 <span class="keywordflow">return</span> AM2_BASE;
+<a name="l00653"></a>00653 }
+<a name="l00654"></a>00654 }
+<a name="l00655"></a>00655
+<a name="l00656"></a>00656 <span class="keywordflow">if</span> ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.<a class="code" href="classllvm_1_1SDValue.html#a97b0f24f3e52f030830fca6fbfcbd37d">hasOneUse</a>()) {
+<a name="l00657"></a>00657 <span class="comment">// Compute R +/- (R << N) and reuse it.</span>
+<a name="l00658"></a>00658 Base = N;
+<a name="l00659"></a>00659 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00660"></a>00660 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>, 0,
+<a name="l00661"></a>00661 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>),
+<a name="l00662"></a>00662 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00663"></a>00663 <span class="keywordflow">return</span> AM2_BASE;
+<a name="l00664"></a>00664 }
+<a name="l00665"></a>00665
+<a name="l00666"></a>00666 <span class="comment">// Otherwise this is R +/- [possibly shifted] R.</span>
+<a name="l00667"></a>00667 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> ? <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>:<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00668"></a>00668 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal =
+<a name="l00669"></a>00669 <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l00670"></a>00670 <span class="keywordtype">unsigned</span> ShAmt = 0;
+<a name="l00671"></a>00671
+<a name="l00672"></a>00672 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00673"></a>00673 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00674"></a>00674
+<a name="l00675"></a>00675 <span class="keywordflow">if</span> (ShOpcVal != <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>) {
+<a name="l00676"></a>00676 <span class="comment">// Check to see if the RHS of the shift is a constant, if not, we can't fold</span>
+<a name="l00677"></a>00677 <span class="comment">// it.</span>
+<a name="l00678"></a>00678 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *Sh =
+<a name="l00679"></a>00679 dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l00680"></a>00680 ShAmt = Sh->getZExtValue();
+<a name="l00681"></a>00681 <span class="keywordflow">if</span> (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
+<a name="l00682"></a>00682 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00683"></a>00683 <span class="keywordflow">else</span> {
+<a name="l00684"></a>00684 ShAmt = 0;
+<a name="l00685"></a>00685 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00686"></a>00686 }
+<a name="l00687"></a>00687 } <span class="keywordflow">else</span> {
+<a name="l00688"></a>00688 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00689"></a>00689 }
+<a name="l00690"></a>00690 }
+<a name="l00691"></a>00691
+<a name="l00692"></a>00692 <span class="comment">// Try matching (R shl C) + (R).</span>
+<a name="l00693"></a>00693 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> && ShOpcVal == <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a> &&
+<a name="l00694"></a>00694 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
+<a name="l00695"></a>00695 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a97b0f24f3e52f030830fca6fbfcbd37d">hasOneUse</a>())) {
+<a name="l00696"></a>00696 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l00697"></a>00697 <span class="keywordflow">if</span> (ShOpcVal != <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>) {
+<a name="l00698"></a>00698 <span class="comment">// Check to see if the RHS of the shift is a constant, if not, we can't</span>
+<a name="l00699"></a>00699 <span class="comment">// fold it.</span>
+<a name="l00700"></a>00700 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *Sh =
+<a name="l00701"></a>00701 dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l00702"></a>00702 ShAmt = Sh->getZExtValue();
+<a name="l00703"></a>00703 <span class="keywordflow">if</span> (isShifterOpProfitable(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), ShOpcVal, ShAmt)) {
+<a name="l00704"></a>00704 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00705"></a>00705 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00706"></a>00706 } <span class="keywordflow">else</span> {
+<a name="l00707"></a>00707 ShAmt = 0;
+<a name="l00708"></a>00708 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00709"></a>00709 }
+<a name="l00710"></a>00710 } <span class="keywordflow">else</span> {
+<a name="l00711"></a>00711 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00712"></a>00712 }
+<a name="l00713"></a>00713 }
+<a name="l00714"></a>00714 }
+<a name="l00715"></a>00715
+<a name="l00716"></a>00716 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(AddSub, ShAmt, ShOpcVal),
+<a name="l00717"></a>00717 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00718"></a>00718 <span class="keywordflow">return</span> AM2_SHOP;
+<a name="l00719"></a>00719 }
+<a name="l00720"></a>00720
+<a name="l00721"></a>00721 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrMode2OffsetReg(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00722"></a>00722 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00723"></a>00723 <span class="keywordtype">unsigned</span> Opcode = Op-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>();
+<a name="l00724"></a>00724 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> AM = (Opcode == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a>)
+<a name="l00725"></a>00725 ? cast<LoadSDNode>(Op)->getAddressingMode()
+<a name="l00726"></a>00726 : cast<StoreSDNode>(Op)->getAddressingMode();
+<a name="l00727"></a>00727 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a> || AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31a866c29237765ff291c9503abbdca60e1">ISD::POST_INC</a>)
+<a name="l00728"></a>00728 ? <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a> : <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00729"></a>00729 <span class="keywordtype">int</span> Val;
+<a name="l00730"></a>00730 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N, <span class="comment">/*Scale=*/</span>1, 0, 0x1000, Val))
+<a name="l00731"></a>00731 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00732"></a>00732
+<a name="l00733"></a>00733 Offset = N;
+<a name="l00734"></a>00734 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l00735"></a>00735 <span class="keywordtype">unsigned</span> ShAmt = 0;
+<a name="l00736"></a>00736 <span class="keywordflow">if</span> (ShOpcVal != <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>) {
+<a name="l00737"></a>00737 <span class="comment">// Check to see if the RHS of the shift is a constant, if not, we can't fold</span>
+<a name="l00738"></a>00738 <span class="comment">// it.</span>
+<a name="l00739"></a>00739 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *Sh = dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l00740"></a>00740 ShAmt = Sh->getZExtValue();
+<a name="l00741"></a>00741 <span class="keywordflow">if</span> (isShifterOpProfitable(N, ShOpcVal, ShAmt))
+<a name="l00742"></a>00742 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00743"></a>00743 <span class="keywordflow">else</span> {
+<a name="l00744"></a>00744 ShAmt = 0;
+<a name="l00745"></a>00745 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00746"></a>00746 }
+<a name="l00747"></a>00747 } <span class="keywordflow">else</span> {
+<a name="l00748"></a>00748 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l00749"></a>00749 }
+<a name="l00750"></a>00750 }
+<a name="l00751"></a>00751
+<a name="l00752"></a>00752 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(AddSub, ShAmt, ShOpcVal),
+<a name="l00753"></a>00753 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00754"></a>00754 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00755"></a>00755 }
+<a name="l00756"></a>00756
+<a name="l00757"></a>00757 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00758"></a>00758 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00759"></a>00759 <span class="keywordtype">unsigned</span> Opcode = Op-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>();
+<a name="l00760"></a>00760 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> AM = (Opcode == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a>)
+<a name="l00761"></a>00761 ? cast<LoadSDNode>(Op)->getAddressingMode()
+<a name="l00762"></a>00762 : cast<StoreSDNode>(Op)->getAddressingMode();
+<a name="l00763"></a>00763 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a> || AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31a866c29237765ff291c9503abbdca60e1">ISD::POST_INC</a>)
+<a name="l00764"></a>00764 ? <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a> : <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00765"></a>00765 <span class="keywordtype">int</span> Val;
+<a name="l00766"></a>00766 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N, <span class="comment">/*Scale=*/</span>1, 0, 0x1000, Val)) { <span class="comment">// 12 bits.</span>
+<a name="l00767"></a>00767 <span class="keywordflow">if</span> (AddSub == <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>) Val *= -1;
+<a name="l00768"></a>00768 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00769"></a>00769 Opc = CurDAG->getTargetConstant(Val, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00770"></a>00770 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00771"></a>00771 }
+<a name="l00772"></a>00772
+<a name="l00773"></a>00773 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00774"></a>00774 }
+<a name="l00775"></a>00775
+<a name="l00776"></a>00776
+<a name="l00777"></a>00777 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrMode2OffsetImm(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00778"></a>00778 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00779"></a>00779 <span class="keywordtype">unsigned</span> Opcode = Op-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>();
+<a name="l00780"></a>00780 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> AM = (Opcode == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a>)
+<a name="l00781"></a>00781 ? cast<LoadSDNode>(Op)->getAddressingMode()
+<a name="l00782"></a>00782 : cast<StoreSDNode>(Op)->getAddressingMode();
+<a name="l00783"></a>00783 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a> || AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31a866c29237765ff291c9503abbdca60e1">ISD::POST_INC</a>)
+<a name="l00784"></a>00784 ? <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a> : <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00785"></a>00785 <span class="keywordtype">int</span> Val;
+<a name="l00786"></a>00786 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N, <span class="comment">/*Scale=*/</span>1, 0, 0x1000, Val)) { <span class="comment">// 12 bits.</span>
+<a name="l00787"></a>00787 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00788"></a>00788 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a97e4756295ed8f0cfc534cac7fa60beb">ARM_AM::getAM2Opc</a>(AddSub, Val,
+<a name="l00789"></a>00789 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>),
+<a name="l00790"></a>00790 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00791"></a>00791 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00792"></a>00792 }
+<a name="l00793"></a>00793
+<a name="l00794"></a>00794 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00795"></a>00795 }
+<a name="l00796"></a>00796
+<a name="l00797"></a>00797 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrOffsetNone(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base) {
+<a name="l00798"></a>00798 Base = N;
+<a name="l00799"></a>00799 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00800"></a>00800 }
+<a name="l00801"></a>00801
+<a name="l00802"></a>00802 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrMode3(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00803"></a>00803 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset,
+<a name="l00804"></a>00804 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00805"></a>00805 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>) {
+<a name="l00806"></a>00806 <span class="comment">// X - C is canonicalize to X + -C, no need to handle it here.</span>
+<a name="l00807"></a>00807 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00808"></a>00808 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00809"></a>00809 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a2b9258fcda1e898fc68533884715bdc6" title="getAM3Opc - This function encodes the addrmode3 opc field.">ARM_AM::getAM3Opc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>, 0),<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00810"></a>00810 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00811"></a>00811 }
+<a name="l00812"></a>00812
+<a name="l00813"></a>00813 <span class="keywordflow">if</span> (!CurDAG->isBaseWithConstantOffset(N)) {
+<a name="l00814"></a>00814 Base = N;
+<a name="l00815"></a>00815 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l00816"></a>00816 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(N)->getIndex();
+<a name="l00817"></a>00817 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l00818"></a>00818 }
+<a name="l00819"></a>00819 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00820"></a>00820 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a2b9258fcda1e898fc68533884715bdc6" title="getAM3Opc - This function encodes the addrmode3 opc field.">ARM_AM::getAM3Opc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>, 0),<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00821"></a>00821 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00822"></a>00822 }
+<a name="l00823"></a>00823
+<a name="l00824"></a>00824 <span class="comment">// If the RHS is +/- imm8, fold into addr mode.</span>
+<a name="l00825"></a>00825 <span class="keywordtype">int</span> RHSC;
+<a name="l00826"></a>00826 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), <span class="comment">/*Scale=*/</span>1,
+<a name="l00827"></a>00827 -256 + 1, 256, RHSC)) { <span class="comment">// 8 bits.</span>
+<a name="l00828"></a>00828 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00829"></a>00829 <span class="keywordflow">if</span> (Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l00830"></a>00830 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(Base)->getIndex();
+<a name="l00831"></a>00831 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l00832"></a>00832 }
+<a name="l00833"></a>00833 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00834"></a>00834
+<a name="l00835"></a>00835 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>;
+<a name="l00836"></a>00836 <span class="keywordflow">if</span> (RHSC < 0) {
+<a name="l00837"></a>00837 AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00838"></a>00838 RHSC = -RHSC;
+<a name="l00839"></a>00839 }
+<a name="l00840"></a>00840 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a2b9258fcda1e898fc68533884715bdc6" title="getAM3Opc - This function encodes the addrmode3 opc field.">ARM_AM::getAM3Opc</a>(AddSub, RHSC),<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00841"></a>00841 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00842"></a>00842 }
+<a name="l00843"></a>00843
+<a name="l00844"></a>00844 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00845"></a>00845 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00846"></a>00846 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a2b9258fcda1e898fc68533884715bdc6" title="getAM3Opc - This function encodes the addrmode3 opc field.">ARM_AM::getAM3Opc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>, 0), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00847"></a>00847 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00848"></a>00848 }
+<a name="l00849"></a>00849
+<a name="l00850"></a>00850 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrMode3Offset(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00851"></a>00851 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l00852"></a>00852 <span class="keywordtype">unsigned</span> Opcode = Op-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>();
+<a name="l00853"></a>00853 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> AM = (Opcode == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a>)
+<a name="l00854"></a>00854 ? cast<LoadSDNode>(Op)->getAddressingMode()
+<a name="l00855"></a>00855 : cast<StoreSDNode>(Op)->getAddressingMode();
+<a name="l00856"></a>00856 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a> || AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31a866c29237765ff291c9503abbdca60e1">ISD::POST_INC</a>)
+<a name="l00857"></a>00857 ? <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a> : <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00858"></a>00858 <span class="keywordtype">int</span> Val;
+<a name="l00859"></a>00859 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N, <span class="comment">/*Scale=*/</span>1, 0, 256, Val)) { <span class="comment">// 12 bits.</span>
+<a name="l00860"></a>00860 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00861"></a>00861 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a2b9258fcda1e898fc68533884715bdc6" title="getAM3Opc - This function encodes the addrmode3 opc field.">ARM_AM::getAM3Opc</a>(AddSub, Val), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00862"></a>00862 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00863"></a>00863 }
+<a name="l00864"></a>00864
+<a name="l00865"></a>00865 Offset = N;
+<a name="l00866"></a>00866 Opc = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a2b9258fcda1e898fc68533884715bdc6" title="getAM3Opc - This function encodes the addrmode3 opc field.">ARM_AM::getAM3Opc</a>(AddSub, 0), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00867"></a>00867 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00868"></a>00868 }
+<a name="l00869"></a>00869
+<a name="l00870"></a>00870 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrMode5(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00871"></a>00871 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset) {
+<a name="l00872"></a>00872 <span class="keywordflow">if</span> (!CurDAG->isBaseWithConstantOffset(N)) {
+<a name="l00873"></a>00873 Base = N;
+<a name="l00874"></a>00874 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l00875"></a>00875 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(N)->getIndex();
+<a name="l00876"></a>00876 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l00877"></a>00877 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a029f48a0b5e0d471de85baca7745d1a0">ARMISD::Wrapper</a> &&
+<a name="l00878"></a>00878 !(Subtarget->useMovt() &&
+<a name="l00879"></a>00879 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a>)) {
+<a name="l00880"></a>00880 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00881"></a>00881 }
+<a name="l00882"></a>00882 Offset = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#aeaddd028e428140b446fac6bf267f0cf" title="getAM5Opc - This function encodes the addrmode5 opc field.">ARM_AM::getAM5Opc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>, 0),
+<a name="l00883"></a>00883 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00884"></a>00884 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00885"></a>00885 }
+<a name="l00886"></a>00886
+<a name="l00887"></a>00887 <span class="comment">// If the RHS is +/- imm8, fold into addr mode.</span>
+<a name="l00888"></a>00888 <span class="keywordtype">int</span> RHSC;
+<a name="l00889"></a>00889 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), <span class="comment">/*Scale=*/</span>4,
+<a name="l00890"></a>00890 -256 + 1, 256, RHSC)) {
+<a name="l00891"></a>00891 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00892"></a>00892 <span class="keywordflow">if</span> (Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l00893"></a>00893 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(Base)->getIndex();
+<a name="l00894"></a>00894 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l00895"></a>00895 }
+<a name="l00896"></a>00896
+<a name="l00897"></a>00897 <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cd">ARM_AM::AddrOpc</a> AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>;
+<a name="l00898"></a>00898 <span class="keywordflow">if</span> (RHSC < 0) {
+<a name="l00899"></a>00899 AddSub = <a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cda41a13f3ce88ed84e63003e32b18c1235">ARM_AM::sub</a>;
+<a name="l00900"></a>00900 RHSC = -RHSC;
+<a name="l00901"></a>00901 }
+<a name="l00902"></a>00902 Offset = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#aeaddd028e428140b446fac6bf267f0cf" title="getAM5Opc - This function encodes the addrmode5 opc field.">ARM_AM::getAM5Opc</a>(AddSub, RHSC),
+<a name="l00903"></a>00903 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00904"></a>00904 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00905"></a>00905 }
+<a name="l00906"></a>00906
+<a name="l00907"></a>00907 Base = N;
+<a name="l00908"></a>00908 Offset = CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#aeaddd028e428140b446fac6bf267f0cf" title="getAM5Opc - This function encodes the addrmode5 opc field.">ARM_AM::getAM5Opc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a5d0557608eaebed12bc00812724ba2cdae6bcee28992dab735eaa43f5dfa48a09">ARM_AM::add</a>, 0),
+<a name="l00909"></a>00909 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00910"></a>00910 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00911"></a>00911 }
+<a name="l00912"></a>00912
+<a name="l00913"></a>00913 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrMode6(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Parent, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Addr,
+<a name="l00914"></a>00914 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Align) {
+<a name="l00915"></a>00915 Addr = N;
+<a name="l00916"></a>00916
+<a name="l00917"></a>00917 <span class="keywordtype">unsigned</span> Alignment = 0;
+<a name="l00918"></a>00918 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1LSBaseSDNode.html">LSBaseSDNode</a> *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
+<a name="l00919"></a>00919 <span class="comment">// This case occurs only for VLD1-lane/dup and VST1-lane instructions.</span>
+<a name="l00920"></a>00920 <span class="comment">// The maximum alignment is equal to the memory size being referenced.</span>
+<a name="l00921"></a>00921 <span class="keywordtype">unsigned</span> LSNAlign = LSN->getAlignment();
+<a name="l00922"></a>00922 <span class="keywordtype">unsigned</span> MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
+<a name="l00923"></a>00923 <span class="keywordflow">if</span> (LSNAlign >= MemSize && MemSize > 1)
+<a name="l00924"></a>00924 Alignment = MemSize;
+<a name="l00925"></a>00925 } <span class="keywordflow">else</span> {
+<a name="l00926"></a>00926 <span class="comment">// All other uses of addrmode6 are for intrinsics. For now just record</span>
+<a name="l00927"></a>00927 <span class="comment">// the raw alignment value; it will be refined later based on the legal</span>
+<a name="l00928"></a>00928 <span class="comment">// alignment operands for the intrinsic.</span>
+<a name="l00929"></a>00929 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
+<a name="l00930"></a>00930 }
+<a name="l00931"></a>00931
+<a name="l00932"></a>00932 Align = CurDAG->getTargetConstant(Alignment, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00933"></a>00933 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00934"></a>00934 }
+<a name="l00935"></a>00935
+<a name="l00936"></a>00936 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrMode6Offset(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00937"></a>00937 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset) {
+<a name="l00938"></a>00938 <a class="code" href="classllvm_1_1LSBaseSDNode.html">LSBaseSDNode</a> *LdSt = cast<LSBaseSDNode>(Op);
+<a name="l00939"></a>00939 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> AM = LdSt-><a class="code" href="classllvm_1_1LSBaseSDNode.html#a76f8f644c33a885eaff35f94c39d5048">getAddressingMode</a>();
+<a name="l00940"></a>00940 <span class="keywordflow">if</span> (AM != <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31a866c29237765ff291c9503abbdca60e1">ISD::POST_INC</a>)
+<a name="l00941"></a>00941 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00942"></a>00942 Offset = N;
+<a name="l00943"></a>00943 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *<a class="code" href="regutils_8h.html#a1fa2460e32327ade49189c95740bc1b5">NC</a> = dyn_cast<ConstantSDNode>(N)) {
+<a name="l00944"></a>00944 <span class="keywordflow">if</span> (<a class="code" href="regutils_8h.html#a1fa2460e32327ade49189c95740bc1b5">NC</a>->getZExtValue() * 8 == LdSt-><a class="code" href="classllvm_1_1MemSDNode.html#a7cead3a2a7771e61083bcc6959915a13" title="getMemoryVT - Return the type of the in-memory value.">getMemoryVT</a>().<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>())
+<a name="l00945"></a>00945 Offset = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00946"></a>00946 }
+<a name="l00947"></a>00947 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00948"></a>00948 }
+<a name="l00949"></a>00949
+<a name="l00950"></a>00950 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectAddrModePC(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00951"></a>00951 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Label) {
+<a name="l00952"></a>00952 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a5bc71a39554a14104bfd1011dffbed0b">ARMISD::PIC_ADD</a> && N.<a class="code" href="classllvm_1_1SDValue.html#a97b0f24f3e52f030830fca6fbfcbd37d">hasOneUse</a>()) {
+<a name="l00953"></a>00953 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00954"></a>00954 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N1 = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00955"></a>00955 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
+<a name="l00956"></a>00956 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l00957"></a>00957 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00958"></a>00958 }
+<a name="l00959"></a>00959
+<a name="l00960"></a>00960 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00961"></a>00961 }
+<a name="l00962"></a>00962
+<a name="l00963"></a>00963
+<a name="l00964"></a>00964 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00965"></a>00965 <span class="comment">// Thumb Addressing Modes</span>
+<a name="l00966"></a>00966 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l00967"></a>00967
+<a name="l00968"></a>00968 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectThumbAddrModeRR(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l00969"></a>00969 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset){
+<a name="l00970"></a>00970 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> && !CurDAG->isBaseWithConstantOffset(N)) {
+<a name="l00971"></a>00971 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *<a class="code" href="regutils_8h.html#a1fa2460e32327ade49189c95740bc1b5">NC</a> = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(N);
+<a name="l00972"></a>00972 <span class="keywordflow">if</span> (!NC || !NC-><a class="code" href="classllvm_1_1ConstantSDNode.html#a702de70a3d9e57c3ffe65bc3fab3e087">isNullValue</a>())
+<a name="l00973"></a>00973 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00974"></a>00974
+<a name="l00975"></a>00975 Base = Offset = N;
+<a name="l00976"></a>00976 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00977"></a>00977 }
+<a name="l00978"></a>00978
+<a name="l00979"></a>00979 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l00980"></a>00980 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l00981"></a>00981 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l00982"></a>00982 }
+<a name="l00983"></a>00983
+<a name="l00984"></a>00984 <span class="keywordtype">bool</span>
+<a name="l00985"></a>00985 ARMDAGToDAGISel::SelectThumbAddrModeRI(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l00986"></a>00986 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset, <span class="keywordtype">unsigned</span> Scale) {
+<a name="l00987"></a>00987 <span class="keywordflow">if</span> (Scale == 4) {
+<a name="l00988"></a>00988 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TmpBase, TmpOffImm;
+<a name="l00989"></a>00989 <span class="keywordflow">if</span> (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
+<a name="l00990"></a>00990 <span class="keywordflow">return</span> <span class="keyword">false</span>; <span class="comment">// We want to select tLDRspi / tSTRspi instead.</span>
+<a name="l00991"></a>00991
+<a name="l00992"></a>00992 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a029f48a0b5e0d471de85baca7745d1a0">ARMISD::Wrapper</a> &&
+<a name="l00993"></a>00993 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a038a7f124b4118456a27a739c03650bf">ISD::TargetConstantPool</a>)
+<a name="l00994"></a>00994 <span class="keywordflow">return</span> <span class="keyword">false</span>; <span class="comment">// We want to select tLDRpci instead.</span>
+<a name="l00995"></a>00995 }
+<a name="l00996"></a>00996
+<a name="l00997"></a>00997 <span class="keywordflow">if</span> (!CurDAG->isBaseWithConstantOffset(N))
+<a name="l00998"></a>00998 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l00999"></a>00999
+<a name="l01000"></a>01000 <span class="comment">// Thumb does not have [sp, r] address mode.</span>
+<a name="l01001"></a>01001 <a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a> *LHSR = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0));
+<a name="l01002"></a>01002 <a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a> *RHSR = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1));
+<a name="l01003"></a>01003 <span class="keywordflow">if</span> ((LHSR && LHSR-><a class="code" href="classllvm_1_1RegisterSDNode.html#a32d3064d680bb98aeec9cabf85995d31">getReg</a>() == ARM::SP) ||
+<a name="l01004"></a>01004 (RHSR && RHSR->getReg() == ARM::SP))
+<a name="l01005"></a>01005 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01006"></a>01006
+<a name="l01007"></a>01007 <span class="comment">// FIXME: Why do we explicitly check for a match here and then return false?</span>
+<a name="l01008"></a>01008 <span class="comment">// Presumably to allow something else to match, but shouldn't this be</span>
+<a name="l01009"></a>01009 <span class="comment">// documented?</span>
+<a name="l01010"></a>01010 <span class="keywordtype">int</span> RHSC;
+<a name="l01011"></a>01011 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), Scale, 0, 32, RHSC))
+<a name="l01012"></a>01012 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01013"></a>01013
+<a name="l01014"></a>01014 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01015"></a>01015 Offset = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l01016"></a>01016 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01017"></a>01017 }
+<a name="l01018"></a>01018
+<a name="l01019"></a>01019 <span class="keywordtype">bool</span>
+<a name="l01020"></a>01020 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l01021"></a>01021 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01022"></a>01022 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset) {
+<a name="l01023"></a>01023 <span class="keywordflow">return</span> SelectThumbAddrModeRI(N, Base, Offset, 1);
+<a name="l01024"></a>01024 }
+<a name="l01025"></a>01025
+<a name="l01026"></a>01026 <span class="keywordtype">bool</span>
+<a name="l01027"></a>01027 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l01028"></a>01028 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01029"></a>01029 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset) {
+<a name="l01030"></a>01030 <span class="keywordflow">return</span> SelectThumbAddrModeRI(N, Base, Offset, 2);
+<a name="l01031"></a>01031 }
+<a name="l01032"></a>01032
+<a name="l01033"></a>01033 <span class="keywordtype">bool</span>
+<a name="l01034"></a>01034 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l01035"></a>01035 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01036"></a>01036 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Offset) {
+<a name="l01037"></a>01037 <span class="keywordflow">return</span> SelectThumbAddrModeRI(N, Base, Offset, 4);
+<a name="l01038"></a>01038 }
+<a name="l01039"></a>01039
+<a name="l01040"></a>01040 <span class="keywordtype">bool</span>
+<a name="l01041"></a>01041 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <span class="keywordtype">unsigned</span> Scale,
+<a name="l01042"></a>01042 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm) {
+<a name="l01043"></a>01043 <span class="keywordflow">if</span> (Scale == 4) {
+<a name="l01044"></a>01044 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TmpBase, TmpOffImm;
+<a name="l01045"></a>01045 <span class="keywordflow">if</span> (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
+<a name="l01046"></a>01046 <span class="keywordflow">return</span> <span class="keyword">false</span>; <span class="comment">// We want to select tLDRspi / tSTRspi instead.</span>
+<a name="l01047"></a>01047
+<a name="l01048"></a>01048 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a029f48a0b5e0d471de85baca7745d1a0">ARMISD::Wrapper</a> &&
+<a name="l01049"></a>01049 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a038a7f124b4118456a27a739c03650bf">ISD::TargetConstantPool</a>)
+<a name="l01050"></a>01050 <span class="keywordflow">return</span> <span class="keyword">false</span>; <span class="comment">// We want to select tLDRpci instead.</span>
+<a name="l01051"></a>01051 }
+<a name="l01052"></a>01052
+<a name="l01053"></a>01053 <span class="keywordflow">if</span> (!CurDAG->isBaseWithConstantOffset(N)) {
+<a name="l01054"></a>01054 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a029f48a0b5e0d471de85baca7745d1a0">ARMISD::Wrapper</a> &&
+<a name="l01055"></a>01055 !(Subtarget->useMovt() &&
+<a name="l01056"></a>01056 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a>)) {
+<a name="l01057"></a>01057 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01058"></a>01058 } <span class="keywordflow">else</span> {
+<a name="l01059"></a>01059 Base = N;
+<a name="l01060"></a>01060 }
+<a name="l01061"></a>01061
+<a name="l01062"></a>01062 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01063"></a>01063 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01064"></a>01064 }
+<a name="l01065"></a>01065
+<a name="l01066"></a>01066 <a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a> *LHSR = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0));
+<a name="l01067"></a>01067 <a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a> *RHSR = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1));
+<a name="l01068"></a>01068 <span class="keywordflow">if</span> ((LHSR && LHSR-><a class="code" href="classllvm_1_1RegisterSDNode.html#a32d3064d680bb98aeec9cabf85995d31">getReg</a>() == ARM::SP) ||
+<a name="l01069"></a>01069 (RHSR && RHSR->getReg() == ARM::SP)) {
+<a name="l01070"></a>01070 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *LHS = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0));
+<a name="l01071"></a>01071 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1));
+<a name="l01072"></a>01072 <span class="keywordtype">unsigned</span> LHSC = LHS ? LHS-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>() : 0;
+<a name="l01073"></a>01073 <span class="keywordtype">unsigned</span> RHSC = RHS ? RHS->getZExtValue() : 0;
+<a name="l01074"></a>01074
+<a name="l01075"></a>01075 <span class="comment">// Thumb does not have [sp, #imm5] address mode for non-zero imm5.</span>
+<a name="l01076"></a>01076 <span class="keywordflow">if</span> (LHSC != 0 || RHSC != 0) <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01077"></a>01077
+<a name="l01078"></a>01078 Base = N;
+<a name="l01079"></a>01079 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01080"></a>01080 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01081"></a>01081 }
+<a name="l01082"></a>01082
+<a name="l01083"></a>01083 <span class="comment">// If the RHS is + imm5 * scale, fold into addr mode.</span>
+<a name="l01084"></a>01084 <span class="keywordtype">int</span> RHSC;
+<a name="l01085"></a>01085 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), Scale, 0, 32, RHSC)) {
+<a name="l01086"></a>01086 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01087"></a>01087 OffImm = CurDAG->getTargetConstant(RHSC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01088"></a>01088 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01089"></a>01089 }
+<a name="l01090"></a>01090
+<a name="l01091"></a>01091 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01092"></a>01092 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01093"></a>01093 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01094"></a>01094 }
+<a name="l01095"></a>01095
+<a name="l01096"></a>01096 <span class="keywordtype">bool</span>
+<a name="l01097"></a>01097 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01098"></a>01098 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm) {
+<a name="l01099"></a>01099 <span class="keywordflow">return</span> SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
+<a name="l01100"></a>01100 }
+<a name="l01101"></a>01101
+<a name="l01102"></a>01102 <span class="keywordtype">bool</span>
+<a name="l01103"></a>01103 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01104"></a>01104 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm) {
+<a name="l01105"></a>01105 <span class="keywordflow">return</span> SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
+<a name="l01106"></a>01106 }
+<a name="l01107"></a>01107
+<a name="l01108"></a>01108 <span class="keywordtype">bool</span>
+<a name="l01109"></a>01109 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01110"></a>01110 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm) {
+<a name="l01111"></a>01111 <span class="keywordflow">return</span> SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
+<a name="l01112"></a>01112 }
+<a name="l01113"></a>01113
+<a name="l01114"></a>01114 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectThumbAddrModeSP(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l01115"></a>01115 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm) {
+<a name="l01116"></a>01116 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l01117"></a>01117 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(N)->getIndex();
+<a name="l01118"></a>01118 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l01119"></a>01119 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01120"></a>01120 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01121"></a>01121 }
+<a name="l01122"></a>01122
+<a name="l01123"></a>01123 <span class="keywordflow">if</span> (!CurDAG->isBaseWithConstantOffset(N))
+<a name="l01124"></a>01124 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01125"></a>01125
+<a name="l01126"></a>01126 <a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a> *LHSR = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1RegisterSDNode.html">RegisterSDNode</a>>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0));
+<a name="l01127"></a>01127 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a> ||
+<a name="l01128"></a>01128 (LHSR && LHSR-><a class="code" href="classllvm_1_1RegisterSDNode.html#a32d3064d680bb98aeec9cabf85995d31">getReg</a>() == ARM::SP)) {
+<a name="l01129"></a>01129 <span class="comment">// If the RHS is + imm8 * scale, fold into addr mode.</span>
+<a name="l01130"></a>01130 <span class="keywordtype">int</span> RHSC;
+<a name="l01131"></a>01131 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1), <span class="comment">/*Scale=*/</span>4, 0, 256, RHSC)) {
+<a name="l01132"></a>01132 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01133"></a>01133 <span class="keywordflow">if</span> (Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l01134"></a>01134 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(Base)->getIndex();
+<a name="l01135"></a>01135 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l01136"></a>01136 }
+<a name="l01137"></a>01137 OffImm = CurDAG->getTargetConstant(RHSC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01138"></a>01138 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01139"></a>01139 }
+<a name="l01140"></a>01140 }
+<a name="l01141"></a>01141
+<a name="l01142"></a>01142 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01143"></a>01143 }
+<a name="l01144"></a>01144
+<a name="l01145"></a>01145
+<a name="l01146"></a>01146 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l01147"></a>01147 <span class="comment">// Thumb 2 Addressing Modes</span>
+<a name="l01148"></a>01148 <span class="comment">//===----------------------------------------------------------------------===//</span>
+<a name="l01149"></a>01149
+<a name="l01150"></a>01150
+<a name="l01151"></a>01151 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectT2ShifterOperandReg(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &BaseReg,
+<a name="l01152"></a>01152 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Opc) {
+<a name="l01153"></a>01153 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a775cda86be29a0e990bbeb92f84f57bb">DisableShifterOp</a>)
+<a name="l01154"></a>01154 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01155"></a>01155
+<a name="l01156"></a>01156 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l01157"></a>01157
+<a name="l01158"></a>01158 <span class="comment">// Don't match base register only case. That is matched to a separate</span>
+<a name="l01159"></a>01159 <span class="comment">// lower complexity pattern with explicit register operand.</span>
+<a name="l01160"></a>01160 <span class="keywordflow">if</span> (ShOpcVal == <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>) <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01161"></a>01161
+<a name="l01162"></a>01162 BaseReg = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01163"></a>01163 <span class="keywordtype">unsigned</span> ShImmVal = 0;
+<a name="l01164"></a>01164 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l01165"></a>01165 ShImmVal = RHS->getZExtValue() & 31;
+<a name="l01166"></a>01166 Opc = getI32Imm(<a class="code" href="namespacellvm_1_1ARM__AM.html#a257cdd16d16d0a9d9b358b5e5a472258">ARM_AM::getSORegOpc</a>(ShOpcVal, ShImmVal));
+<a name="l01167"></a>01167 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01168"></a>01168 }
+<a name="l01169"></a>01169
+<a name="l01170"></a>01170 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01171"></a>01171 }
+<a name="l01172"></a>01172
+<a name="l01173"></a>01173 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectT2AddrModeImm12(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l01174"></a>01174 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm) {
+<a name="l01175"></a>01175 <span class="comment">// Match simple R + imm12 operands.</span>
+<a name="l01176"></a>01176
+<a name="l01177"></a>01177 <span class="comment">// Base only.</span>
+<a name="l01178"></a>01178 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> && N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> &&
+<a name="l01179"></a>01179 !CurDAG->isBaseWithConstantOffset(N)) {
+<a name="l01180"></a>01180 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l01181"></a>01181 <span class="comment">// Match frame index.</span>
+<a name="l01182"></a>01182 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(N)->getIndex();
+<a name="l01183"></a>01183 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l01184"></a>01184 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01185"></a>01185 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01186"></a>01186 }
+<a name="l01187"></a>01187
+<a name="l01188"></a>01188 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a029f48a0b5e0d471de85baca7745d1a0">ARMISD::Wrapper</a> &&
+<a name="l01189"></a>01189 !(Subtarget->useMovt() &&
+<a name="l01190"></a>01190 N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a87b8176af163ee944af127081d24f4a2">ISD::TargetGlobalAddress</a>)) {
+<a name="l01191"></a>01191 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01192"></a>01192 <span class="keywordflow">if</span> (Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a038a7f124b4118456a27a739c03650bf">ISD::TargetConstantPool</a>)
+<a name="l01193"></a>01193 <span class="keywordflow">return</span> <span class="keyword">false</span>; <span class="comment">// We want to select t2LDRpci instead.</span>
+<a name="l01194"></a>01194 } <span class="keywordflow">else</span>
+<a name="l01195"></a>01195 Base = N;
+<a name="l01196"></a>01196 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01197"></a>01197 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01198"></a>01198 }
+<a name="l01199"></a>01199
+<a name="l01200"></a>01200 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l01201"></a>01201 <span class="keywordflow">if</span> (SelectT2AddrModeImm8(N, Base, OffImm))
+<a name="l01202"></a>01202 <span class="comment">// Let t2LDRi8 handle (R - imm8).</span>
+<a name="l01203"></a>01203 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01204"></a>01204
+<a name="l01205"></a>01205 <span class="keywordtype">int</span> RHSC = (int)RHS->getZExtValue();
+<a name="l01206"></a>01206 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>)
+<a name="l01207"></a>01207 RHSC = -RHSC;
+<a name="l01208"></a>01208
+<a name="l01209"></a>01209 <span class="keywordflow">if</span> (RHSC >= 0 && RHSC < 0x1000) { <span class="comment">// 12 bits (unsigned)</span>
+<a name="l01210"></a>01210 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01211"></a>01211 <span class="keywordflow">if</span> (Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l01212"></a>01212 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(Base)->getIndex();
+<a name="l01213"></a>01213 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l01214"></a>01214 }
+<a name="l01215"></a>01215 OffImm = CurDAG->getTargetConstant(RHSC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01216"></a>01216 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01217"></a>01217 }
+<a name="l01218"></a>01218 }
+<a name="l01219"></a>01219
+<a name="l01220"></a>01220 <span class="comment">// Base only.</span>
+<a name="l01221"></a>01221 Base = N;
+<a name="l01222"></a>01222 OffImm = CurDAG->getTargetConstant(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01223"></a>01223 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01224"></a>01224 }
+<a name="l01225"></a>01225
+<a name="l01226"></a>01226 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectT2AddrModeImm8(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l01227"></a>01227 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm) {
+<a name="l01228"></a>01228 <span class="comment">// Match simple R - imm8 operands.</span>
+<a name="l01229"></a>01229 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> && N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a> &&
+<a name="l01230"></a>01230 !CurDAG->isBaseWithConstantOffset(N))
+<a name="l01231"></a>01231 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01232"></a>01232
+<a name="l01233"></a>01233 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l01234"></a>01234 <span class="keywordtype">int</span> RHSC = (int)RHS->getSExtValue();
+<a name="l01235"></a>01235 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a9fa617e5567c3c2638938f7b9ddc3f1c">ISD::SUB</a>)
+<a name="l01236"></a>01236 RHSC = -RHSC;
+<a name="l01237"></a>01237
+<a name="l01238"></a>01238 <span class="keywordflow">if</span> ((RHSC >= -255) && (RHSC < 0)) { <span class="comment">// 8 bits (always negative)</span>
+<a name="l01239"></a>01239 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01240"></a>01240 <span class="keywordflow">if</span> (Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>) {
+<a name="l01241"></a>01241 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(Base)->getIndex();
+<a name="l01242"></a>01242 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l01243"></a>01243 }
+<a name="l01244"></a>01244 OffImm = CurDAG->getTargetConstant(RHSC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01245"></a>01245 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01246"></a>01246 }
+<a name="l01247"></a>01247 }
+<a name="l01248"></a>01248
+<a name="l01249"></a>01249 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01250"></a>01250 }
+<a name="l01251"></a>01251
+<a name="l01252"></a>01252 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Op, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l01253"></a>01253 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffImm){
+<a name="l01254"></a>01254 <span class="keywordtype">unsigned</span> Opcode = Op-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>();
+<a name="l01255"></a>01255 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> AM = (Opcode == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a>)
+<a name="l01256"></a>01256 ? cast<LoadSDNode>(Op)->getAddressingMode()
+<a name="l01257"></a>01257 : cast<StoreSDNode>(Op)->getAddressingMode();
+<a name="l01258"></a>01258 <span class="keywordtype">int</span> RHSC;
+<a name="l01259"></a>01259 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#aff84d21c1e747c062f6a9198cf7b50d2" title="Check whether a particular node is a constant value representable as (N * Scale) where (N in [RangeMi...">isScaledConstantInRange</a>(N, <span class="comment">/*Scale=*/</span>1, 0, 0x100, RHSC)) { <span class="comment">// 8 bits.</span>
+<a name="l01260"></a>01260 OffImm = ((AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>) || (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31a866c29237765ff291c9503abbdca60e1">ISD::POST_INC</a>))
+<a name="l01261"></a>01261 ? CurDAG->getTargetConstant(RHSC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>)
+<a name="l01262"></a>01262 : CurDAG->getTargetConstant(-RHSC, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01263"></a>01263 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01264"></a>01264 }
+<a name="l01265"></a>01265
+<a name="l01266"></a>01266 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01267"></a>01267 }
+<a name="l01268"></a>01268
+<a name="l01269"></a>01269 <span class="keywordtype">bool</span> ARMDAGToDAGISel::SelectT2AddrModeSoReg(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N,
+<a name="l01270"></a>01270 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Base,
+<a name="l01271"></a>01271 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &OffReg, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &ShImm) {
+<a name="l01272"></a>01272 <span class="comment">// (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.</span>
+<a name="l01273"></a>01273 <span class="keywordflow">if</span> (N.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> && !CurDAG->isBaseWithConstantOffset(N))
+<a name="l01274"></a>01274 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01275"></a>01275
+<a name="l01276"></a>01276 <span class="comment">// Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.</span>
+<a name="l01277"></a>01277 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *RHS = dyn_cast<ConstantSDNode>(N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l01278"></a>01278 <span class="keywordtype">int</span> RHSC = (int)RHS->getZExtValue();
+<a name="l01279"></a>01279 <span class="keywordflow">if</span> (RHSC >= 0 && RHSC < 0x1000) <span class="comment">// 12 bits (unsigned)</span>
+<a name="l01280"></a>01280 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01281"></a>01281 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (RHSC < 0 && RHSC >= -255) <span class="comment">// 8 bits</span>
+<a name="l01282"></a>01282 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l01283"></a>01283 }
+<a name="l01284"></a>01284
+<a name="l01285"></a>01285 <span class="comment">// Look for (R + R) or (R + (R << [1,2,3])).</span>
+<a name="l01286"></a>01286 <span class="keywordtype">unsigned</span> ShAmt = 0;
+<a name="l01287"></a>01287 Base = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01288"></a>01288 OffReg = N.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l01289"></a>01289
+<a name="l01290"></a>01290 <span class="comment">// Swap if it is ((R << c) + R).</span>
+<a name="l01291"></a>01291 <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239ef">ARM_AM::ShiftOpc</a> ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(OffReg.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l01292"></a>01292 <span class="keywordflow">if</span> (ShOpcVal != <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a>) {
+<a name="l01293"></a>01293 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a0f0e8b13220b4094b0eade6c4a691a68">ARM_AM::getShiftOpcForNode</a>(Base.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>());
+<a name="l01294"></a>01294 <span class="keywordflow">if</span> (ShOpcVal == <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a>)
+<a name="l01295"></a>01295 <a class="code" href="namespacellvm.html#a39bdaf6372ed2ef16d951fc0f6d54dd4">std::swap</a>(Base, OffReg);
+<a name="l01296"></a>01296 }
+<a name="l01297"></a>01297
+<a name="l01298"></a>01298 <span class="keywordflow">if</span> (ShOpcVal == <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a>) {
+<a name="l01299"></a>01299 <span class="comment">// Check to see if the RHS of the shift is a constant, if not, we can't fold</span>
+<a name="l01300"></a>01300 <span class="comment">// it.</span>
+<a name="l01301"></a>01301 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *Sh = dyn_cast<ConstantSDNode>(OffReg.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1))) {
+<a name="l01302"></a>01302 ShAmt = Sh->getZExtValue();
+<a name="l01303"></a>01303 <span class="keywordflow">if</span> (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
+<a name="l01304"></a>01304 OffReg = OffReg.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l01305"></a>01305 <span class="keywordflow">else</span> {
+<a name="l01306"></a>01306 ShAmt = 0;
+<a name="l01307"></a>01307 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l01308"></a>01308 }
+<a name="l01309"></a>01309 } <span class="keywordflow">else</span> {
+<a name="l01310"></a>01310 ShOpcVal = <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa52ce105a97f77049ddfe808bbf0f3eac">ARM_AM::no_shift</a>;
+<a name="l01311"></a>01311 }
+<a name="l01312"></a>01312 }
+<a name="l01313"></a>01313
+<a name="l01314"></a>01314 ShImm = CurDAG->getTargetConstant(ShAmt, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01315"></a>01315
+<a name="l01316"></a>01316 <span class="keywordflow">return</span> <span class="keyword">true</span>;
+<a name="l01317"></a>01317 }
+<a name="l01318"></a>01318
+<a name="l01319"></a>01319 <span class="comment">//===--------------------------------------------------------------------===//</span>
+<a name="l01320"></a>01320 <span class="comment"></span>
+<a name="l01321"></a>01321 <span class="comment">/// getAL - Returns a ARMCC::AL immediate node.</span>
+<a name="l01322"></a><a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551">01322</a> <span class="comment"></span><span class="keyword">static</span> <span class="keyword">inline</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(<a class="code" href="classllvm_1_1SelectionDAG.html">SelectionDAG</a> *CurDAG) {
+<a name="l01323"></a>01323 <span class="keywordflow">return</span> CurDAG-><a class="code" href="classllvm_1_1SelectionDAG.html#ace5bddfde14abf966790e8438e88d6d2">getTargetConstant</a>((uint64_t)<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6a8b2ef77967dee1220cc6ee5aee595e11">ARMCC::AL</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01324"></a>01324 }
+<a name="l01325"></a>01325
+<a name="l01326"></a>01326 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectARMIndexedLoad(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l01327"></a>01327 <a class="code" href="classllvm_1_1LoadSDNode.html">LoadSDNode</a> *LD = cast<LoadSDNode>(N);
+<a name="l01328"></a>01328 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> AM = LD-><a class="code" href="classllvm_1_1LSBaseSDNode.html#a76f8f644c33a885eaff35f94c39d5048">getAddressingMode</a>();
+<a name="l01329"></a>01329 <span class="keywordflow">if</span> (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ade1c53e7b8a373e22ec53ff7bcbace9f">ISD::UNINDEXED</a>)
+<a name="l01330"></a>01330 <span class="keywordflow">return</span> NULL;
+<a name="l01331"></a>01331
+<a name="l01332"></a>01332 <a class="code" href="structllvm_1_1EVT.html">EVT</a> LoadedVT = LD-><a class="code" href="classllvm_1_1MemSDNode.html#a7cead3a2a7771e61083bcc6959915a13" title="getMemoryVT - Return the type of the in-memory value.">getMemoryVT</a>();
+<a name="l01333"></a>01333 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Offset, AMOpc;
+<a name="l01334"></a>01334 <span class="keywordtype">bool</span> isPre = (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>) || (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31a57c3822f99653c422d5a21206adc6e42">ISD::PRE_DEC</a>);
+<a name="l01335"></a>01335 <span class="keywordtype">unsigned</span> Opcode = 0;
+<a name="l01336"></a>01336 <span class="keywordtype">bool</span> Match = <span class="keyword">false</span>;
+<a name="l01337"></a>01337 <span class="keywordflow">if</span> (LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> && isPre &&
+<a name="l01338"></a>01338 SelectAddrMode2OffsetImmPre(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset, AMOpc)) {
+<a name="l01339"></a>01339 Opcode = ARM::LDR_PRE_IMM;
+<a name="l01340"></a>01340 Match = <span class="keyword">true</span>;
+<a name="l01341"></a>01341 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> && !isPre &&
+<a name="l01342"></a>01342 SelectAddrMode2OffsetImm(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset, AMOpc)) {
+<a name="l01343"></a>01343 Opcode = ARM::LDR_POST_IMM;
+<a name="l01344"></a>01344 Match = <span class="keyword">true</span>;
+<a name="l01345"></a>01345 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a> &&
+<a name="l01346"></a>01346 SelectAddrMode2OffsetReg(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset, AMOpc)) {
+<a name="l01347"></a>01347 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
+<a name="l01348"></a>01348 Match = <span class="keyword">true</span>;
+<a name="l01349"></a>01349
+<a name="l01350"></a>01350 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a> &&
+<a name="l01351"></a>01351 SelectAddrMode3Offset(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset, AMOpc)) {
+<a name="l01352"></a>01352 Match = <span class="keyword">true</span>;
+<a name="l01353"></a>01353 Opcode = (LD-><a class="code" href="classllvm_1_1LoadSDNode.html#af15fb8b2d4c9f295bdcf85a1eb506702">getExtensionType</a>() == <a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a>)
+<a name="l01354"></a>01354 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
+<a name="l01355"></a>01355 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
+<a name="l01356"></a>01356 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a> || LoadedVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>) {
+<a name="l01357"></a>01357 <span class="keywordflow">if</span> (LD-><a class="code" href="classllvm_1_1LoadSDNode.html#af15fb8b2d4c9f295bdcf85a1eb506702">getExtensionType</a>() == <a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a>) {
+<a name="l01358"></a>01358 <span class="keywordflow">if</span> (SelectAddrMode3Offset(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset, AMOpc)) {
+<a name="l01359"></a>01359 Match = <span class="keyword">true</span>;
+<a name="l01360"></a>01360 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
+<a name="l01361"></a>01361 }
+<a name="l01362"></a>01362 } <span class="keywordflow">else</span> {
+<a name="l01363"></a>01363 <span class="keywordflow">if</span> (isPre &&
+<a name="l01364"></a>01364 SelectAddrMode2OffsetImmPre(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset, AMOpc)) {
+<a name="l01365"></a>01365 Match = <span class="keyword">true</span>;
+<a name="l01366"></a>01366 Opcode = ARM::LDRB_PRE_IMM;
+<a name="l01367"></a>01367 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (!isPre &&
+<a name="l01368"></a>01368 SelectAddrMode2OffsetImm(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset, AMOpc)) {
+<a name="l01369"></a>01369 Match = <span class="keyword">true</span>;
+<a name="l01370"></a>01370 Opcode = ARM::LDRB_POST_IMM;
+<a name="l01371"></a>01371 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (SelectAddrMode2OffsetReg(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset, AMOpc)) {
+<a name="l01372"></a>01372 Match = <span class="keyword">true</span>;
+<a name="l01373"></a>01373 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
+<a name="l01374"></a>01374 }
+<a name="l01375"></a>01375 }
+<a name="l01376"></a>01376 }
+<a name="l01377"></a>01377
+<a name="l01378"></a>01378 <span class="keywordflow">if</span> (Match) {
+<a name="l01379"></a>01379 <span class="keywordflow">if</span> (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
+<a name="l01380"></a>01380 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = LD-><a class="code" href="classllvm_1_1MemSDNode.html#ae3cb6fbf8c8cb79e10ac61bd98c85211">getChain</a>();
+<a name="l01381"></a>01381 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Base = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#a3ded48ce66b58b7e7e143991df5dbfae">getBasePtr</a>();
+<a name="l01382"></a>01382 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[]= { Base, AMOpc, <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l01383"></a>01383 CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>), Chain };
+<a name="l01384"></a>01384 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opcode, N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>(), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l01385"></a>01385 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Ops, 5);
+<a name="l01386"></a>01386 } <span class="keywordflow">else</span> {
+<a name="l01387"></a>01387 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = LD-><a class="code" href="classllvm_1_1MemSDNode.html#ae3cb6fbf8c8cb79e10ac61bd98c85211">getChain</a>();
+<a name="l01388"></a>01388 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Base = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#a3ded48ce66b58b7e7e143991df5dbfae">getBasePtr</a>();
+<a name="l01389"></a>01389 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[]= { Base, Offset, AMOpc, <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l01390"></a>01390 CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>), Chain };
+<a name="l01391"></a>01391 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opcode, N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>(), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l01392"></a>01392 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Ops, 6);
+<a name="l01393"></a>01393 }
+<a name="l01394"></a>01394 }
+<a name="l01395"></a>01395
+<a name="l01396"></a>01396 <span class="keywordflow">return</span> NULL;
+<a name="l01397"></a>01397 }
+<a name="l01398"></a>01398
+<a name="l01399"></a>01399 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectT2IndexedLoad(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l01400"></a>01400 <a class="code" href="classllvm_1_1LoadSDNode.html">LoadSDNode</a> *LD = cast<LoadSDNode>(N);
+<a name="l01401"></a>01401 <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31">ISD::MemIndexedMode</a> AM = LD-><a class="code" href="classllvm_1_1LSBaseSDNode.html#a76f8f644c33a885eaff35f94c39d5048">getAddressingMode</a>();
+<a name="l01402"></a>01402 <span class="keywordflow">if</span> (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ade1c53e7b8a373e22ec53ff7bcbace9f">ISD::UNINDEXED</a>)
+<a name="l01403"></a>01403 <span class="keywordflow">return</span> NULL;
+<a name="l01404"></a>01404
+<a name="l01405"></a>01405 <a class="code" href="structllvm_1_1EVT.html">EVT</a> LoadedVT = LD-><a class="code" href="classllvm_1_1MemSDNode.html#a7cead3a2a7771e61083bcc6959915a13" title="getMemoryVT - Return the type of the in-memory value.">getMemoryVT</a>();
+<a name="l01406"></a>01406 <span class="keywordtype">bool</span> isSExtLd = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#af15fb8b2d4c9f295bdcf85a1eb506702">getExtensionType</a>() == <a class="code" href="namespacellvm_1_1ISD.html#ad4d48171b87ca51ff54c10a436bac4d7a6c61b6125c7901c549f90ee0e443a770">ISD::SEXTLOAD</a>;
+<a name="l01407"></a>01407 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Offset;
+<a name="l01408"></a>01408 <span class="keywordtype">bool</span> isPre = (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31ab5bb854fadd42503c849c4a48d7f3d90">ISD::PRE_INC</a>) || (AM == <a class="code" href="namespacellvm_1_1ISD.html#abee7ecb577fcade34eb16ccb7f503e31a57c3822f99653c422d5a21206adc6e42">ISD::PRE_DEC</a>);
+<a name="l01409"></a>01409 <span class="keywordtype">unsigned</span> Opcode = 0;
+<a name="l01410"></a>01410 <span class="keywordtype">bool</span> Match = <span class="keyword">false</span>;
+<a name="l01411"></a>01411 <span class="keywordflow">if</span> (SelectT2AddrModeImm8Offset(N, LD-><a class="code" href="classllvm_1_1LoadSDNode.html#ae769a35bdc5f1748a40134166a312901">getOffset</a>(), Offset)) {
+<a name="l01412"></a>01412 <span class="keywordflow">switch</span> (LoadedVT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l01413"></a>01413 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>:
+<a name="l01414"></a>01414 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
+<a name="l01415"></a>01415 <span class="keywordflow">break</span>;
+<a name="l01416"></a>01416 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cab3be25b50efa0289a3c86fd50454b683">MVT::i16</a>:
+<a name="l01417"></a>01417 <span class="keywordflow">if</span> (isSExtLd)
+<a name="l01418"></a>01418 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
+<a name="l01419"></a>01419 <span class="keywordflow">else</span>
+<a name="l01420"></a>01420 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
+<a name="l01421"></a>01421 <span class="keywordflow">break</span>;
+<a name="l01422"></a>01422 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf777e086e32f60c0c87b460964eae7d0">MVT::i8</a>:
+<a name="l01423"></a>01423 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca85440bbdbba12de574c02e515444d3f4">MVT::i1</a>:
+<a name="l01424"></a>01424 <span class="keywordflow">if</span> (isSExtLd)
+<a name="l01425"></a>01425 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
+<a name="l01426"></a>01426 <span class="keywordflow">else</span>
+<a name="l01427"></a>01427 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
+<a name="l01428"></a>01428 <span class="keywordflow">break</span>;
+<a name="l01429"></a>01429 <span class="keywordflow">default</span>:
+<a name="l01430"></a>01430 <span class="keywordflow">return</span> NULL;
+<a name="l01431"></a>01431 }
+<a name="l01432"></a>01432 Match = <span class="keyword">true</span>;
+<a name="l01433"></a>01433 }
+<a name="l01434"></a>01434
+<a name="l01435"></a>01435 <span class="keywordflow">if</span> (Match) {
+<a name="l01436"></a>01436 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = LD-><a class="code" href="classllvm_1_1MemSDNode.html#ae3cb6fbf8c8cb79e10ac61bd98c85211">getChain</a>();
+<a name="l01437"></a>01437 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Base = LD-><a class="code" href="classllvm_1_1LoadSDNode.html#a3ded48ce66b58b7e7e143991df5dbfae">getBasePtr</a>();
+<a name="l01438"></a>01438 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[]= { Base, Offset, <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l01439"></a>01439 CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>), Chain };
+<a name="l01440"></a>01440 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opcode, N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>(), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,
+<a name="l01441"></a>01441 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, Ops, 5);
+<a name="l01442"></a>01442 }
+<a name="l01443"></a>01443
+<a name="l01444"></a>01444 <span class="keywordflow">return</span> NULL;
+<a name="l01445"></a>01445 }
+<a name="l01446"></a>01446 <span class="comment"></span>
+<a name="l01447"></a>01447 <span class="comment">/// PairSRegs - Form a D register from a pair of S registers.</span>
+<a name="l01448"></a>01448 <span class="comment">///</span>
+<a name="l01449"></a>01449 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::PairSRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1) {
+<a name="l01450"></a>01450 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = V0.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01451"></a>01451 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegClass =
+<a name="l01452"></a>01452 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01453"></a>01453 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01454"></a>01454 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01455"></a>01455 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
+<a name="l01456"></a>01456 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaafeda787b63f1bfa875e4cb8afe2b5ea9">TargetOpcode::REG_SEQUENCE</a>, dl, VT, Ops, 5);
+<a name="l01457"></a>01457 }
+<a name="l01458"></a>01458 <span class="comment"></span>
+<a name="l01459"></a>01459 <span class="comment">/// PairDRegs - Form a quad register from a pair of D registers.</span>
+<a name="l01460"></a>01460 <span class="comment">///</span>
+<a name="l01461"></a>01461 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::PairDRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1) {
+<a name="l01462"></a>01462 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = V0.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01463"></a>01463 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01464"></a>01464 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01465"></a>01465 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01466"></a>01466 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
+<a name="l01467"></a>01467 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaafeda787b63f1bfa875e4cb8afe2b5ea9">TargetOpcode::REG_SEQUENCE</a>, dl, VT, Ops, 5);
+<a name="l01468"></a>01468 }
+<a name="l01469"></a>01469 <span class="comment"></span>
+<a name="l01470"></a>01470 <span class="comment">/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.</span>
+<a name="l01471"></a>01471 <span class="comment">///</span>
+<a name="l01472"></a>01472 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::PairQRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1) {
+<a name="l01473"></a>01473 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = V0.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01474"></a>01474 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01475"></a>01475 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01476"></a>01476 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01477"></a>01477 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
+<a name="l01478"></a>01478 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaafeda787b63f1bfa875e4cb8afe2b5ea9">TargetOpcode::REG_SEQUENCE</a>, dl, VT, Ops, 5);
+<a name="l01479"></a>01479 }
+<a name="l01480"></a>01480 <span class="comment"></span>
+<a name="l01481"></a>01481 <span class="comment">/// QuadSRegs - Form 4 consecutive S registers.</span>
+<a name="l01482"></a>01482 <span class="comment">///</span>
+<a name="l01483"></a>01483 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::QuadSRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1,
+<a name="l01484"></a>01484 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a>, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3) {
+<a name="l01485"></a>01485 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = V0.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01486"></a>01486 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegClass =
+<a name="l01487"></a>01487 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01488"></a>01488 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01489"></a>01489 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01490"></a>01490 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01491"></a>01491 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01492"></a>01492 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
+<a name="l01493"></a>01493 <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a>, SubReg2, V3, SubReg3 };
+<a name="l01494"></a>01494 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaafeda787b63f1bfa875e4cb8afe2b5ea9">TargetOpcode::REG_SEQUENCE</a>, dl, VT, Ops, 9);
+<a name="l01495"></a>01495 }
+<a name="l01496"></a>01496 <span class="comment"></span>
+<a name="l01497"></a>01497 <span class="comment">/// QuadDRegs - Form 4 consecutive D registers.</span>
+<a name="l01498"></a>01498 <span class="comment">///</span>
+<a name="l01499"></a>01499 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::QuadDRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1,
+<a name="l01500"></a>01500 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V2, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3) {
+<a name="l01501"></a>01501 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = V0.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01502"></a>01502 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01503"></a>01503 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01504"></a>01504 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01505"></a>01505 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01506"></a>01506 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01507"></a>01507 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
+<a name="l01508"></a>01508 <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a>, SubReg2, V3, SubReg3 };
+<a name="l01509"></a>01509 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaafeda787b63f1bfa875e4cb8afe2b5ea9">TargetOpcode::REG_SEQUENCE</a>, dl, VT, Ops, 9);
+<a name="l01510"></a>01510 }
+<a name="l01511"></a>01511 <span class="comment"></span>
+<a name="l01512"></a>01512 <span class="comment">/// QuadQRegs - Form 4 consecutive Q registers.</span>
+<a name="l01513"></a>01513 <span class="comment">///</span>
+<a name="l01514"></a>01514 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::QuadQRegs(<a class="code" href="structllvm_1_1EVT.html">EVT</a> VT, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1,
+<a name="l01515"></a>01515 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V2, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3) {
+<a name="l01516"></a>01516 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = V0.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01517"></a>01517 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01518"></a>01518 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01519"></a>01519 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01520"></a>01520 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01521"></a>01521 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01522"></a>01522 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
+<a name="l01523"></a>01523 <a class="code" href="namespacellvm_1_1NVPTX_1_1PTXLdStInstCode.html#a91119cbee2be000c528a690252aee07ca24244a27b634ef3e256ab3c64c6fecd4">V2</a>, SubReg2, V3, SubReg3 };
+<a name="l01524"></a>01524 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaafeda787b63f1bfa875e4cb8afe2b5ea9">TargetOpcode::REG_SEQUENCE</a>, dl, VT, Ops, 9);
+<a name="l01525"></a>01525 }
+<a name="l01526"></a>01526 <span class="comment"></span>
+<a name="l01527"></a>01527 <span class="comment">/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand</span>
+<a name="l01528"></a>01528 <span class="comment">/// of a NEON VLD or VST instruction. The supported values depend on the</span>
+<a name="l01529"></a>01529 <span class="comment">/// number of registers being loaded.</span>
+<a name="l01530"></a>01530 <span class="comment"></span><a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ARMDAGToDAGISel::GetVLDSTAlign(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Align, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l01531"></a>01531 <span class="keywordtype">bool</span> is64BitVector) {
+<a name="l01532"></a>01532 <span class="keywordtype">unsigned</span> NumRegs = NumVecs;
+<a name="l01533"></a>01533 <span class="keywordflow">if</span> (!is64BitVector && NumVecs < 3)
+<a name="l01534"></a>01534 NumRegs *= 2;
+<a name="l01535"></a>01535
+<a name="l01536"></a>01536 <span class="keywordtype">unsigned</span> Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
+<a name="l01537"></a>01537 <span class="keywordflow">if</span> (Alignment >= 32 && NumRegs == 4)
+<a name="l01538"></a>01538 Alignment = 32;
+<a name="l01539"></a>01539 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
+<a name="l01540"></a>01540 Alignment = 16;
+<a name="l01541"></a>01541 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Alignment >= 8)
+<a name="l01542"></a>01542 Alignment = 8;
+<a name="l01543"></a>01543 <span class="keywordflow">else</span>
+<a name="l01544"></a>01544 Alignment = 0;
+<a name="l01545"></a>01545
+<a name="l01546"></a>01546 <span class="keywordflow">return</span> CurDAG->getTargetConstant(Alignment, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01547"></a>01547 }
+<a name="l01548"></a>01548
+<a name="l01549"></a>01549 <span class="comment">// Get the register stride update opcode of a VLD/VST instruction that</span>
+<a name="l01550"></a>01550 <span class="comment">// is otherwise equivalent to the given fixed stride updating instruction.</span>
+<a name="l01551"></a><a class="code" href="ARMISelDAGToDAG_8cpp.html#a3b274201fdc7fbf1fc5f91a661b9410f">01551</a> <span class="keyword">static</span> <span class="keywordtype">unsigned</span> <a class="code" href="ARMISelDAGToDAG_8cpp.html#a3b274201fdc7fbf1fc5f91a661b9410f">getVLDSTRegisterUpdateOpcode</a>(<span class="keywordtype">unsigned</span> Opc) {
+<a name="l01552"></a>01552 <span class="keywordflow">switch</span> (Opc) {
+<a name="l01553"></a>01553 <span class="keywordflow">default</span>: <span class="keywordflow">break</span>;
+<a name="l01554"></a>01554 <span class="keywordflow">case</span> ARM::VLD1d8wb_fixed: <span class="keywordflow">return</span> ARM::VLD1d8wb_register;
+<a name="l01555"></a>01555 <span class="keywordflow">case</span> ARM::VLD1d16wb_fixed: <span class="keywordflow">return</span> ARM::VLD1d16wb_register;
+<a name="l01556"></a>01556 <span class="keywordflow">case</span> ARM::VLD1d32wb_fixed: <span class="keywordflow">return</span> ARM::VLD1d32wb_register;
+<a name="l01557"></a>01557 <span class="keywordflow">case</span> ARM::VLD1d64wb_fixed: <span class="keywordflow">return</span> ARM::VLD1d64wb_register;
+<a name="l01558"></a>01558 <span class="keywordflow">case</span> ARM::VLD1q8wb_fixed: <span class="keywordflow">return</span> ARM::VLD1q8wb_register;
+<a name="l01559"></a>01559 <span class="keywordflow">case</span> ARM::VLD1q16wb_fixed: <span class="keywordflow">return</span> ARM::VLD1q16wb_register;
+<a name="l01560"></a>01560 <span class="keywordflow">case</span> ARM::VLD1q32wb_fixed: <span class="keywordflow">return</span> ARM::VLD1q32wb_register;
+<a name="l01561"></a>01561 <span class="keywordflow">case</span> ARM::VLD1q64wb_fixed: <span class="keywordflow">return</span> ARM::VLD1q64wb_register;
+<a name="l01562"></a>01562
+<a name="l01563"></a>01563 <span class="keywordflow">case</span> ARM::VST1d8wb_fixed: <span class="keywordflow">return</span> ARM::VST1d8wb_register;
+<a name="l01564"></a>01564 <span class="keywordflow">case</span> ARM::VST1d16wb_fixed: <span class="keywordflow">return</span> ARM::VST1d16wb_register;
+<a name="l01565"></a>01565 <span class="keywordflow">case</span> ARM::VST1d32wb_fixed: <span class="keywordflow">return</span> ARM::VST1d32wb_register;
+<a name="l01566"></a>01566 <span class="keywordflow">case</span> ARM::VST1d64wb_fixed: <span class="keywordflow">return</span> ARM::VST1d64wb_register;
+<a name="l01567"></a>01567 <span class="keywordflow">case</span> ARM::VST1q8wb_fixed: <span class="keywordflow">return</span> ARM::VST1q8wb_register;
+<a name="l01568"></a>01568 <span class="keywordflow">case</span> ARM::VST1q16wb_fixed: <span class="keywordflow">return</span> ARM::VST1q16wb_register;
+<a name="l01569"></a>01569 <span class="keywordflow">case</span> ARM::VST1q32wb_fixed: <span class="keywordflow">return</span> ARM::VST1q32wb_register;
+<a name="l01570"></a>01570 <span class="keywordflow">case</span> ARM::VST1q64wb_fixed: <span class="keywordflow">return</span> ARM::VST1q64wb_register;
+<a name="l01571"></a>01571 <span class="keywordflow">case</span> ARM::VST1d64TPseudoWB_fixed: <span class="keywordflow">return</span> ARM::VST1d64TPseudoWB_register;
+<a name="l01572"></a>01572 <span class="keywordflow">case</span> ARM::VST1d64QPseudoWB_fixed: <span class="keywordflow">return</span> ARM::VST1d64QPseudoWB_register;
+<a name="l01573"></a>01573
+<a name="l01574"></a>01574 <span class="keywordflow">case</span> ARM::VLD2d8wb_fixed: <span class="keywordflow">return</span> ARM::VLD2d8wb_register;
+<a name="l01575"></a>01575 <span class="keywordflow">case</span> ARM::VLD2d16wb_fixed: <span class="keywordflow">return</span> ARM::VLD2d16wb_register;
+<a name="l01576"></a>01576 <span class="keywordflow">case</span> ARM::VLD2d32wb_fixed: <span class="keywordflow">return</span> ARM::VLD2d32wb_register;
+<a name="l01577"></a>01577 <span class="keywordflow">case</span> ARM::VLD2q8PseudoWB_fixed: <span class="keywordflow">return</span> ARM::VLD2q8PseudoWB_register;
+<a name="l01578"></a>01578 <span class="keywordflow">case</span> ARM::VLD2q16PseudoWB_fixed: <span class="keywordflow">return</span> ARM::VLD2q16PseudoWB_register;
+<a name="l01579"></a>01579 <span class="keywordflow">case</span> ARM::VLD2q32PseudoWB_fixed: <span class="keywordflow">return</span> ARM::VLD2q32PseudoWB_register;
+<a name="l01580"></a>01580
+<a name="l01581"></a>01581 <span class="keywordflow">case</span> ARM::VST2d8wb_fixed: <span class="keywordflow">return</span> ARM::VST2d8wb_register;
+<a name="l01582"></a>01582 <span class="keywordflow">case</span> ARM::VST2d16wb_fixed: <span class="keywordflow">return</span> ARM::VST2d16wb_register;
+<a name="l01583"></a>01583 <span class="keywordflow">case</span> ARM::VST2d32wb_fixed: <span class="keywordflow">return</span> ARM::VST2d32wb_register;
+<a name="l01584"></a>01584 <span class="keywordflow">case</span> ARM::VST2q8PseudoWB_fixed: <span class="keywordflow">return</span> ARM::VST2q8PseudoWB_register;
+<a name="l01585"></a>01585 <span class="keywordflow">case</span> ARM::VST2q16PseudoWB_fixed: <span class="keywordflow">return</span> ARM::VST2q16PseudoWB_register;
+<a name="l01586"></a>01586 <span class="keywordflow">case</span> ARM::VST2q32PseudoWB_fixed: <span class="keywordflow">return</span> ARM::VST2q32PseudoWB_register;
+<a name="l01587"></a>01587
+<a name="l01588"></a>01588 <span class="keywordflow">case</span> ARM::VLD2DUPd8wb_fixed: <span class="keywordflow">return</span> ARM::VLD2DUPd8wb_register;
+<a name="l01589"></a>01589 <span class="keywordflow">case</span> ARM::VLD2DUPd16wb_fixed: <span class="keywordflow">return</span> ARM::VLD2DUPd16wb_register;
+<a name="l01590"></a>01590 <span class="keywordflow">case</span> ARM::VLD2DUPd32wb_fixed: <span class="keywordflow">return</span> ARM::VLD2DUPd32wb_register;
+<a name="l01591"></a>01591 }
+<a name="l01592"></a>01592 <span class="keywordflow">return</span> Opc; <span class="comment">// If not one we handle, return it unchanged.</span>
+<a name="l01593"></a>01593 }
+<a name="l01594"></a>01594
+<a name="l01595"></a>01595 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectVLD(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> isUpdating, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l01596"></a>01596 <span class="keyword">const</span> uint16_t *DOpcodes,
+<a name="l01597"></a>01597 <span class="keyword">const</span> uint16_t *QOpcodes0,
+<a name="l01598"></a>01598 <span class="keyword">const</span> uint16_t *QOpcodes1) {
+<a name="l01599"></a>01599 assert(NumVecs >= 1 && NumVecs <= 4 && <span class="stringliteral">"VLD NumVecs out-of-range"</span>);
+<a name="l01600"></a>01600 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01601"></a>01601
+<a name="l01602"></a>01602 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MemAddr, Align;
+<a name="l01603"></a>01603 <span class="keywordtype">unsigned</span> AddrOpIdx = isUpdating ? 1 : 2;
+<a name="l01604"></a>01604 <span class="keywordflow">if</span> (!SelectAddrMode6(N, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(AddrOpIdx), MemAddr, Align))
+<a name="l01605"></a>01605 <span class="keywordflow">return</span> NULL;
+<a name="l01606"></a>01606
+<a name="l01607"></a>01607 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l01608"></a>01608 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l01609"></a>01609 <span class="keywordtype">bool</span> is64BitVector = VT.<a class="code" href="structllvm_1_1EVT.html#a2b1f43f2f2563290b65f7e7e6bb71b0b" title="is64BitVector - Return true if this is a 64-bit vector type.">is64BitVector</a>();
+<a name="l01610"></a>01610 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
+<a name="l01611"></a>01611
+<a name="l01612"></a>01612 <span class="keywordtype">unsigned</span> OpcodeIndex;
+<a name="l01613"></a>01613 <span class="keywordflow">switch</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l01614"></a>01614 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"unhandled vld type"</span>);
+<a name="l01615"></a>01615 <span class="comment">// Double-register operations:</span>
+<a name="l01616"></a>01616 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca31f0af1863185f14e91278f7d567ae81">MVT::v8i8</a>: OpcodeIndex = 0; <span class="keywordflow">break</span>;
+<a name="l01617"></a>01617 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca9b846c126ddfbe57601a050653a45bd3">MVT::v4i16</a>: OpcodeIndex = 1; <span class="keywordflow">break</span>;
+<a name="l01618"></a>01618 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0bc51b0308b6c057dc86d2a6bf4b6573">MVT::v2f32</a>:
+<a name="l01619"></a>01619 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca5782b71c5eafe937e8d31d7b62497d99">MVT::v2i32</a>: OpcodeIndex = 2; <span class="keywordflow">break</span>;
+<a name="l01620"></a>01620 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf1e053801285fc066af033c62980eb33">MVT::v1i64</a>: OpcodeIndex = 3; <span class="keywordflow">break</span>;
+<a name="l01621"></a>01621 <span class="comment">// Quad-register operations:</span>
+<a name="l01622"></a>01622 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>: OpcodeIndex = 0; <span class="keywordflow">break</span>;
+<a name="l01623"></a>01623 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>: OpcodeIndex = 1; <span class="keywordflow">break</span>;
+<a name="l01624"></a>01624 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l01625"></a>01625 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>: OpcodeIndex = 2; <span class="keywordflow">break</span>;
+<a name="l01626"></a>01626 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0f87637b0102ab8e9f085bf80358fabc">MVT::v2i64</a>: OpcodeIndex = 3;
+<a name="l01627"></a>01627 assert(NumVecs == 1 && <span class="stringliteral">"v2i64 type only supported for VLD1"</span>);
+<a name="l01628"></a>01628 <span class="keywordflow">break</span>;
+<a name="l01629"></a>01629 }
+<a name="l01630"></a>01630
+<a name="l01631"></a>01631 <a class="code" href="structllvm_1_1EVT.html">EVT</a> ResTy;
+<a name="l01632"></a>01632 <span class="keywordflow">if</span> (NumVecs == 1)
+<a name="l01633"></a>01633 ResTy = VT;
+<a name="l01634"></a>01634 <span class="keywordflow">else</span> {
+<a name="l01635"></a>01635 <span class="keywordtype">unsigned</span> ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
+<a name="l01636"></a>01636 <span class="keywordflow">if</span> (!is64BitVector)
+<a name="l01637"></a>01637 ResTyElts *= 2;
+<a name="l01638"></a>01638 ResTy = <a class="code" href="structllvm_1_1EVT.html#a18c2edf1939f6e87f1e586b815f398cd">EVT::getVectorVT</a>(*CurDAG->getContext(), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, ResTyElts);
+<a name="l01639"></a>01639 }
+<a name="l01640"></a>01640 std::vector<EVT> ResTys;
+<a name="l01641"></a>01641 ResTys.push_back(ResTy);
+<a name="l01642"></a>01642 <span class="keywordflow">if</span> (isUpdating)
+<a name="l01643"></a>01643 ResTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01644"></a>01644 ResTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>);
+<a name="l01645"></a>01645
+<a name="l01646"></a>01646 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred = <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG);
+<a name="l01647"></a>01647 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Reg0 = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01648"></a>01648 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *VLd;
+<a name="l01649"></a>01649 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 7></a> Ops;
+<a name="l01650"></a>01650
+<a name="l01651"></a>01651 <span class="comment">// Double registers and VLD1/VLD2 quad registers are directly supported.</span>
+<a name="l01652"></a>01652 <span class="keywordflow">if</span> (is64BitVector || NumVecs <= 2) {
+<a name="l01653"></a>01653 <span class="keywordtype">unsigned</span> Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
+<a name="l01654"></a>01654 QOpcodes0[OpcodeIndex]);
+<a name="l01655"></a>01655 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(MemAddr);
+<a name="l01656"></a>01656 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Align);
+<a name="l01657"></a>01657 <span class="keywordflow">if</span> (isUpdating) {
+<a name="l01658"></a>01658 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Inc = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(AddrOpIdx + 1);
+<a name="l01659"></a>01659 <span class="comment">// FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0</span>
+<a name="l01660"></a>01660 <span class="comment">// case entirely when the rest are updated to that form, too.</span>
+<a name="l01661"></a>01661 <span class="keywordflow">if</span> ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()))
+<a name="l01662"></a>01662 Opc = <a class="code" href="ARMISelDAGToDAG_8cpp.html#a3b274201fdc7fbf1fc5f91a661b9410f">getVLDSTRegisterUpdateOpcode</a>(Opc);
+<a name="l01663"></a>01663 <span class="comment">// We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so</span>
+<a name="l01664"></a>01664 <span class="comment">// check for that explicitly too. Horribly hacky, but temporary.</span>
+<a name="l01665"></a>01665 <span class="keywordflow">if</span> ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
+<a name="l01666"></a>01666 !isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()))
+<a name="l01667"></a>01667 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()) ? Reg0 : Inc);
+<a name="l01668"></a>01668 }
+<a name="l01669"></a>01669 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Pred);
+<a name="l01670"></a>01670 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l01671"></a>01671 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l01672"></a>01672 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l01673"></a>01673
+<a name="l01674"></a>01674 } <span class="keywordflow">else</span> {
+<a name="l01675"></a>01675 <span class="comment">// Otherwise, quad registers are loaded with two separate instructions,</span>
+<a name="l01676"></a>01676 <span class="comment">// where one loads the even registers and the other loads the odd registers.</span>
+<a name="l01677"></a>01677 <a class="code" href="structllvm_1_1EVT.html">EVT</a> AddrTy = MemAddr.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01678"></a>01678
+<a name="l01679"></a>01679 <span class="comment">// Load the even subregs. This is always an updating load, so that it</span>
+<a name="l01680"></a>01680 <span class="comment">// provides the address to the second load for the odd subregs.</span>
+<a name="l01681"></a>01681 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ImplDef =
+<a name="l01682"></a>01682 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaa5a91c23866687baf221ce86ff6fde01f" title="IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.">TargetOpcode::IMPLICIT_DEF</a>, dl, ResTy), 0);
+<a name="l01683"></a>01683 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
+<a name="l01684"></a>01684 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
+<a name="l01685"></a>01685 ResTy, AddrTy, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, OpsA, 7);
+<a name="l01686"></a>01686 Chain = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdA, 2);
+<a name="l01687"></a>01687
+<a name="l01688"></a>01688 <span class="comment">// Load the odd subregs.</span>
+<a name="l01689"></a>01689 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdA, 1));
+<a name="l01690"></a>01690 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Align);
+<a name="l01691"></a>01691 <span class="keywordflow">if</span> (isUpdating) {
+<a name="l01692"></a>01692 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Inc = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(AddrOpIdx + 1);
+<a name="l01693"></a>01693 assert(isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()) &&
+<a name="l01694"></a>01694 <span class="stringliteral">"only constant post-increment update allowed for VLD3/4"</span>);
+<a name="l01695"></a>01695 (void)Inc;
+<a name="l01696"></a>01696 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l01697"></a>01697 }
+<a name="l01698"></a>01698 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdA, 0));
+<a name="l01699"></a>01699 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Pred);
+<a name="l01700"></a>01700 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l01701"></a>01701 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l01702"></a>01702 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
+<a name="l01703"></a>01703 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l01704"></a>01704 }
+<a name="l01705"></a>01705
+<a name="l01706"></a>01706 <span class="comment">// Transfer memoperands.</span>
+<a name="l01707"></a>01707 <a class="code" href="classllvm_1_1MachineMemOperand.html">MachineSDNode::mmo_iterator</a> MemOp = MF->allocateMemRefsArray(1);
+<a name="l01708"></a>01708 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+<a name="l01709"></a>01709 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
+<a name="l01710"></a>01710
+<a name="l01711"></a>01711 <span class="keywordflow">if</span> (NumVecs == 1)
+<a name="l01712"></a>01712 <span class="keywordflow">return</span> VLd;
+<a name="l01713"></a>01713
+<a name="l01714"></a>01714 <span class="comment">// Extract out the subregisters.</span>
+<a name="l01715"></a>01715 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SuperReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLd, 0);
+<a name="l01716"></a>01716 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
+<a name="l01717"></a>01717 ARM::qsub_3 == ARM::qsub_0+3 && <span class="stringliteral">"Unexpected subreg numbering"</span>);
+<a name="l01718"></a>01718 <span class="keywordtype">unsigned</span> Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
+<a name="l01719"></a>01719 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> Vec = 0; Vec < NumVecs; ++Vec)
+<a name="l01720"></a>01720 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, Vec),
+<a name="l01721"></a>01721 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
+<a name="l01722"></a>01722 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, NumVecs), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLd, 1));
+<a name="l01723"></a>01723 <span class="keywordflow">if</span> (isUpdating)
+<a name="l01724"></a>01724 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, NumVecs + 1), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLd, 2));
+<a name="l01725"></a>01725 <span class="keywordflow">return</span> NULL;
+<a name="l01726"></a>01726 }
+<a name="l01727"></a>01727
+<a name="l01728"></a>01728 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectVST(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> isUpdating, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l01729"></a>01729 <span class="keyword">const</span> uint16_t *DOpcodes,
+<a name="l01730"></a>01730 <span class="keyword">const</span> uint16_t *QOpcodes0,
+<a name="l01731"></a>01731 <span class="keyword">const</span> uint16_t *QOpcodes1) {
+<a name="l01732"></a>01732 assert(NumVecs >= 1 && NumVecs <= 4 && <span class="stringliteral">"VST NumVecs out-of-range"</span>);
+<a name="l01733"></a>01733 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01734"></a>01734
+<a name="l01735"></a>01735 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MemAddr, Align;
+<a name="l01736"></a>01736 <span class="keywordtype">unsigned</span> AddrOpIdx = isUpdating ? 1 : 2;
+<a name="l01737"></a>01737 <span class="keywordtype">unsigned</span> Vec0Idx = 3; <span class="comment">// AddrOpIdx + (isUpdating ? 2 : 1)</span>
+<a name="l01738"></a>01738 <span class="keywordflow">if</span> (!SelectAddrMode6(N, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(AddrOpIdx), MemAddr, Align))
+<a name="l01739"></a>01739 <span class="keywordflow">return</span> NULL;
+<a name="l01740"></a>01740
+<a name="l01741"></a>01741 <a class="code" href="classllvm_1_1MachineMemOperand.html">MachineSDNode::mmo_iterator</a> MemOp = MF->allocateMemRefsArray(1);
+<a name="l01742"></a>01742 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+<a name="l01743"></a>01743
+<a name="l01744"></a>01744 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l01745"></a>01745 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01746"></a>01746 <span class="keywordtype">bool</span> is64BitVector = VT.<a class="code" href="structllvm_1_1EVT.html#a2b1f43f2f2563290b65f7e7e6bb71b0b" title="is64BitVector - Return true if this is a 64-bit vector type.">is64BitVector</a>();
+<a name="l01747"></a>01747 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
+<a name="l01748"></a>01748
+<a name="l01749"></a>01749 <span class="keywordtype">unsigned</span> OpcodeIndex;
+<a name="l01750"></a>01750 <span class="keywordflow">switch</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l01751"></a>01751 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"unhandled vst type"</span>);
+<a name="l01752"></a>01752 <span class="comment">// Double-register operations:</span>
+<a name="l01753"></a>01753 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca31f0af1863185f14e91278f7d567ae81">MVT::v8i8</a>: OpcodeIndex = 0; <span class="keywordflow">break</span>;
+<a name="l01754"></a>01754 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca9b846c126ddfbe57601a050653a45bd3">MVT::v4i16</a>: OpcodeIndex = 1; <span class="keywordflow">break</span>;
+<a name="l01755"></a>01755 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0bc51b0308b6c057dc86d2a6bf4b6573">MVT::v2f32</a>:
+<a name="l01756"></a>01756 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca5782b71c5eafe937e8d31d7b62497d99">MVT::v2i32</a>: OpcodeIndex = 2; <span class="keywordflow">break</span>;
+<a name="l01757"></a>01757 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50caf1e053801285fc066af033c62980eb33">MVT::v1i64</a>: OpcodeIndex = 3; <span class="keywordflow">break</span>;
+<a name="l01758"></a>01758 <span class="comment">// Quad-register operations:</span>
+<a name="l01759"></a>01759 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>: OpcodeIndex = 0; <span class="keywordflow">break</span>;
+<a name="l01760"></a>01760 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>: OpcodeIndex = 1; <span class="keywordflow">break</span>;
+<a name="l01761"></a>01761 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l01762"></a>01762 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>: OpcodeIndex = 2; <span class="keywordflow">break</span>;
+<a name="l01763"></a>01763 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0f87637b0102ab8e9f085bf80358fabc">MVT::v2i64</a>: OpcodeIndex = 3;
+<a name="l01764"></a>01764 assert(NumVecs == 1 && <span class="stringliteral">"v2i64 type only supported for VST1"</span>);
+<a name="l01765"></a>01765 <span class="keywordflow">break</span>;
+<a name="l01766"></a>01766 }
+<a name="l01767"></a>01767
+<a name="l01768"></a>01768 std::vector<EVT> ResTys;
+<a name="l01769"></a>01769 <span class="keywordflow">if</span> (isUpdating)
+<a name="l01770"></a>01770 ResTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01771"></a>01771 ResTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>);
+<a name="l01772"></a>01772
+<a name="l01773"></a>01773 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred = <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG);
+<a name="l01774"></a>01774 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Reg0 = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01775"></a>01775 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 7></a> Ops;
+<a name="l01776"></a>01776
+<a name="l01777"></a>01777 <span class="comment">// Double registers and VST1/VST2 quad registers are directly supported.</span>
+<a name="l01778"></a>01778 <span class="keywordflow">if</span> (is64BitVector || NumVecs <= 2) {
+<a name="l01779"></a>01779 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SrcReg;
+<a name="l01780"></a>01780 <span class="keywordflow">if</span> (NumVecs == 1) {
+<a name="l01781"></a>01781 SrcReg = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx);
+<a name="l01782"></a>01782 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (is64BitVector) {
+<a name="l01783"></a>01783 <span class="comment">// Form a REG_SEQUENCE to force register allocation.</span>
+<a name="l01784"></a>01784 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 0);
+<a name="l01785"></a>01785 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 1);
+<a name="l01786"></a>01786 <span class="keywordflow">if</span> (NumVecs == 2)
+<a name="l01787"></a>01787 SrcReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(PairDRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0f87637b0102ab8e9f085bf80358fabc">MVT::v2i64</a>, V0, V1), 0);
+<a name="l01788"></a>01788 <span class="keywordflow">else</span> {
+<a name="l01789"></a>01789 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V2 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 2);
+<a name="l01790"></a>01790 <span class="comment">// If it's a vst3, form a quad D-register and leave the last part as</span>
+<a name="l01791"></a>01791 <span class="comment">// an undef.</span>
+<a name="l01792"></a>01792 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3 = (NumVecs == 3)
+<a name="l01793"></a>01793 ? <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaa5a91c23866687baf221ce86ff6fde01f" title="IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.">TargetOpcode::IMPLICIT_DEF</a>,dl,VT), 0)
+<a name="l01794"></a>01794 : N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 3);
+<a name="l01795"></a>01795 SrcReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(QuadDRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca16a8c1f04762886c0a57a4d8b4500db1">MVT::v4i64</a>, V0, V1, V2, V3), 0);
+<a name="l01796"></a>01796 }
+<a name="l01797"></a>01797 } <span class="keywordflow">else</span> {
+<a name="l01798"></a>01798 <span class="comment">// Form a QQ register.</span>
+<a name="l01799"></a>01799 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Q0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx);
+<a name="l01800"></a>01800 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Q1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 1);
+<a name="l01801"></a>01801 SrcReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(PairQRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca16a8c1f04762886c0a57a4d8b4500db1">MVT::v4i64</a>, Q0, Q1), 0);
+<a name="l01802"></a>01802 }
+<a name="l01803"></a>01803
+<a name="l01804"></a>01804 <span class="keywordtype">unsigned</span> Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
+<a name="l01805"></a>01805 QOpcodes0[OpcodeIndex]);
+<a name="l01806"></a>01806 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(MemAddr);
+<a name="l01807"></a>01807 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Align);
+<a name="l01808"></a>01808 <span class="keywordflow">if</span> (isUpdating) {
+<a name="l01809"></a>01809 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Inc = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(AddrOpIdx + 1);
+<a name="l01810"></a>01810 <span class="comment">// FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0</span>
+<a name="l01811"></a>01811 <span class="comment">// case entirely when the rest are updated to that form, too.</span>
+<a name="l01812"></a>01812 <span class="keywordflow">if</span> (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()))
+<a name="l01813"></a>01813 Opc = <a class="code" href="ARMISelDAGToDAG_8cpp.html#a3b274201fdc7fbf1fc5f91a661b9410f">getVLDSTRegisterUpdateOpcode</a>(Opc);
+<a name="l01814"></a>01814 <span class="comment">// We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so</span>
+<a name="l01815"></a>01815 <span class="comment">// check for that explicitly too. Horribly hacky, but temporary.</span>
+<a name="l01816"></a>01816 <span class="keywordflow">if</span> ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
+<a name="l01817"></a>01817 !isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()))
+<a name="l01818"></a>01818 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()) ? Reg0 : Inc);
+<a name="l01819"></a>01819 }
+<a name="l01820"></a>01820 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(SrcReg);
+<a name="l01821"></a>01821 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Pred);
+<a name="l01822"></a>01822 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l01823"></a>01823 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l01824"></a>01824 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *VSt =
+<a name="l01825"></a>01825 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l01826"></a>01826
+<a name="l01827"></a>01827 <span class="comment">// Transfer memoperands.</span>
+<a name="l01828"></a>01828 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
+<a name="l01829"></a>01829
+<a name="l01830"></a>01830 <span class="keywordflow">return</span> VSt;
+<a name="l01831"></a>01831 }
+<a name="l01832"></a>01832
+<a name="l01833"></a>01833 <span class="comment">// Otherwise, quad registers are stored with two separate instructions,</span>
+<a name="l01834"></a>01834 <span class="comment">// where one stores the even registers and the other stores the odd registers.</span>
+<a name="l01835"></a>01835
+<a name="l01836"></a>01836 <span class="comment">// Form the QQQQ REG_SEQUENCE.</span>
+<a name="l01837"></a>01837 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 0);
+<a name="l01838"></a>01838 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 1);
+<a name="l01839"></a>01839 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V2 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 2);
+<a name="l01840"></a>01840 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3 = (NumVecs == 3)
+<a name="l01841"></a>01841 ? <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaa5a91c23866687baf221ce86ff6fde01f" title="IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.">TargetOpcode::IMPLICIT_DEF</a>, dl, VT), 0)
+<a name="l01842"></a>01842 : N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 3);
+<a name="l01843"></a>01843 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegSeq = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(QuadQRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4c5a8a44331ca7bfa1400a74affc0d89">MVT::v8i64</a>, V0, V1, V2, V3), 0);
+<a name="l01844"></a>01844
+<a name="l01845"></a>01845 <span class="comment">// Store the even D registers. This is always an updating store, so that it</span>
+<a name="l01846"></a>01846 <span class="comment">// provides the address to the second store for the odd subregs.</span>
+<a name="l01847"></a>01847 <span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
+<a name="l01848"></a>01848 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
+<a name="l01849"></a>01849 MemAddr.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>(),
+<a name="l01850"></a>01850 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>, OpsA, 7);
+<a name="l01851"></a>01851 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
+<a name="l01852"></a>01852 Chain = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VStA, 1);
+<a name="l01853"></a>01853
+<a name="l01854"></a>01854 <span class="comment">// Store the odd D registers.</span>
+<a name="l01855"></a>01855 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VStA, 0));
+<a name="l01856"></a>01856 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Align);
+<a name="l01857"></a>01857 <span class="keywordflow">if</span> (isUpdating) {
+<a name="l01858"></a>01858 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Inc = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(AddrOpIdx + 1);
+<a name="l01859"></a>01859 assert(isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()) &&
+<a name="l01860"></a>01860 <span class="stringliteral">"only constant post-increment update allowed for VST3/4"</span>);
+<a name="l01861"></a>01861 (void)Inc;
+<a name="l01862"></a>01862 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l01863"></a>01863 }
+<a name="l01864"></a>01864 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(RegSeq);
+<a name="l01865"></a>01865 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Pred);
+<a name="l01866"></a>01866 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l01867"></a>01867 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l01868"></a>01868 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
+<a name="l01869"></a>01869 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l01870"></a>01870 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
+<a name="l01871"></a>01871 <span class="keywordflow">return</span> VStB;
+<a name="l01872"></a>01872 }
+<a name="l01873"></a>01873
+<a name="l01874"></a>01874 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectVLDSTLane(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> IsLoad,
+<a name="l01875"></a>01875 <span class="keywordtype">bool</span> isUpdating, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l01876"></a>01876 <span class="keyword">const</span> uint16_t *DOpcodes,
+<a name="l01877"></a>01877 <span class="keyword">const</span> uint16_t *QOpcodes) {
+<a name="l01878"></a>01878 assert(NumVecs >=2 && NumVecs <= 4 && <span class="stringliteral">"VLDSTLane NumVecs out-of-range"</span>);
+<a name="l01879"></a>01879 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01880"></a>01880
+<a name="l01881"></a>01881 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MemAddr, Align;
+<a name="l01882"></a>01882 <span class="keywordtype">unsigned</span> AddrOpIdx = isUpdating ? 1 : 2;
+<a name="l01883"></a>01883 <span class="keywordtype">unsigned</span> Vec0Idx = 3; <span class="comment">// AddrOpIdx + (isUpdating ? 2 : 1)</span>
+<a name="l01884"></a>01884 <span class="keywordflow">if</span> (!SelectAddrMode6(N, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(AddrOpIdx), MemAddr, Align))
+<a name="l01885"></a>01885 <span class="keywordflow">return</span> NULL;
+<a name="l01886"></a>01886
+<a name="l01887"></a>01887 <a class="code" href="classllvm_1_1MachineMemOperand.html">MachineSDNode::mmo_iterator</a> MemOp = MF->allocateMemRefsArray(1);
+<a name="l01888"></a>01888 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+<a name="l01889"></a>01889
+<a name="l01890"></a>01890 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l01891"></a>01891 <span class="keywordtype">unsigned</span> Lane =
+<a name="l01892"></a>01892 cast<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + NumVecs))->getZExtValue();
+<a name="l01893"></a>01893 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx).<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l01894"></a>01894 <span class="keywordtype">bool</span> is64BitVector = VT.<a class="code" href="structllvm_1_1EVT.html#a2b1f43f2f2563290b65f7e7e6bb71b0b" title="is64BitVector - Return true if this is a 64-bit vector type.">is64BitVector</a>();
+<a name="l01895"></a>01895
+<a name="l01896"></a>01896 <span class="keywordtype">unsigned</span> Alignment = 0;
+<a name="l01897"></a>01897 <span class="keywordflow">if</span> (NumVecs != 3) {
+<a name="l01898"></a>01898 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
+<a name="l01899"></a>01899 <span class="keywordtype">unsigned</span> NumBytes = NumVecs * VT.<a class="code" href="structllvm_1_1EVT.html#a3a07c062cc9330acd8e8c4e3930cbb25">getVectorElementType</a>().<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8;
+<a name="l01900"></a>01900 <span class="keywordflow">if</span> (Alignment > NumBytes)
+<a name="l01901"></a>01901 Alignment = NumBytes;
+<a name="l01902"></a>01902 <span class="keywordflow">if</span> (Alignment < 8 && Alignment < NumBytes)
+<a name="l01903"></a>01903 Alignment = 0;
+<a name="l01904"></a>01904 <span class="comment">// Alignment must be a power of two; make sure of that.</span>
+<a name="l01905"></a>01905 Alignment = (Alignment & -Alignment);
+<a name="l01906"></a>01906 <span class="keywordflow">if</span> (Alignment == 1)
+<a name="l01907"></a>01907 Alignment = 0;
+<a name="l01908"></a>01908 }
+<a name="l01909"></a>01909 Align = CurDAG->getTargetConstant(Alignment, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01910"></a>01910
+<a name="l01911"></a>01911 <span class="keywordtype">unsigned</span> OpcodeIndex;
+<a name="l01912"></a>01912 <span class="keywordflow">switch</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l01913"></a>01913 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"unhandled vld/vst lane type"</span>);
+<a name="l01914"></a>01914 <span class="comment">// Double-register operations:</span>
+<a name="l01915"></a>01915 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca31f0af1863185f14e91278f7d567ae81">MVT::v8i8</a>: OpcodeIndex = 0; <span class="keywordflow">break</span>;
+<a name="l01916"></a>01916 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca9b846c126ddfbe57601a050653a45bd3">MVT::v4i16</a>: OpcodeIndex = 1; <span class="keywordflow">break</span>;
+<a name="l01917"></a>01917 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0bc51b0308b6c057dc86d2a6bf4b6573">MVT::v2f32</a>:
+<a name="l01918"></a>01918 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca5782b71c5eafe937e8d31d7b62497d99">MVT::v2i32</a>: OpcodeIndex = 2; <span class="keywordflow">break</span>;
+<a name="l01919"></a>01919 <span class="comment">// Quad-register operations:</span>
+<a name="l01920"></a>01920 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>: OpcodeIndex = 0; <span class="keywordflow">break</span>;
+<a name="l01921"></a>01921 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l01922"></a>01922 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>: OpcodeIndex = 1; <span class="keywordflow">break</span>;
+<a name="l01923"></a>01923 }
+<a name="l01924"></a>01924
+<a name="l01925"></a>01925 std::vector<EVT> ResTys;
+<a name="l01926"></a>01926 <span class="keywordflow">if</span> (IsLoad) {
+<a name="l01927"></a>01927 <span class="keywordtype">unsigned</span> ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
+<a name="l01928"></a>01928 <span class="keywordflow">if</span> (!is64BitVector)
+<a name="l01929"></a>01929 ResTyElts *= 2;
+<a name="l01930"></a>01930 ResTys.push_back(<a class="code" href="structllvm_1_1EVT.html#a18c2edf1939f6e87f1e586b815f398cd">EVT::getVectorVT</a>(*CurDAG->getContext(),
+<a name="l01931"></a>01931 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>, ResTyElts));
+<a name="l01932"></a>01932 }
+<a name="l01933"></a>01933 <span class="keywordflow">if</span> (isUpdating)
+<a name="l01934"></a>01934 ResTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01935"></a>01935 ResTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>);
+<a name="l01936"></a>01936
+<a name="l01937"></a>01937 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred = <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG);
+<a name="l01938"></a>01938 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Reg0 = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l01939"></a>01939
+<a name="l01940"></a>01940 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 8></a> Ops;
+<a name="l01941"></a>01941 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(MemAddr);
+<a name="l01942"></a>01942 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Align);
+<a name="l01943"></a>01943 <span class="keywordflow">if</span> (isUpdating) {
+<a name="l01944"></a>01944 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Inc = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(AddrOpIdx + 1);
+<a name="l01945"></a>01945 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()) ? Reg0 : Inc);
+<a name="l01946"></a>01946 }
+<a name="l01947"></a>01947
+<a name="l01948"></a>01948 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SuperReg;
+<a name="l01949"></a>01949 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 0);
+<a name="l01950"></a>01950 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 1);
+<a name="l01951"></a>01951 <span class="keywordflow">if</span> (NumVecs == 2) {
+<a name="l01952"></a>01952 <span class="keywordflow">if</span> (is64BitVector)
+<a name="l01953"></a>01953 SuperReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(PairDRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0f87637b0102ab8e9f085bf80358fabc">MVT::v2i64</a>, V0, V1), 0);
+<a name="l01954"></a>01954 <span class="keywordflow">else</span>
+<a name="l01955"></a>01955 SuperReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(PairQRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca16a8c1f04762886c0a57a4d8b4500db1">MVT::v4i64</a>, V0, V1), 0);
+<a name="l01956"></a>01956 } <span class="keywordflow">else</span> {
+<a name="l01957"></a>01957 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V2 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 2);
+<a name="l01958"></a>01958 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3 = (NumVecs == 3)
+<a name="l01959"></a>01959 ? <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaa5a91c23866687baf221ce86ff6fde01f" title="IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.">TargetOpcode::IMPLICIT_DEF</a>, dl, VT), 0)
+<a name="l01960"></a>01960 : N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(Vec0Idx + 3);
+<a name="l01961"></a>01961 <span class="keywordflow">if</span> (is64BitVector)
+<a name="l01962"></a>01962 SuperReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(QuadDRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca16a8c1f04762886c0a57a4d8b4500db1">MVT::v4i64</a>, V0, V1, V2, V3), 0);
+<a name="l01963"></a>01963 <span class="keywordflow">else</span>
+<a name="l01964"></a>01964 SuperReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(QuadQRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4c5a8a44331ca7bfa1400a74affc0d89">MVT::v8i64</a>, V0, V1, V2, V3), 0);
+<a name="l01965"></a>01965 }
+<a name="l01966"></a>01966 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(SuperReg);
+<a name="l01967"></a>01967 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(getI32Imm(Lane));
+<a name="l01968"></a>01968 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Pred);
+<a name="l01969"></a>01969 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l01970"></a>01970 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l01971"></a>01971
+<a name="l01972"></a>01972 <span class="keywordtype">unsigned</span> Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
+<a name="l01973"></a>01973 QOpcodes[OpcodeIndex]);
+<a name="l01974"></a>01974 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
+<a name="l01975"></a>01975 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l01976"></a>01976 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
+<a name="l01977"></a>01977 <span class="keywordflow">if</span> (!IsLoad)
+<a name="l01978"></a>01978 <span class="keywordflow">return</span> VLdLn;
+<a name="l01979"></a>01979
+<a name="l01980"></a>01980 <span class="comment">// Extract the subregisters.</span>
+<a name="l01981"></a>01981 SuperReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdLn, 0);
+<a name="l01982"></a>01982 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
+<a name="l01983"></a>01983 ARM::qsub_3 == ARM::qsub_0+3 && <span class="stringliteral">"Unexpected subreg numbering"</span>);
+<a name="l01984"></a>01984 <span class="keywordtype">unsigned</span> Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
+<a name="l01985"></a>01985 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> Vec = 0; Vec < NumVecs; ++Vec)
+<a name="l01986"></a>01986 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, Vec),
+<a name="l01987"></a>01987 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
+<a name="l01988"></a>01988 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, NumVecs), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdLn, 1));
+<a name="l01989"></a>01989 <span class="keywordflow">if</span> (isUpdating)
+<a name="l01990"></a>01990 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, NumVecs + 1), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdLn, 2));
+<a name="l01991"></a>01991 <span class="keywordflow">return</span> NULL;
+<a name="l01992"></a>01992 }
+<a name="l01993"></a>01993
+<a name="l01994"></a>01994 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectVLDDup(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> isUpdating,
+<a name="l01995"></a>01995 <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l01996"></a>01996 <span class="keyword">const</span> uint16_t *Opcodes) {
+<a name="l01997"></a>01997 assert(NumVecs >=2 && NumVecs <= 4 && <span class="stringliteral">"VLDDup NumVecs out-of-range"</span>);
+<a name="l01998"></a>01998 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l01999"></a>01999
+<a name="l02000"></a>02000 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MemAddr, Align;
+<a name="l02001"></a>02001 <span class="keywordflow">if</span> (!SelectAddrMode6(N, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), MemAddr, Align))
+<a name="l02002"></a>02002 <span class="keywordflow">return</span> NULL;
+<a name="l02003"></a>02003
+<a name="l02004"></a>02004 <a class="code" href="classllvm_1_1MachineMemOperand.html">MachineSDNode::mmo_iterator</a> MemOp = MF->allocateMemRefsArray(1);
+<a name="l02005"></a>02005 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+<a name="l02006"></a>02006
+<a name="l02007"></a>02007 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l02008"></a>02008 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02009"></a>02009
+<a name="l02010"></a>02010 <span class="keywordtype">unsigned</span> Alignment = 0;
+<a name="l02011"></a>02011 <span class="keywordflow">if</span> (NumVecs != 3) {
+<a name="l02012"></a>02012 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
+<a name="l02013"></a>02013 <span class="keywordtype">unsigned</span> NumBytes = NumVecs * VT.<a class="code" href="structllvm_1_1EVT.html#a3a07c062cc9330acd8e8c4e3930cbb25">getVectorElementType</a>().<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>()/8;
+<a name="l02014"></a>02014 <span class="keywordflow">if</span> (Alignment > NumBytes)
+<a name="l02015"></a>02015 Alignment = NumBytes;
+<a name="l02016"></a>02016 <span class="keywordflow">if</span> (Alignment < 8 && Alignment < NumBytes)
+<a name="l02017"></a>02017 Alignment = 0;
+<a name="l02018"></a>02018 <span class="comment">// Alignment must be a power of two; make sure of that.</span>
+<a name="l02019"></a>02019 Alignment = (Alignment & -Alignment);
+<a name="l02020"></a>02020 <span class="keywordflow">if</span> (Alignment == 1)
+<a name="l02021"></a>02021 Alignment = 0;
+<a name="l02022"></a>02022 }
+<a name="l02023"></a>02023 Align = CurDAG->getTargetConstant(Alignment, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02024"></a>02024
+<a name="l02025"></a>02025 <span class="keywordtype">unsigned</span> OpcodeIndex;
+<a name="l02026"></a>02026 <span class="keywordflow">switch</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l02027"></a>02027 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"unhandled vld-dup type"</span>);
+<a name="l02028"></a>02028 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca31f0af1863185f14e91278f7d567ae81">MVT::v8i8</a>: OpcodeIndex = 0; <span class="keywordflow">break</span>;
+<a name="l02029"></a>02029 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca9b846c126ddfbe57601a050653a45bd3">MVT::v4i16</a>: OpcodeIndex = 1; <span class="keywordflow">break</span>;
+<a name="l02030"></a>02030 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0bc51b0308b6c057dc86d2a6bf4b6573">MVT::v2f32</a>:
+<a name="l02031"></a>02031 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca5782b71c5eafe937e8d31d7b62497d99">MVT::v2i32</a>: OpcodeIndex = 2; <span class="keywordflow">break</span>;
+<a name="l02032"></a>02032 }
+<a name="l02033"></a>02033
+<a name="l02034"></a>02034 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred = <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG);
+<a name="l02035"></a>02035 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Reg0 = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02036"></a>02036 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SuperReg;
+<a name="l02037"></a>02037 <span class="keywordtype">unsigned</span> Opc = Opcodes[OpcodeIndex];
+<a name="l02038"></a>02038 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 6></a> Ops;
+<a name="l02039"></a>02039 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(MemAddr);
+<a name="l02040"></a>02040 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Align);
+<a name="l02041"></a>02041 <span class="keywordflow">if</span> (isUpdating) {
+<a name="l02042"></a>02042 <span class="comment">// fixed-stride update instructions don't have an explicit writeback</span>
+<a name="l02043"></a>02043 <span class="comment">// operand. It's implicit in the opcode itself.</span>
+<a name="l02044"></a>02044 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Inc = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2);
+<a name="l02045"></a>02045 <span class="keywordflow">if</span> (!isa<ConstantSDNode>(Inc.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()))
+<a name="l02046"></a>02046 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Inc);
+<a name="l02047"></a>02047 <span class="comment">// FIXME: VLD3 and VLD4 haven't been updated to that form yet.</span>
+<a name="l02048"></a>02048 <span class="keywordflow">else</span> <span class="keywordflow">if</span> (NumVecs > 2)
+<a name="l02049"></a>02049 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l02050"></a>02050 }
+<a name="l02051"></a>02051 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Pred);
+<a name="l02052"></a>02052 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Reg0);
+<a name="l02053"></a>02053 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l02054"></a>02054
+<a name="l02055"></a>02055 <span class="keywordtype">unsigned</span> ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
+<a name="l02056"></a>02056 std::vector<EVT> ResTys;
+<a name="l02057"></a>02057 ResTys.push_back(<a class="code" href="structllvm_1_1EVT.html#a18c2edf1939f6e87f1e586b815f398cd">EVT::getVectorVT</a>(*CurDAG->getContext(), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97f56253625b3fe7b371ce76722de4b8">MVT::i64</a>,ResTyElts));
+<a name="l02058"></a>02058 <span class="keywordflow">if</span> (isUpdating)
+<a name="l02059"></a>02059 ResTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02060"></a>02060 ResTys.push_back(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>);
+<a name="l02061"></a>02061 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *VLdDup =
+<a name="l02062"></a>02062 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l02063"></a>02063 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
+<a name="l02064"></a>02064 SuperReg = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdDup, 0);
+<a name="l02065"></a>02065
+<a name="l02066"></a>02066 <span class="comment">// Extract the subregisters.</span>
+<a name="l02067"></a>02067 assert(ARM::dsub_7 == ARM::dsub_0+7 && <span class="stringliteral">"Unexpected subreg numbering"</span>);
+<a name="l02068"></a>02068 <span class="keywordtype">unsigned</span> SubIdx = ARM::dsub_0;
+<a name="l02069"></a>02069 <span class="keywordflow">for</span> (<span class="keywordtype">unsigned</span> Vec = 0; Vec < NumVecs; ++Vec)
+<a name="l02070"></a>02070 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, Vec),
+<a name="l02071"></a>02071 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
+<a name="l02072"></a>02072 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, NumVecs), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdDup, 1));
+<a name="l02073"></a>02073 <span class="keywordflow">if</span> (isUpdating)
+<a name="l02074"></a>02074 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, NumVecs + 1), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(VLdDup, 2));
+<a name="l02075"></a>02075 <span class="keywordflow">return</span> NULL;
+<a name="l02076"></a>02076 }
+<a name="l02077"></a>02077
+<a name="l02078"></a>02078 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectVTBL(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <span class="keywordtype">bool</span> IsExt, <span class="keywordtype">unsigned</span> NumVecs,
+<a name="l02079"></a>02079 <span class="keywordtype">unsigned</span> Opc) {
+<a name="l02080"></a>02080 assert(NumVecs >= 2 && NumVecs <= 4 && <span class="stringliteral">"VTBL NumVecs out-of-range"</span>);
+<a name="l02081"></a>02081 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l02082"></a>02082 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02083"></a>02083 <span class="keywordtype">unsigned</span> FirstTblReg = IsExt ? 2 : 1;
+<a name="l02084"></a>02084
+<a name="l02085"></a>02085 <span class="comment">// Form a REG_SEQUENCE to force register allocation.</span>
+<a name="l02086"></a>02086 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegSeq;
+<a name="l02087"></a>02087 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(FirstTblReg + 0);
+<a name="l02088"></a>02088 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(FirstTblReg + 1);
+<a name="l02089"></a>02089 <span class="keywordflow">if</span> (NumVecs == 2)
+<a name="l02090"></a>02090 RegSeq = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(PairDRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, V0, V1), 0);
+<a name="l02091"></a>02091 <span class="keywordflow">else</span> {
+<a name="l02092"></a>02092 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V2 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(FirstTblReg + 2);
+<a name="l02093"></a>02093 <span class="comment">// If it's a vtbl3, form a quad D-register and leave the last part as</span>
+<a name="l02094"></a>02094 <span class="comment">// an undef.</span>
+<a name="l02095"></a>02095 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V3 = (NumVecs == 3)
+<a name="l02096"></a>02096 ? <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1TargetOpcode.html#aa2b3629c9319f86eee5a2c0e8c75ebfaa5a91c23866687baf221ce86ff6fde01f" title="IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.">TargetOpcode::IMPLICIT_DEF</a>, dl, VT), 0)
+<a name="l02097"></a>02097 : N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(FirstTblReg + 3);
+<a name="l02098"></a>02098 RegSeq = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(QuadDRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca16a8c1f04762886c0a57a4d8b4500db1">MVT::v4i64</a>, V0, V1, V2, V3), 0);
+<a name="l02099"></a>02099 }
+<a name="l02100"></a>02100
+<a name="l02101"></a>02101 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 6></a> Ops;
+<a name="l02102"></a>02102 <span class="keywordflow">if</span> (IsExt)
+<a name="l02103"></a>02103 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1));
+<a name="l02104"></a>02104 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(RegSeq);
+<a name="l02105"></a>02105 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(FirstTblReg + NumVecs));
+<a name="l02106"></a>02106 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(<a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG)); <span class="comment">// predicate</span>
+<a name="l02107"></a>02107 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>)); <span class="comment">// predicate register</span>
+<a name="l02108"></a>02108 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opc, dl, VT, Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l02109"></a>02109 }
+<a name="l02110"></a>02110
+<a name="l02111"></a>02111 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N,
+<a name="l02112"></a>02112 <span class="keywordtype">bool</span> isSigned) {
+<a name="l02113"></a>02113 <span class="keywordflow">if</span> (!Subtarget->hasV6T2Ops())
+<a name="l02114"></a>02114 <span class="keywordflow">return</span> NULL;
+<a name="l02115"></a>02115
+<a name="l02116"></a>02116 <span class="keywordtype">unsigned</span> Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
+<a name="l02117"></a>02117 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
+<a name="l02118"></a>02118
+<a name="l02119"></a>02119
+<a name="l02120"></a>02120 <span class="comment">// For unsigned extracts, check for a shift right and mask</span>
+<a name="l02121"></a>02121 <span class="keywordtype">unsigned</span> And_imm = 0;
+<a name="l02122"></a>02122 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>) {
+<a name="l02123"></a>02123 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">isOpcWithIntImmediate</a>(N, <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>, And_imm)) {
+<a name="l02124"></a>02124
+<a name="l02125"></a>02125 <span class="comment">// The immediate is a mask of the low bits iff imm & (imm+1) == 0</span>
+<a name="l02126"></a>02126 <span class="keywordflow">if</span> (And_imm & (And_imm + 1))
+<a name="l02127"></a>02127 <span class="keywordflow">return</span> NULL;
+<a name="l02128"></a>02128
+<a name="l02129"></a>02129 <span class="keywordtype">unsigned</span> Srl_imm = 0;
+<a name="l02130"></a>02130 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">isOpcWithIntImmediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>,
+<a name="l02131"></a>02131 Srl_imm)) {
+<a name="l02132"></a>02132 assert(Srl_imm > 0 && Srl_imm < 32 && <span class="stringliteral">"bad amount in shift node!"</span>);
+<a name="l02133"></a>02133
+<a name="l02134"></a>02134 <span class="comment">// Note: The width operand is encoded as width-1.</span>
+<a name="l02135"></a>02135 <span class="keywordtype">unsigned</span> Width = <a class="code" href="namespacellvm.html#a2a37fef2c58b20b5884297b082eca44b">CountTrailingOnes_32</a>(And_imm) - 1;
+<a name="l02136"></a>02136 <span class="keywordtype">unsigned</span> LSB = Srl_imm;
+<a name="l02137"></a>02137 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Reg0 = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02138"></a>02138 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0),
+<a name="l02139"></a>02139 CurDAG->getTargetConstant(LSB, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>),
+<a name="l02140"></a>02140 CurDAG->getTargetConstant(Width, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>),
+<a name="l02141"></a>02141 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), Reg0 };
+<a name="l02142"></a>02142 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opc, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 5);
+<a name="l02143"></a>02143 }
+<a name="l02144"></a>02144 }
+<a name="l02145"></a>02145 <span class="keywordflow">return</span> NULL;
+<a name="l02146"></a>02146 }
+<a name="l02147"></a>02147
+<a name="l02148"></a>02148 <span class="comment">// Otherwise, we're looking for a shift of a shift</span>
+<a name="l02149"></a>02149 <span class="keywordtype">unsigned</span> Shl_imm = 0;
+<a name="l02150"></a>02150 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a5fa1cb1a1d96ce454ea9056f487d718e">isOpcWithIntImmediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8cc94e03dea594863073a02f5bb94997">ISD::SHL</a>, Shl_imm)) {
+<a name="l02151"></a>02151 assert(Shl_imm > 0 && Shl_imm < 32 && <span class="stringliteral">"bad amount in shift node!"</span>);
+<a name="l02152"></a>02152 <span class="keywordtype">unsigned</span> Srl_imm = 0;
+<a name="l02153"></a>02153 <span class="keywordflow">if</span> (<a class="code" href="ARMISelDAGToDAG_8cpp.html#a7c97deb23c9a669470b42d2bd2e99f19">isInt32Immediate</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Srl_imm)) {
+<a name="l02154"></a>02154 assert(Srl_imm > 0 && Srl_imm < 32 && <span class="stringliteral">"bad amount in shift node!"</span>);
+<a name="l02155"></a>02155 <span class="comment">// Note: The width operand is encoded as width-1.</span>
+<a name="l02156"></a>02156 <span class="keywordtype">unsigned</span> Width = 32 - Srl_imm - 1;
+<a name="l02157"></a>02157 <span class="keywordtype">int</span> LSB = Srl_imm - Shl_imm;
+<a name="l02158"></a>02158 <span class="keywordflow">if</span> (LSB < 0)
+<a name="l02159"></a>02159 <span class="keywordflow">return</span> NULL;
+<a name="l02160"></a>02160 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Reg0 = CurDAG->getRegister(0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02161"></a>02161 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0).<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0),
+<a name="l02162"></a>02162 CurDAG->getTargetConstant(LSB, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>),
+<a name="l02163"></a>02163 CurDAG->getTargetConstant(Width, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>),
+<a name="l02164"></a>02164 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), Reg0 };
+<a name="l02165"></a>02165 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opc, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 5);
+<a name="l02166"></a>02166 }
+<a name="l02167"></a>02167 }
+<a name="l02168"></a>02168 <span class="keywordflow">return</span> NULL;
+<a name="l02169"></a>02169 }
+<a name="l02170"></a>02170
+<a name="l02171"></a>02171 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::
+<a name="l02172"></a>02172 SelectT2CMOVShiftOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal,
+<a name="l02173"></a>02173 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag) {
+<a name="l02174"></a>02174 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CPTmp0;
+<a name="l02175"></a>02175 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CPTmp1;
+<a name="l02176"></a>02176 <span class="keywordflow">if</span> (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
+<a name="l02177"></a>02177 <span class="keywordtype">unsigned</span> SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
+<a name="l02178"></a>02178 <span class="keywordtype">unsigned</span> SOShOp = <a class="code" href="namespacellvm_1_1ARM__AM.html#a3c0892ca13564f7da976c5defe746fcf">ARM_AM::getSORegShOp</a>(SOVal);
+<a name="l02179"></a>02179 <span class="keywordtype">unsigned</span> Opc = 0;
+<a name="l02180"></a>02180 <span class="keywordflow">switch</span> (SOShOp) {
+<a name="l02181"></a>02181 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a>: Opc = ARM::t2MOVCClsl; <span class="keywordflow">break</span>;
+<a name="l02182"></a>02182 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa25f26a9f4d00c9ac425953111519c041">ARM_AM::lsr</a>: Opc = ARM::t2MOVCClsr; <span class="keywordflow">break</span>;
+<a name="l02183"></a>02183 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efa325f4baf722ab35ea203950c4e3c5e5a">ARM_AM::asr</a>: Opc = ARM::t2MOVCCasr; <span class="keywordflow">break</span>;
+<a name="l02184"></a>02184 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaf9bc4030b576764b9de7211577c98460">ARM_AM::ror</a>: Opc = ARM::t2MOVCCror; <span class="keywordflow">break</span>;
+<a name="l02185"></a>02185 <span class="keywordflow">default</span>:
+<a name="l02186"></a>02186 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Unknown so_reg opcode!"</span>);
+<a name="l02187"></a>02187 }
+<a name="l02188"></a>02188 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SOShImm =
+<a name="l02189"></a>02189 CurDAG->getTargetConstant(<a class="code" href="namespacellvm_1_1ARM__AM.html#a6c300abe1e4b9fda1a3eb6630eb99cd5">ARM_AM::getSORegOffset</a>(SOVal), <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02190"></a>02190 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a> = CurDAG->getTargetConstant(CCVal, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02191"></a>02191 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { FalseVal, CPTmp0, SOShImm, <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, CCR, InFlag };
+<a name="l02192"></a>02192 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opc, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>,Ops, 6);
+<a name="l02193"></a>02193 }
+<a name="l02194"></a>02194 <span class="keywordflow">return</span> 0;
+<a name="l02195"></a>02195 }
+<a name="l02196"></a>02196
+<a name="l02197"></a>02197 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::
+<a name="l02198"></a>02198 SelectARMCMOVShiftOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal,
+<a name="l02199"></a>02199 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag) {
+<a name="l02200"></a>02200 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CPTmp0;
+<a name="l02201"></a>02201 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CPTmp1;
+<a name="l02202"></a>02202 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CPTmp2;
+<a name="l02203"></a>02203 <span class="keywordflow">if</span> (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
+<a name="l02204"></a>02204 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CC = CurDAG->getTargetConstant(CCVal, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02205"></a>02205 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { FalseVal, CPTmp0, CPTmp2, <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, CCR, InFlag };
+<a name="l02206"></a>02206 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, ARM::MOVCCsi, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 6);
+<a name="l02207"></a>02207 }
+<a name="l02208"></a>02208
+<a name="l02209"></a>02209 <span class="keywordflow">if</span> (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
+<a name="l02210"></a>02210 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CC = CurDAG->getTargetConstant(CCVal, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02211"></a>02211 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, CCR, InFlag };
+<a name="l02212"></a>02212 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, ARM::MOVCCsr, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 7);
+<a name="l02213"></a>02213 }
+<a name="l02214"></a>02214 <span class="keywordflow">return</span> 0;
+<a name="l02215"></a>02215 }
+<a name="l02216"></a>02216
+<a name="l02217"></a>02217 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::
+<a name="l02218"></a>02218 SelectT2CMOVImmOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal,
+<a name="l02219"></a>02219 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag) {
+<a name="l02220"></a>02220 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *T = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(TrueVal);
+<a name="l02221"></a>02221 <span class="keywordflow">if</span> (!T)
+<a name="l02222"></a>02222 <span class="keywordflow">return</span> 0;
+<a name="l02223"></a>02223
+<a name="l02224"></a>02224 <span class="keywordtype">unsigned</span> Opc = 0;
+<a name="l02225"></a>02225 <span class="keywordtype">unsigned</span> TrueImm = T-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l02226"></a>02226 <span class="keywordflow">if</span> (is_t2_so_imm(TrueImm)) {
+<a name="l02227"></a>02227 Opc = ARM::t2MOVCCi;
+<a name="l02228"></a>02228 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (TrueImm <= 0xffff) {
+<a name="l02229"></a>02229 Opc = ARM::t2MOVCCi16;
+<a name="l02230"></a>02230 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (is_t2_so_imm_not(TrueImm)) {
+<a name="l02231"></a>02231 TrueImm = ~TrueImm;
+<a name="l02232"></a>02232 Opc = ARM::t2MVNCCi;
+<a name="l02233"></a>02233 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (TrueVal.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a52753947fce3a01b1c18dd4713c587e8">hasOneUse</a>() && Subtarget->hasV6T2Ops()) {
+<a name="l02234"></a>02234 <span class="comment">// Large immediate.</span>
+<a name="l02235"></a>02235 Opc = ARM::t2MOVCCi32imm;
+<a name="l02236"></a>02236 }
+<a name="l02237"></a>02237
+<a name="l02238"></a>02238 <span class="keywordflow">if</span> (Opc) {
+<a name="l02239"></a>02239 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> True = CurDAG->getTargetConstant(TrueImm, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02240"></a>02240 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CC = CurDAG->getTargetConstant(CCVal, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02241"></a>02241 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { FalseVal, True, <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, CCR, InFlag };
+<a name="l02242"></a>02242 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opc, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 5);
+<a name="l02243"></a>02243 }
+<a name="l02244"></a>02244
+<a name="l02245"></a>02245 <span class="keywordflow">return</span> 0;
+<a name="l02246"></a>02246 }
+<a name="l02247"></a>02247
+<a name="l02248"></a>02248 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::
+<a name="l02249"></a>02249 SelectARMCMOVImmOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal,
+<a name="l02250"></a>02250 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR, <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag) {
+<a name="l02251"></a>02251 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *T = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(TrueVal);
+<a name="l02252"></a>02252 <span class="keywordflow">if</span> (!T)
+<a name="l02253"></a>02253 <span class="keywordflow">return</span> 0;
+<a name="l02254"></a>02254
+<a name="l02255"></a>02255 <span class="keywordtype">unsigned</span> Opc = 0;
+<a name="l02256"></a>02256 <span class="keywordtype">unsigned</span> TrueImm = T-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l02257"></a>02257 <span class="keywordtype">bool</span> isSoImm = is_so_imm(TrueImm);
+<a name="l02258"></a>02258 <span class="keywordflow">if</span> (isSoImm) {
+<a name="l02259"></a>02259 Opc = ARM::MOVCCi;
+<a name="l02260"></a>02260 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
+<a name="l02261"></a>02261 Opc = ARM::MOVCCi16;
+<a name="l02262"></a>02262 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (is_so_imm_not(TrueImm)) {
+<a name="l02263"></a>02263 TrueImm = ~TrueImm;
+<a name="l02264"></a>02264 Opc = ARM::MVNCCi;
+<a name="l02265"></a>02265 } <span class="keywordflow">else</span> <span class="keywordflow">if</span> (TrueVal.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a52753947fce3a01b1c18dd4713c587e8">hasOneUse</a>() &&
+<a name="l02266"></a>02266 (Subtarget->hasV6T2Ops() || <a class="code" href="namespacellvm_1_1ARM__AM.html#ac229bc1c730b34dff4b13afbe7747e22">ARM_AM::isSOImmTwoPartVal</a>(TrueImm))) {
+<a name="l02267"></a>02267 <span class="comment">// Large immediate.</span>
+<a name="l02268"></a>02268 Opc = ARM::MOVCCi32imm;
+<a name="l02269"></a>02269 }
+<a name="l02270"></a>02270
+<a name="l02271"></a>02271 <span class="keywordflow">if</span> (Opc) {
+<a name="l02272"></a>02272 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> True = CurDAG->getTargetConstant(TrueImm, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02273"></a>02273 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CC = CurDAG->getTargetConstant(CCVal, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02274"></a>02274 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { FalseVal, True, <a class="code" href="namespacellvm_1_1MBlazeCC.html#aba42d64ed60fd2a2e8045b6d7f26958d">CC</a>, CCR, InFlag };
+<a name="l02275"></a>02275 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opc, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 5);
+<a name="l02276"></a>02276 }
+<a name="l02277"></a>02277
+<a name="l02278"></a>02278 <span class="keywordflow">return</span> 0;
+<a name="l02279"></a>02279 }
+<a name="l02280"></a>02280
+<a name="l02281"></a>02281 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectCMOVOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l02282"></a>02282 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02283"></a>02283 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> FalseVal = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l02284"></a>02284 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TrueVal = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l02285"></a>02285 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CC = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2);
+<a name="l02286"></a>02286 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CCR = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3);
+<a name="l02287"></a>02287 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(4);
+<a name="l02288"></a>02288 assert(CC.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a>);
+<a name="l02289"></a>02289 assert(CCR.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a419e8283a58d2b1b86591fa7f18ccfd9">ISD::Register</a>);
+<a name="l02290"></a>02290 <a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a> CCVal =
+<a name="l02291"></a>02291 (<a class="code" href="namespacellvm_1_1ARMCC.html#ac8391dd6b8083baa870dee5142ff22b6">ARMCC::CondCodes</a>)cast<ConstantSDNode>(CC)->getZExtValue();
+<a name="l02292"></a>02292
+<a name="l02293"></a>02293 <span class="keywordflow">if</span> (!Subtarget->isThumb1Only() && VT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>) {
+<a name="l02294"></a>02294 <span class="comment">// Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)</span>
+<a name="l02295"></a>02295 <span class="comment">// Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)</span>
+<a name="l02296"></a>02296 <span class="comment">// Pattern complexity = 18 cost = 1 size = 0</span>
+<a name="l02297"></a>02297 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02298"></a>02298 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
+<a name="l02299"></a>02299 CCVal, CCR, InFlag);
+<a name="l02300"></a>02300 <span class="keywordflow">if</span> (!Res)
+<a name="l02301"></a>02301 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
+<a name="l02302"></a>02302 <a class="code" href="namespacellvm_1_1ARMCC.html#a4bd63de978510703f28cd98ea7c0ffa5">ARMCC::getOppositeCondition</a>(CCVal), CCR, InFlag);
+<a name="l02303"></a>02303 <span class="keywordflow">if</span> (Res)
+<a name="l02304"></a>02304 <span class="keywordflow">return</span> Res;
+<a name="l02305"></a>02305 } <span class="keywordflow">else</span> {
+<a name="l02306"></a>02306 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
+<a name="l02307"></a>02307 CCVal, CCR, InFlag);
+<a name="l02308"></a>02308 <span class="keywordflow">if</span> (!Res)
+<a name="l02309"></a>02309 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
+<a name="l02310"></a>02310 <a class="code" href="namespacellvm_1_1ARMCC.html#a4bd63de978510703f28cd98ea7c0ffa5">ARMCC::getOppositeCondition</a>(CCVal), CCR, InFlag);
+<a name="l02311"></a>02311 <span class="keywordflow">if</span> (Res)
+<a name="l02312"></a>02312 <span class="keywordflow">return</span> Res;
+<a name="l02313"></a>02313 }
+<a name="l02314"></a>02314
+<a name="l02315"></a>02315 <span class="comment">// Pattern: (ARMcmov:i32 GPR:i32:$false,</span>
+<a name="l02316"></a>02316 <span class="comment">// (imm:i32)<<P:Pred_so_imm>>:$true,</span>
+<a name="l02317"></a>02317 <span class="comment">// (imm:i32):$cc)</span>
+<a name="l02318"></a>02318 <span class="comment">// Emits: (MOVCCi:i32 GPR:i32:$false,</span>
+<a name="l02319"></a>02319 <span class="comment">// (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)</span>
+<a name="l02320"></a>02320 <span class="comment">// Pattern complexity = 10 cost = 1 size = 0</span>
+<a name="l02321"></a>02321 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02322"></a>02322 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
+<a name="l02323"></a>02323 CCVal, CCR, InFlag);
+<a name="l02324"></a>02324 <span class="keywordflow">if</span> (!Res)
+<a name="l02325"></a>02325 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
+<a name="l02326"></a>02326 <a class="code" href="namespacellvm_1_1ARMCC.html#a4bd63de978510703f28cd98ea7c0ffa5">ARMCC::getOppositeCondition</a>(CCVal), CCR, InFlag);
+<a name="l02327"></a>02327 <span class="keywordflow">if</span> (Res)
+<a name="l02328"></a>02328 <span class="keywordflow">return</span> Res;
+<a name="l02329"></a>02329 } <span class="keywordflow">else</span> {
+<a name="l02330"></a>02330 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
+<a name="l02331"></a>02331 CCVal, CCR, InFlag);
+<a name="l02332"></a>02332 <span class="keywordflow">if</span> (!Res)
+<a name="l02333"></a>02333 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
+<a name="l02334"></a>02334 <a class="code" href="namespacellvm_1_1ARMCC.html#a4bd63de978510703f28cd98ea7c0ffa5">ARMCC::getOppositeCondition</a>(CCVal), CCR, InFlag);
+<a name="l02335"></a>02335 <span class="keywordflow">if</span> (Res)
+<a name="l02336"></a>02336 <span class="keywordflow">return</span> Res;
+<a name="l02337"></a>02337 }
+<a name="l02338"></a>02338 }
+<a name="l02339"></a>02339
+<a name="l02340"></a>02340 <span class="comment">// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)</span>
+<a name="l02341"></a>02341 <span class="comment">// Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)</span>
+<a name="l02342"></a>02342 <span class="comment">// Pattern complexity = 6 cost = 1 size = 0</span>
+<a name="l02343"></a>02343 <span class="comment">//</span>
+<a name="l02344"></a>02344 <span class="comment">// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)</span>
+<a name="l02345"></a>02345 <span class="comment">// Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)</span>
+<a name="l02346"></a>02346 <span class="comment">// Pattern complexity = 6 cost = 11 size = 0</span>
+<a name="l02347"></a>02347 <span class="comment">//</span>
+<a name="l02348"></a>02348 <span class="comment">// Also VMOVScc and VMOVDcc.</span>
+<a name="l02349"></a>02349 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp2 = CurDAG->getTargetConstant(CCVal, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>);
+<a name="l02350"></a>02350 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
+<a name="l02351"></a>02351 <span class="keywordtype">unsigned</span> Opc = 0;
+<a name="l02352"></a>02352 <span class="keywordflow">switch</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l02353"></a>02353 <span class="keywordflow">default</span>: <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"Illegal conditional move type!"</span>);
+<a name="l02354"></a>02354 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>:
+<a name="l02355"></a>02355 Opc = Subtarget->isThumb()
+<a name="l02356"></a>02356 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
+<a name="l02357"></a>02357 : ARM::MOVCCr;
+<a name="l02358"></a>02358 <span class="keywordflow">break</span>;
+<a name="l02359"></a>02359 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a>:
+<a name="l02360"></a>02360 Opc = ARM::VMOVScc;
+<a name="l02361"></a>02361 <span class="keywordflow">break</span>;
+<a name="l02362"></a>02362 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>:
+<a name="l02363"></a>02363 Opc = ARM::VMOVDcc;
+<a name="l02364"></a>02364 <span class="keywordflow">break</span>;
+<a name="l02365"></a>02365 }
+<a name="l02366"></a>02366 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
+<a name="l02367"></a>02367 }
+<a name="l02368"></a>02368 <span class="comment"></span>
+<a name="l02369"></a>02369 <span class="comment">/// Target-specific DAG combining for ISD::XOR.</span>
+<a name="l02370"></a>02370 <span class="comment">/// Target-independent combining lowers SELECT_CC nodes of the form</span>
+<a name="l02371"></a>02371 <span class="comment">/// select_cc setg[ge] X, 0, X, -X</span>
+<a name="l02372"></a>02372 <span class="comment">/// select_cc setgt X, -1, X, -X</span>
+<a name="l02373"></a>02373 <span class="comment">/// select_cc setl[te] X, 0, -X, X</span>
+<a name="l02374"></a>02374 <span class="comment">/// select_cc setlt X, 1, -X, X</span>
+<a name="l02375"></a>02375 <span class="comment">/// which represent Integer ABS into:</span>
+<a name="l02376"></a>02376 <span class="comment">/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)</span>
+<a name="l02377"></a>02377 <span class="comment">/// ARM instruction selection detects the latter and matches it to</span>
+<a name="l02378"></a>02378 <span class="comment">/// ARM::ABS or ARM::t2ABS machine node.</span>
+<a name="l02379"></a>02379 <span class="comment"></span><a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectABSOp(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N){
+<a name="l02380"></a>02380 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> XORSrc0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l02381"></a>02381 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> XORSrc1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l02382"></a>02382 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02383"></a>02383
+<a name="l02384"></a>02384 <span class="keywordflow">if</span> (Subtarget->isThumb1Only())
+<a name="l02385"></a>02385 <span class="keywordflow">return</span> NULL;
+<a name="l02386"></a>02386
+<a name="l02387"></a>02387 <span class="keywordflow">if</span> (XORSrc0.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269996b43a1f3e1d1f84a70fd4387535" title="Simple integer binary arithmetic operators.">ISD::ADD</a> || XORSrc1.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() != <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4a055321c361a0f6ee77ed764730ffc1">ISD::SRA</a>)
+<a name="l02388"></a>02388 <span class="keywordflow">return</span> NULL;
+<a name="l02389"></a>02389
+<a name="l02390"></a>02390 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ADDSrc0 = XORSrc0.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l02391"></a>02391 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ADDSrc1 = XORSrc0.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l02392"></a>02392 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SRASrc0 = XORSrc1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0);
+<a name="l02393"></a>02393 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> SRASrc1 = XORSrc1.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l02394"></a>02394 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *SRAConstant = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(SRASrc1);
+<a name="l02395"></a>02395 <a class="code" href="structllvm_1_1EVT.html">EVT</a> XType = SRASrc0.<a class="code" href="classllvm_1_1SDValue.html#a7d2ad4aa4277eb4e1138ff9791c8fbb7">getValueType</a>();
+<a name="l02396"></a>02396 <span class="keywordtype">unsigned</span> Size = XType.<a class="code" href="structllvm_1_1EVT.html#a8cca25ddb3be86ad23567dc8d36dacd3" title="getSizeInBits - Return the size of the specified value type in bits.">getSizeInBits</a>() - 1;
+<a name="l02397"></a>02397
+<a name="l02398"></a>02398 <span class="keywordflow">if</span> (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
+<a name="l02399"></a>02399 XType.isInteger() && SRAConstant != NULL &&
+<a name="l02400"></a>02400 Size == SRAConstant-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>()) {
+<a name="l02401"></a>02401 <span class="keywordtype">unsigned</span> Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
+<a name="l02402"></a>02402 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
+<a name="l02403"></a>02403 }
+<a name="l02404"></a>02404
+<a name="l02405"></a>02405 <span class="keywordflow">return</span> NULL;
+<a name="l02406"></a>02406 }
+<a name="l02407"></a>02407
+<a name="l02408"></a>02408 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectConcatVector(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l02409"></a>02409 <span class="comment">// The only time a CONCAT_VECTORS operation can have legal types is when</span>
+<a name="l02410"></a>02410 <span class="comment">// two 64-bit vectors are concatenated to a 128-bit vector.</span>
+<a name="l02411"></a>02411 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02412"></a>02412 <span class="keywordflow">if</span> (!VT.<a class="code" href="structllvm_1_1EVT.html#aea7fd4e11a4194a9df590e2975e4d939" title="is128BitVector - Return true if this is a 128-bit vector type.">is128BitVector</a>() || N-><a class="code" href="classllvm_1_1SDNode.html#abc5c2f1d47a517373030133c6a102106">getNumOperands</a>() != 2)
+<a name="l02413"></a>02413 <a class="code" href="ErrorHandling_8h.html#ace243f5c25697a1107cce46626b3dc94">llvm_unreachable</a>(<span class="stringliteral">"unexpected CONCAT_VECTORS"</span>);
+<a name="l02414"></a>02414 <span class="keywordflow">return</span> PairDRegs(VT, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1));
+<a name="l02415"></a>02415 }
+<a name="l02416"></a>02416
+<a name="l02417"></a>02417 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ARMDAGToDAGISel::SelectAtomic64(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Node, <span class="keywordtype">unsigned</span> Opc) {
+<a name="l02418"></a>02418 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 6></a> Ops;
+<a name="l02419"></a>02419 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1)); <span class="comment">// Ptr</span>
+<a name="l02420"></a>02420 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2)); <span class="comment">// Low part of Val1</span>
+<a name="l02421"></a>02421 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3)); <span class="comment">// High part of Val1</span>
+<a name="l02422"></a>02422 <span class="keywordflow">if</span> (Opc == ARM::ATOMCMPXCHG6432) {
+<a name="l02423"></a>02423 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(4)); <span class="comment">// Low part of Val2</span>
+<a name="l02424"></a>02424 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(5)); <span class="comment">// High part of Val2</span>
+<a name="l02425"></a>02425 }
+<a name="l02426"></a>02426 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Node-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0)); <span class="comment">// Chain</span>
+<a name="l02427"></a>02427 <a class="code" href="classllvm_1_1MachineMemOperand.html">MachineSDNode::mmo_iterator</a> MemOp = MF->allocateMemRefsArray(1);
+<a name="l02428"></a>02428 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
+<a name="l02429"></a>02429 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ResNode = CurDAG->getMachineNode(Opc, Node-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>(),
+<a name="l02430"></a>02430 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca62a222acce6360abd2726719fabc2797">MVT::Other</a>,
+<a name="l02431"></a>02431 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>() ,Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l02432"></a>02432 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
+<a name="l02433"></a>02433 <span class="keywordflow">return</span> ResNode;
+<a name="l02434"></a>02434 }
+<a name="l02435"></a>02435
+<a name="l02436"></a>02436 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="namespacellvm.html#af3ab12efdd6b4902d711e72b7a81f13b">ARMDAGToDAGISel::Select</a>(<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *N) {
+<a name="l02437"></a>02437 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l02438"></a>02438
+<a name="l02439"></a>02439 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#a7ef138746b04be6d07091b9ba49d74da">isMachineOpcode</a>())
+<a name="l02440"></a>02440 <span class="keywordflow">return</span> NULL; <span class="comment">// Already selected.</span>
+<a name="l02441"></a>02441
+<a name="l02442"></a>02442 <span class="keywordflow">switch</span> (N-><a class="code" href="classllvm_1_1SDNode.html#af0d328f3f61168f4ea7d6e4044af4f97">getOpcode</a>()) {
+<a name="l02443"></a>02443 <span class="keywordflow">default</span>: <span class="keywordflow">break</span>;
+<a name="l02444"></a>02444 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a92febb83e6ba116eb7aae8e7e3f70cc1">ISD::XOR</a>: {
+<a name="l02445"></a>02445 <span class="comment">// Select special operations if XOR node forms integer ABS pattern</span>
+<a name="l02446"></a>02446 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ResNode = SelectABSOp(N);
+<a name="l02447"></a>02447 <span class="keywordflow">if</span> (ResNode)
+<a name="l02448"></a>02448 <span class="keywordflow">return</span> ResNode;
+<a name="l02449"></a>02449 <span class="comment">// Other cases are autogenerated.</span>
+<a name="l02450"></a>02450 <span class="keywordflow">break</span>;
+<a name="l02451"></a>02451 }
+<a name="l02452"></a>02452 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a>: {
+<a name="l02453"></a>02453 <span class="keywordtype">unsigned</span> Val = cast<ConstantSDNode>(N)->getZExtValue();
+<a name="l02454"></a>02454 <span class="keywordtype">bool</span> UseCP = <span class="keyword">true</span>;
+<a name="l02455"></a>02455 <span class="keywordflow">if</span> (Subtarget->hasThumb2())
+<a name="l02456"></a>02456 <span class="comment">// Thumb2-aware targets have the MOVT instruction, so all immediates can</span>
+<a name="l02457"></a>02457 <span class="comment">// be done with MOV + MOVT, at worst.</span>
+<a name="l02458"></a>02458 UseCP = 0;
+<a name="l02459"></a>02459 <span class="keywordflow">else</span> {
+<a name="l02460"></a>02460 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02461"></a>02461 UseCP = (Val > 255 && <span class="comment">// MOV</span>
+<a name="l02462"></a>02462 ~Val > 255 && <span class="comment">// MOV + MVN</span>
+<a name="l02463"></a>02463 !<a class="code" href="namespacellvm_1_1ARM__AM.html#a2a556538eeeb14908c7a86d4f8d8e880">ARM_AM::isThumbImmShiftedVal</a>(Val)); <span class="comment">// MOV + LSL</span>
+<a name="l02464"></a>02464 } <span class="keywordflow">else</span>
+<a name="l02465"></a>02465 UseCP = (<a class="code" href="namespacellvm_1_1ARM__AM.html#ab18b193058b463093ad2a5701710bece">ARM_AM::getSOImmVal</a>(Val) == -1 && <span class="comment">// MOV</span>
+<a name="l02466"></a>02466 <a class="code" href="namespacellvm_1_1ARM__AM.html#ab18b193058b463093ad2a5701710bece">ARM_AM::getSOImmVal</a>(~Val) == -1 && <span class="comment">// MVN</span>
+<a name="l02467"></a>02467 !<a class="code" href="namespacellvm_1_1ARM__AM.html#ac229bc1c730b34dff4b13afbe7747e22">ARM_AM::isSOImmTwoPartVal</a>(Val)); <span class="comment">// two instrs.</span>
+<a name="l02468"></a>02468 }
+<a name="l02469"></a>02469
+<a name="l02470"></a>02470 <span class="keywordflow">if</span> (UseCP) {
+<a name="l02471"></a>02471 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> CPIdx =
+<a name="l02472"></a>02472 CurDAG->getTargetConstantPool(<a class="code" href="classllvm_1_1ConstantInt.html#a9105541412dab869e18b3cceebfff07d">ConstantInt::get</a>(
+<a name="l02473"></a>02473 <a class="code" href="classllvm_1_1Type.html#a30dd396c5b40cd86c1591872e574ccdf">Type::getInt32Ty</a>(*CurDAG->getContext()), Val),
+<a name="l02474"></a>02474 TLI.getPointerTy());
+<a name="l02475"></a>02475
+<a name="l02476"></a>02476 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ResNode;
+<a name="l02477"></a>02477 <span class="keywordflow">if</span> (Subtarget->isThumb1Only()) {
+<a name="l02478"></a>02478 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred = <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG);
+<a name="l02479"></a>02479 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PredReg = CurDAG->getRegister(0, MVT::i32);
+<a name="l02480"></a>02480 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
+<a name="l02481"></a>02481 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
+<a name="l02482"></a>02482 Ops, 4);
+<a name="l02483"></a>02483 } <span class="keywordflow">else</span> {
+<a name="l02484"></a>02484 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = {
+<a name="l02485"></a>02485 CPIdx,
+<a name="l02486"></a>02486 CurDAG->getTargetConstant(0, MVT::i32),
+<a name="l02487"></a>02487 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l02488"></a>02488 CurDAG->getRegister(0, MVT::i32),
+<a name="l02489"></a>02489 CurDAG->getEntryNode()
+<a name="l02490"></a>02490 };
+<a name="l02491"></a>02491 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
+<a name="l02492"></a>02492 Ops, 5);
+<a name="l02493"></a>02493 }
+<a name="l02494"></a>02494 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 0), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(ResNode, 0));
+<a name="l02495"></a>02495 <span class="keywordflow">return</span> NULL;
+<a name="l02496"></a>02496 }
+<a name="l02497"></a>02497
+<a name="l02498"></a>02498 <span class="comment">// Other cases are autogenerated.</span>
+<a name="l02499"></a>02499 <span class="keywordflow">break</span>;
+<a name="l02500"></a>02500 }
+<a name="l02501"></a>02501 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4b437632fd9b97dd36010d85eb363efe">ISD::FrameIndex</a>: {
+<a name="l02502"></a>02502 <span class="comment">// Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.</span>
+<a name="l02503"></a>02503 <span class="keywordtype">int</span> FI = cast<FrameIndexSDNode>(N)->getIndex();
+<a name="l02504"></a>02504 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
+<a name="l02505"></a>02505 <span class="keywordflow">if</span> (Subtarget->isThumb1Only()) {
+<a name="l02506"></a>02506 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
+<a name="l02507"></a>02507 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), CurDAG->getRegister(0, MVT::i32) };
+<a name="l02508"></a>02508 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
+<a name="l02509"></a>02509 } <span class="keywordflow">else</span> {
+<a name="l02510"></a>02510 <span class="keywordtype">unsigned</span> Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
+<a name="l02511"></a>02511 ARM::t2ADDri : ARM::ADDri);
+<a name="l02512"></a>02512 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
+<a name="l02513"></a>02513 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), CurDAG->getRegister(0, MVT::i32),
+<a name="l02514"></a>02514 CurDAG->getRegister(0, MVT::i32) };
+<a name="l02515"></a>02515 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
+<a name="l02516"></a>02516 }
+<a name="l02517"></a>02517 }
+<a name="l02518"></a>02518 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a3c6553c8acebe1b57c211ee45e2d8f98">ISD::SRL</a>:
+<a name="l02519"></a>02519 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> = SelectV6T2BitfieldExtractOp(N, <span class="keyword">false</span>))
+<a name="l02520"></a>02520 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>;
+<a name="l02521"></a>02521 <span class="keywordflow">break</span>;
+<a name="l02522"></a>02522 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a4a055321c361a0f6ee77ed764730ffc1">ISD::SRA</a>:
+<a name="l02523"></a>02523 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> = SelectV6T2BitfieldExtractOp(N, <span class="keyword">true</span>))
+<a name="l02524"></a>02524 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>;
+<a name="l02525"></a>02525 <span class="keywordflow">break</span>;
+<a name="l02526"></a>02526 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ad8aec9273962cf78d087090c11a1dd1c">ISD::MUL</a>:
+<a name="l02527"></a>02527 <span class="keywordflow">if</span> (Subtarget->isThumb1Only())
+<a name="l02528"></a>02528 <span class="keywordflow">break</span>;
+<a name="l02529"></a>02529 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *<a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">C</a> = dyn_cast<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1))) {
+<a name="l02530"></a>02530 <span class="keywordtype">unsigned</span> RHSV = <a class="code" href="namespacellvm_1_1CallingConv.html#a4f861731fc6dbfdccc05af5968d98974afd841a49aec1539bc88abc8ff9e170fb">C</a>->getZExtValue();
+<a name="l02531"></a>02531 <span class="keywordflow">if</span> (!RHSV) <span class="keywordflow">break</span>;
+<a name="l02532"></a>02532 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#af4d1a918800291e75b01ce1447be0e83">isPowerOf2_32</a>(RHSV-1)) { <span class="comment">// 2^n+1?</span>
+<a name="l02533"></a>02533 <span class="keywordtype">unsigned</span> ShImm = <a class="code" href="namespacellvm.html#a646986783f35e0fef8988f0f28d2589f">Log2_32</a>(RHSV-1);
+<a name="l02534"></a>02534 <span class="keywordflow">if</span> (ShImm >= 32)
+<a name="l02535"></a>02535 <span class="keywordflow">break</span>;
+<a name="l02536"></a>02536 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l02537"></a>02537 ShImm = <a class="code" href="namespacellvm_1_1ARM__AM.html#a257cdd16d16d0a9d9b358b5e5a472258">ARM_AM::getSORegOpc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a>, ShImm);
+<a name="l02538"></a>02538 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
+<a name="l02539"></a>02539 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Reg0 = CurDAG->getRegister(0, MVT::i32);
+<a name="l02540"></a>02540 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02541"></a>02541 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { V, V, ShImmOp, <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), Reg0, Reg0 };
+<a name="l02542"></a>02542 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
+<a name="l02543"></a>02543 } <span class="keywordflow">else</span> {
+<a name="l02544"></a>02544 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { V, V, Reg0, ShImmOp, <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), Reg0, Reg0 };
+<a name="l02545"></a>02545 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
+<a name="l02546"></a>02546 }
+<a name="l02547"></a>02547 }
+<a name="l02548"></a>02548 <span class="keywordflow">if</span> (<a class="code" href="namespacellvm.html#af4d1a918800291e75b01ce1447be0e83">isPowerOf2_32</a>(RHSV+1)) { <span class="comment">// 2^n-1?</span>
+<a name="l02549"></a>02549 <span class="keywordtype">unsigned</span> ShImm = <a class="code" href="namespacellvm.html#a646986783f35e0fef8988f0f28d2589f">Log2_32</a>(RHSV+1);
+<a name="l02550"></a>02550 <span class="keywordflow">if</span> (ShImm >= 32)
+<a name="l02551"></a>02551 <span class="keywordflow">break</span>;
+<a name="l02552"></a>02552 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l02553"></a>02553 ShImm = <a class="code" href="namespacellvm_1_1ARM__AM.html#a257cdd16d16d0a9d9b358b5e5a472258">ARM_AM::getSORegOpc</a>(<a class="code" href="namespacellvm_1_1ARM__AM.html#a76f5f9f36bbd9f03c844c5b565f239efaafeb1424944dafbde8a990bce1f5bd84">ARM_AM::lsl</a>, ShImm);
+<a name="l02554"></a>02554 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
+<a name="l02555"></a>02555 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Reg0 = CurDAG->getRegister(0, MVT::i32);
+<a name="l02556"></a>02556 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02557"></a>02557 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { V, V, ShImmOp, <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), Reg0, Reg0 };
+<a name="l02558"></a>02558 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
+<a name="l02559"></a>02559 } <span class="keywordflow">else</span> {
+<a name="l02560"></a>02560 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { V, V, Reg0, ShImmOp, <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), Reg0, Reg0 };
+<a name="l02561"></a>02561 <span class="keywordflow">return</span> CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
+<a name="l02562"></a>02562 }
+<a name="l02563"></a>02563 }
+<a name="l02564"></a>02564 }
+<a name="l02565"></a>02565 <span class="keywordflow">break</span>;
+<a name="l02566"></a>02566 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac513a7da1bf74fb3e3c594da8534f2d2" title="Bitwise operators - logical and, logical or, logical xor.">ISD::AND</a>: {
+<a name="l02567"></a>02567 <span class="comment">// Check for unsigned bitfield extract</span>
+<a name="l02568"></a>02568 <span class="keywordflow">if</span> (<a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *<a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a> = SelectV6T2BitfieldExtractOp(N, <span class="keyword">false</span>))
+<a name="l02569"></a>02569 <span class="keywordflow">return</span> <a class="code" href="namespacellvm_1_1ARM__PROC.html#aac31dd660a6f18140efdd62b351cb11ba41e4a98ca287d35fab0923aa355d63a5">I</a>;
+<a name="l02570"></a>02570
+<a name="l02571"></a>02571 <span class="comment">// (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits</span>
+<a name="l02572"></a>02572 <span class="comment">// of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits</span>
+<a name="l02573"></a>02573 <span class="comment">// are entirely contributed by c2 and lower 16-bits are entirely contributed</span>
+<a name="l02574"></a>02574 <span class="comment">// by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).</span>
+<a name="l02575"></a>02575 <span class="comment">// Select it to: "movt x, ((c1 & 0xffff) >> 16)</span>
+<a name="l02576"></a>02576 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02577"></a>02577 <span class="keywordflow">if</span> (VT != MVT::i32)
+<a name="l02578"></a>02578 <span class="keywordflow">break</span>;
+<a name="l02579"></a>02579 <span class="keywordtype">unsigned</span> Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
+<a name="l02580"></a>02580 ? ARM::t2MOVTi16
+<a name="l02581"></a>02581 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
+<a name="l02582"></a>02582 <span class="keywordflow">if</span> (!Opc)
+<a name="l02583"></a>02583 <span class="keywordflow">break</span>;
+<a name="l02584"></a>02584 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l02585"></a>02585 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *N1C = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(N1);
+<a name="l02586"></a>02586 <span class="keywordflow">if</span> (!N1C)
+<a name="l02587"></a>02587 <span class="keywordflow">break</span>;
+<a name="l02588"></a>02588 <span class="keywordflow">if</span> (N0.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a7415ab9f2172c59a2ee7c7a02afa56a4">ISD::OR</a> && N0.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>()-><a class="code" href="classllvm_1_1SDNode.html#a52753947fce3a01b1c18dd4713c587e8">hasOneUse</a>()) {
+<a name="l02589"></a>02589 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N2 = N0.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(1);
+<a name="l02590"></a>02590 <a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a> *N2C = <a class="code" href="namespacellvm.html#a8d8db3a5b2508f7086ef2d43036007b3">dyn_cast</a><<a class="code" href="classllvm_1_1ConstantSDNode.html">ConstantSDNode</a>>(N2);
+<a name="l02591"></a>02591 <span class="keywordflow">if</span> (!N2C)
+<a name="l02592"></a>02592 <span class="keywordflow">break</span>;
+<a name="l02593"></a>02593 <span class="keywordtype">unsigned</span> N1CVal = N1C-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l02594"></a>02594 <span class="keywordtype">unsigned</span> N2CVal = N2C-><a class="code" href="classllvm_1_1ConstantSDNode.html#a1e9365c991dd55e65e9d5ab5653812e4">getZExtValue</a>();
+<a name="l02595"></a>02595 <span class="keywordflow">if</span> ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
+<a name="l02596"></a>02596 (N1CVal & 0xffffU) == 0xffffU &&
+<a name="l02597"></a>02597 (N2CVal & 0xffffU) == 0x0U) {
+<a name="l02598"></a>02598 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933ac21c0e218a109e1353d239807dd4f3c9">Imm16</a> = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
+<a name="l02599"></a>02599 MVT::i32);
+<a name="l02600"></a>02600 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N0.<a class="code" href="classllvm_1_1SDValue.html#a5891be2cd50b5b7f01eb7c1cb0e7a682">getOperand</a>(0), <a class="code" href="namespacellvm_1_1X86II.html#acd283bc8136a594505ec483f4a1cc933ac21c0e218a109e1353d239807dd4f3c9">Imm16</a>,
+<a name="l02601"></a>02601 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), CurDAG->getRegister(0, MVT::i32) };
+<a name="l02602"></a>02602 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
+<a name="l02603"></a>02603 }
+<a name="l02604"></a>02604 }
+<a name="l02605"></a>02605 <span class="keywordflow">break</span>;
+<a name="l02606"></a>02606 }
+<a name="l02607"></a>02607 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a7f93dc1b4123a3d49e2a544960758ef1">ARMISD::VMOVRRD</a>:
+<a name="l02608"></a>02608 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a7f93dc1b4123a3d49e2a544960758ef1">ARM::VMOVRRD</a>, dl, MVT::i32, MVT::i32,
+<a name="l02609"></a>02609 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l02610"></a>02610 CurDAG->getRegister(0, MVT::i32));
+<a name="l02611"></a>02611 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a79c959df09509d7ff66d9b04bc40d18d">ISD::UMUL_LOHI</a>: {
+<a name="l02612"></a>02612 <span class="keywordflow">if</span> (Subtarget->isThumb1Only())
+<a name="l02613"></a>02613 <span class="keywordflow">break</span>;
+<a name="l02614"></a>02614 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02615"></a>02615 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1),
+<a name="l02616"></a>02616 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), CurDAG->getRegister(0, MVT::i32),
+<a name="l02617"></a>02617 CurDAG->getRegister(0, MVT::i32) };
+<a name="l02618"></a>02618 <span class="keywordflow">return</span> CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
+<a name="l02619"></a>02619 } <span class="keywordflow">else</span> {
+<a name="l02620"></a>02620 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1),
+<a name="l02621"></a>02621 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), CurDAG->getRegister(0, MVT::i32),
+<a name="l02622"></a>02622 CurDAG->getRegister(0, MVT::i32) };
+<a name="l02623"></a>02623 <span class="keywordflow">return</span> CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
+<a name="l02624"></a>02624 ARM::UMULL : ARM::UMULLv5,
+<a name="l02625"></a>02625 dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 5);
+<a name="l02626"></a>02626 }
+<a name="l02627"></a>02627 }
+<a name="l02628"></a>02628 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a1354c6f8508d6cd697dc89a5d9a52dfd">ISD::SMUL_LOHI</a>: {
+<a name="l02629"></a>02629 <span class="keywordflow">if</span> (Subtarget->isThumb1Only())
+<a name="l02630"></a>02630 <span class="keywordflow">break</span>;
+<a name="l02631"></a>02631 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02632"></a>02632 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1),
+<a name="l02633"></a>02633 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), CurDAG->getRegister(0, MVT::i32) };
+<a name="l02634"></a>02634 <span class="keywordflow">return</span> CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
+<a name="l02635"></a>02635 } <span class="keywordflow">else</span> {
+<a name="l02636"></a>02636 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1),
+<a name="l02637"></a>02637 <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG), CurDAG->getRegister(0, MVT::i32),
+<a name="l02638"></a>02638 CurDAG->getRegister(0, MVT::i32) };
+<a name="l02639"></a>02639 <span class="keywordflow">return</span> CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
+<a name="l02640"></a>02640 ARM::SMULL : ARM::SMULLv5,
+<a name="l02641"></a>02641 dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 5);
+<a name="l02642"></a>02642 }
+<a name="l02643"></a>02643 }
+<a name="l02644"></a>02644 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a8d9d96ad008a475ebbff8e366bbc1eb6">ARMISD::UMLAL</a>:{
+<a name="l02645"></a>02645 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02646"></a>02646 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2),
+<a name="l02647"></a>02647 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3), <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l02648"></a>02648 CurDAG->getRegister(0, MVT::i32)};
+<a name="l02649"></a>02649 <span class="keywordflow">return</span> CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops, 6);
+<a name="l02650"></a>02650 }<span class="keywordflow">else</span>{
+<a name="l02651"></a>02651 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2),
+<a name="l02652"></a>02652 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3), <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l02653"></a>02653 CurDAG->getRegister(0, MVT::i32),
+<a name="l02654"></a>02654 CurDAG->getRegister(0, MVT::i32) };
+<a name="l02655"></a>02655 <span class="keywordflow">return</span> CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
+<a name="l02656"></a>02656 <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a8d9d96ad008a475ebbff8e366bbc1eb6">ARM::UMLAL</a> : ARM::UMLALv5,
+<a name="l02657"></a>02657 dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 7);
+<a name="l02658"></a>02658 }
+<a name="l02659"></a>02659 }
+<a name="l02660"></a>02660 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9aa174d9797327e782f169f497338fac95">ARMISD::SMLAL</a>:{
+<a name="l02661"></a>02661 <span class="keywordflow">if</span> (Subtarget->isThumb()) {
+<a name="l02662"></a>02662 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2),
+<a name="l02663"></a>02663 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3), <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l02664"></a>02664 CurDAG->getRegister(0, MVT::i32)};
+<a name="l02665"></a>02665 <span class="keywordflow">return</span> CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops, 6);
+<a name="l02666"></a>02666 }<span class="keywordflow">else</span>{
+<a name="l02667"></a>02667 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2),
+<a name="l02668"></a>02668 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3), <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG),
+<a name="l02669"></a>02669 CurDAG->getRegister(0, MVT::i32),
+<a name="l02670"></a>02670 CurDAG->getRegister(0, MVT::i32) };
+<a name="l02671"></a>02671 <span class="keywordflow">return</span> CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
+<a name="l02672"></a>02672 <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9aa174d9797327e782f169f497338fac95">ARM::SMLAL</a> : ARM::SMLALv5,
+<a name="l02673"></a>02673 dl, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Ops, 7);
+<a name="l02674"></a>02674 }
+<a name="l02675"></a>02675 }
+<a name="l02676"></a>02676 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a269b81f007000306e3e69d0d290c2159">ISD::LOAD</a>: {
+<a name="l02677"></a>02677 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ResNode = 0;
+<a name="l02678"></a>02678 <span class="keywordflow">if</span> (Subtarget->isThumb() && Subtarget->hasThumb2())
+<a name="l02679"></a>02679 ResNode = SelectT2IndexedLoad(N);
+<a name="l02680"></a>02680 <span class="keywordflow">else</span>
+<a name="l02681"></a>02681 ResNode = SelectARMIndexedLoad(N);
+<a name="l02682"></a>02682 <span class="keywordflow">if</span> (ResNode)
+<a name="l02683"></a>02683 <span class="keywordflow">return</span> ResNode;
+<a name="l02684"></a>02684 <span class="comment">// Other cases are autogenerated.</span>
+<a name="l02685"></a>02685 <span class="keywordflow">break</span>;
+<a name="l02686"></a>02686 }
+<a name="l02687"></a>02687 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a4621d333784e3cd8c9f92a1443013dbe">ARMISD::BRCOND</a>: {
+<a name="l02688"></a>02688 <span class="comment">// Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)</span>
+<a name="l02689"></a>02689 <span class="comment">// Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)</span>
+<a name="l02690"></a>02690 <span class="comment">// Pattern complexity = 6 cost = 1 size = 0</span>
+<a name="l02691"></a>02691
+<a name="l02692"></a>02692 <span class="comment">// Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)</span>
+<a name="l02693"></a>02693 <span class="comment">// Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)</span>
+<a name="l02694"></a>02694 <span class="comment">// Pattern complexity = 6 cost = 1 size = 0</span>
+<a name="l02695"></a>02695
+<a name="l02696"></a>02696 <span class="comment">// Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)</span>
+<a name="l02697"></a>02697 <span class="comment">// Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)</span>
+<a name="l02698"></a>02698 <span class="comment">// Pattern complexity = 6 cost = 1 size = 0</span>
+<a name="l02699"></a>02699
+<a name="l02700"></a>02700 <span class="keywordtype">unsigned</span> Opc = Subtarget->isThumb() ?
+<a name="l02701"></a>02701 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
+<a name="l02702"></a>02702 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l02703"></a>02703 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l02704"></a>02704 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N2 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2);
+<a name="l02705"></a>02705 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> N3 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3);
+<a name="l02706"></a>02706 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> InFlag = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(4);
+<a name="l02707"></a>02707 assert(N1.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a8472e46f9e4db168c5610ecdfb05dbaf" title="Various leaf nodes.">ISD::BasicBlock</a>);
+<a name="l02708"></a>02708 assert(N2.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110aac2f0a84dd2aa5ee4c3f1385e9565f5e">ISD::Constant</a>);
+<a name="l02709"></a>02709 assert(N3.<a class="code" href="classllvm_1_1SDValue.html#a0caf6a31d8034336a9ba7791a5f583f1">getOpcode</a>() == <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a419e8283a58d2b1b86591fa7f18ccfd9">ISD::Register</a>);
+<a name="l02710"></a>02710
+<a name="l02711"></a>02711 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Tmp2 = CurDAG->getTargetConstant(((<span class="keywordtype">unsigned</span>)
+<a name="l02712"></a>02712 cast<ConstantSDNode>(N2)->getZExtValue()),
+<a name="l02713"></a>02713 MVT::i32);
+<a name="l02714"></a>02714 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N1, Tmp2, N3, Chain, InFlag };
+<a name="l02715"></a>02715 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
+<a name="l02716"></a>02716 <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca59a1908cf136662bcfdc11ed49515ca9">MVT::Glue</a>, Ops, 5);
+<a name="l02717"></a>02717 Chain = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(ResNode, 0);
+<a name="l02718"></a>02718 <span class="keywordflow">if</span> (N-><a class="code" href="classllvm_1_1SDNode.html#ab319fc51db27ec95fd50a910c7ccec94">getNumValues</a>() == 2) {
+<a name="l02719"></a>02719 InFlag = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(ResNode, 1);
+<a name="l02720"></a>02720 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 1), InFlag);
+<a name="l02721"></a>02721 }
+<a name="l02722"></a>02722 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 0),
+<a name="l02723"></a>02723 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Chain.<a class="code" href="classllvm_1_1SDValue.html#a3fad042e27ba626acf5366c845b352d3" title="get the SDNode which holds the desired result">getNode</a>(), Chain.<a class="code" href="classllvm_1_1SDValue.html#a64881a6ca7154fccaeb92cdb1e1e745e" title="get the index which selects a specific result in the SDNode">getResNo</a>()));
+<a name="l02724"></a>02724 <span class="keywordflow">return</span> NULL;
+<a name="l02725"></a>02725 }
+<a name="l02726"></a>02726 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9aee74cff1cb1ea095617b5fa044e342db">ARMISD::CMOV</a>:
+<a name="l02727"></a>02727 <span class="keywordflow">return</span> SelectCMOVOp(N);
+<a name="l02728"></a>02728 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a2ce278a3ff293b574f11d4ee0276770d">ARMISD::VZIP</a>: {
+<a name="l02729"></a>02729 <span class="keywordtype">unsigned</span> Opc = 0;
+<a name="l02730"></a>02730 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02731"></a>02731 <span class="keywordflow">switch</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l02732"></a>02732 <span class="keywordflow">default</span>: <span class="keywordflow">return</span> NULL;
+<a name="l02733"></a>02733 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca31f0af1863185f14e91278f7d567ae81">MVT::v8i8</a>: Opc = ARM::VZIPd8; <span class="keywordflow">break</span>;
+<a name="l02734"></a>02734 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca9b846c126ddfbe57601a050653a45bd3">MVT::v4i16</a>: Opc = ARM::VZIPd16; <span class="keywordflow">break</span>;
+<a name="l02735"></a>02735 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0bc51b0308b6c057dc86d2a6bf4b6573">MVT::v2f32</a>:
+<a name="l02736"></a>02736 <span class="comment">// vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.</span>
+<a name="l02737"></a>02737 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca5782b71c5eafe937e8d31d7b62497d99">MVT::v2i32</a>: Opc = ARM::VTRNd32; <span class="keywordflow">break</span>;
+<a name="l02738"></a>02738 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>: Opc = ARM::VZIPq8; <span class="keywordflow">break</span>;
+<a name="l02739"></a>02739 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>: Opc = ARM::VZIPq16; <span class="keywordflow">break</span>;
+<a name="l02740"></a>02740 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l02741"></a>02741 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>: Opc = ARM::VZIPq32; <span class="keywordflow">break</span>;
+<a name="l02742"></a>02742 }
+<a name="l02743"></a>02743 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred = <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG);
+<a name="l02744"></a>02744 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PredReg = CurDAG->getRegister(0, MVT::i32);
+<a name="l02745"></a>02745 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Pred, PredReg };
+<a name="l02746"></a>02746 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
+<a name="l02747"></a>02747 }
+<a name="l02748"></a>02748 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a3d175a42f3d21e9d95bc684768de999a">ARMISD::VUZP</a>: {
+<a name="l02749"></a>02749 <span class="keywordtype">unsigned</span> Opc = 0;
+<a name="l02750"></a>02750 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02751"></a>02751 <span class="keywordflow">switch</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l02752"></a>02752 <span class="keywordflow">default</span>: <span class="keywordflow">return</span> NULL;
+<a name="l02753"></a>02753 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca31f0af1863185f14e91278f7d567ae81">MVT::v8i8</a>: Opc = ARM::VUZPd8; <span class="keywordflow">break</span>;
+<a name="l02754"></a>02754 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca9b846c126ddfbe57601a050653a45bd3">MVT::v4i16</a>: Opc = ARM::VUZPd16; <span class="keywordflow">break</span>;
+<a name="l02755"></a>02755 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0bc51b0308b6c057dc86d2a6bf4b6573">MVT::v2f32</a>:
+<a name="l02756"></a>02756 <span class="comment">// vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.</span>
+<a name="l02757"></a>02757 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca5782b71c5eafe937e8d31d7b62497d99">MVT::v2i32</a>: Opc = ARM::VTRNd32; <span class="keywordflow">break</span>;
+<a name="l02758"></a>02758 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>: Opc = ARM::VUZPq8; <span class="keywordflow">break</span>;
+<a name="l02759"></a>02759 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>: Opc = ARM::VUZPq16; <span class="keywordflow">break</span>;
+<a name="l02760"></a>02760 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l02761"></a>02761 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>: Opc = ARM::VUZPq32; <span class="keywordflow">break</span>;
+<a name="l02762"></a>02762 }
+<a name="l02763"></a>02763 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred = <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG);
+<a name="l02764"></a>02764 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PredReg = CurDAG->getRegister(0, MVT::i32);
+<a name="l02765"></a>02765 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Pred, PredReg };
+<a name="l02766"></a>02766 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
+<a name="l02767"></a>02767 }
+<a name="l02768"></a>02768 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a78557d58c18ae631207ea472be421497">ARMISD::VTRN</a>: {
+<a name="l02769"></a>02769 <span class="keywordtype">unsigned</span> Opc = 0;
+<a name="l02770"></a>02770 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02771"></a>02771 <span class="keywordflow">switch</span> (VT.<a class="code" href="structllvm_1_1EVT.html#a5b45953b758fdfe88452530f7d8371bc">getSimpleVT</a>().<a class="code" href="classllvm_1_1MVT.html#a27bda7d8e8e4f0337650a892f3c9b46a">SimpleTy</a>) {
+<a name="l02772"></a>02772 <span class="keywordflow">default</span>: <span class="keywordflow">return</span> NULL;
+<a name="l02773"></a>02773 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca31f0af1863185f14e91278f7d567ae81">MVT::v8i8</a>: Opc = ARM::VTRNd8; <span class="keywordflow">break</span>;
+<a name="l02774"></a>02774 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca9b846c126ddfbe57601a050653a45bd3">MVT::v4i16</a>: Opc = ARM::VTRNd16; <span class="keywordflow">break</span>;
+<a name="l02775"></a>02775 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca0bc51b0308b6c057dc86d2a6bf4b6573">MVT::v2f32</a>:
+<a name="l02776"></a>02776 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca5782b71c5eafe937e8d31d7b62497d99">MVT::v2i32</a>: Opc = ARM::VTRNd32; <span class="keywordflow">break</span>;
+<a name="l02777"></a>02777 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>: Opc = ARM::VTRNq8; <span class="keywordflow">break</span>;
+<a name="l02778"></a>02778 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca97a9e92da302a5dd0ff02cf2587d7db3">MVT::v8i16</a>: Opc = ARM::VTRNq16; <span class="keywordflow">break</span>;
+<a name="l02779"></a>02779 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca49615145fd6c985a530ec3743d053475">MVT::v4f32</a>:
+<a name="l02780"></a>02780 <span class="keywordflow">case</span> <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca4b321667ee9d821362ffabd3c24d17b1">MVT::v4i32</a>: Opc = ARM::VTRNq32; <span class="keywordflow">break</span>;
+<a name="l02781"></a>02781 }
+<a name="l02782"></a>02782 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Pred = <a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG);
+<a name="l02783"></a>02783 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> PredReg = CurDAG->getRegister(0, MVT::i32);
+<a name="l02784"></a>02784 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Ops[] = { N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1), Pred, PredReg };
+<a name="l02785"></a>02785 <span class="keywordflow">return</span> CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
+<a name="l02786"></a>02786 }
+<a name="l02787"></a>02787 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a9b3b5c8aca58fc851520aab312b46637">ARMISD::BUILD_VECTOR</a>: {
+<a name="l02788"></a>02788 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VecVT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l02789"></a>02789 <a class="code" href="structllvm_1_1EVT.html">EVT</a> EltVT = VecVT.<a class="code" href="structllvm_1_1EVT.html#a3a07c062cc9330acd8e8c4e3930cbb25">getVectorElementType</a>();
+<a name="l02790"></a>02790 <span class="keywordtype">unsigned</span> NumElts = VecVT.<a class="code" href="structllvm_1_1EVT.html#a42bca41d2438197c12b6db2c710a959c">getVectorNumElements</a>();
+<a name="l02791"></a>02791 <span class="keywordflow">if</span> (EltVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cac661c912350e3095c85ba75b8dbc17b1">MVT::f64</a>) {
+<a name="l02792"></a>02792 assert(NumElts == 2 && <span class="stringliteral">"unexpected type for BUILD_VECTOR"</span>);
+<a name="l02793"></a>02793 <span class="keywordflow">return</span> PairDRegs(VecVT, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1));
+<a name="l02794"></a>02794 }
+<a name="l02795"></a>02795 assert(EltVT == <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca586bae91020e6d8cccfe0995f527606f">MVT::f32</a> && <span class="stringliteral">"unexpected type for BUILD_VECTOR"</span>);
+<a name="l02796"></a>02796 <span class="keywordflow">if</span> (NumElts == 2)
+<a name="l02797"></a>02797 <span class="keywordflow">return</span> PairSRegs(VecVT, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1));
+<a name="l02798"></a>02798 assert(NumElts == 4 && <span class="stringliteral">"unexpected type for BUILD_VECTOR"</span>);
+<a name="l02799"></a>02799 <span class="keywordflow">return</span> QuadSRegs(VecVT, N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1),
+<a name="l02800"></a>02800 N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2), N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3));
+<a name="l02801"></a>02801 }
+<a name="l02802"></a>02802
+<a name="l02803"></a>02803 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a81b77974c326f91d888b4f7c7346440d">ARMISD::VLD2DUP</a>: {
+<a name="l02804"></a>02804 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
+<a name="l02805"></a>02805 ARM::VLD2DUPd32 };
+<a name="l02806"></a>02806 <span class="keywordflow">return</span> SelectVLDDup(N, <span class="keyword">false</span>, 2, Opcodes);
+<a name="l02807"></a>02807 }
+<a name="l02808"></a>02808
+<a name="l02809"></a>02809 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9aeb8a7ec48dfdbb30f676f1f9ed78515e">ARMISD::VLD3DUP</a>: {
+<a name="l02810"></a>02810 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
+<a name="l02811"></a>02811 ARM::VLD3DUPd16Pseudo,
+<a name="l02812"></a>02812 ARM::VLD3DUPd32Pseudo };
+<a name="l02813"></a>02813 <span class="keywordflow">return</span> SelectVLDDup(N, <span class="keyword">false</span>, 3, Opcodes);
+<a name="l02814"></a>02814 }
+<a name="l02815"></a>02815
+<a name="l02816"></a>02816 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a682019fb60ebfdcb1b6c12bef90e81d1">ARMISD::VLD4DUP</a>: {
+<a name="l02817"></a>02817 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
+<a name="l02818"></a>02818 ARM::VLD4DUPd16Pseudo,
+<a name="l02819"></a>02819 ARM::VLD4DUPd32Pseudo };
+<a name="l02820"></a>02820 <span class="keywordflow">return</span> SelectVLDDup(N, <span class="keyword">false</span>, 4, Opcodes);
+<a name="l02821"></a>02821 }
+<a name="l02822"></a>02822
+<a name="l02823"></a>02823 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9aeecdd98f156fccc64b091ed05e2a7fa2">ARMISD::VLD2DUP_UPD</a>: {
+<a name="l02824"></a>02824 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
+<a name="l02825"></a>02825 ARM::VLD2DUPd16wb_fixed,
+<a name="l02826"></a>02826 ARM::VLD2DUPd32wb_fixed };
+<a name="l02827"></a>02827 <span class="keywordflow">return</span> SelectVLDDup(N, <span class="keyword">true</span>, 2, Opcodes);
+<a name="l02828"></a>02828 }
+<a name="l02829"></a>02829
+<a name="l02830"></a>02830 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a55c84e4b70ccda76faa80ac003a66b86">ARMISD::VLD3DUP_UPD</a>: {
+<a name="l02831"></a>02831 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
+<a name="l02832"></a>02832 ARM::VLD3DUPd16Pseudo_UPD,
+<a name="l02833"></a>02833 ARM::VLD3DUPd32Pseudo_UPD };
+<a name="l02834"></a>02834 <span class="keywordflow">return</span> SelectVLDDup(N, <span class="keyword">true</span>, 3, Opcodes);
+<a name="l02835"></a>02835 }
+<a name="l02836"></a>02836
+<a name="l02837"></a>02837 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a8cae6c5ad12cf66a9b86fe48082bd9d1">ARMISD::VLD4DUP_UPD</a>: {
+<a name="l02838"></a>02838 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
+<a name="l02839"></a>02839 ARM::VLD4DUPd16Pseudo_UPD,
+<a name="l02840"></a>02840 ARM::VLD4DUPd32Pseudo_UPD };
+<a name="l02841"></a>02841 <span class="keywordflow">return</span> SelectVLDDup(N, <span class="keyword">true</span>, 4, Opcodes);
+<a name="l02842"></a>02842 }
+<a name="l02843"></a>02843
+<a name="l02844"></a>02844 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9aeb657e0aaf4405a13d3379c9ef08c5e1">ARMISD::VLD1_UPD</a>: {
+<a name="l02845"></a>02845 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
+<a name="l02846"></a>02846 ARM::VLD1d16wb_fixed,
+<a name="l02847"></a>02847 ARM::VLD1d32wb_fixed,
+<a name="l02848"></a>02848 ARM::VLD1d64wb_fixed };
+<a name="l02849"></a>02849 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
+<a name="l02850"></a>02850 ARM::VLD1q16wb_fixed,
+<a name="l02851"></a>02851 ARM::VLD1q32wb_fixed,
+<a name="l02852"></a>02852 ARM::VLD1q64wb_fixed };
+<a name="l02853"></a>02853 <span class="keywordflow">return</span> SelectVLD(N, <span class="keyword">true</span>, 1, DOpcodes, QOpcodes, 0);
+<a name="l02854"></a>02854 }
+<a name="l02855"></a>02855
+<a name="l02856"></a>02856 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a3e74c01534bbe58a9716c4ed9afb552b">ARMISD::VLD2_UPD</a>: {
+<a name="l02857"></a>02857 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
+<a name="l02858"></a>02858 ARM::VLD2d16wb_fixed,
+<a name="l02859"></a>02859 ARM::VLD2d32wb_fixed,
+<a name="l02860"></a>02860 ARM::VLD1q64wb_fixed};
+<a name="l02861"></a>02861 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
+<a name="l02862"></a>02862 ARM::VLD2q16PseudoWB_fixed,
+<a name="l02863"></a>02863 ARM::VLD2q32PseudoWB_fixed };
+<a name="l02864"></a>02864 <span class="keywordflow">return</span> SelectVLD(N, <span class="keyword">true</span>, 2, DOpcodes, QOpcodes, 0);
+<a name="l02865"></a>02865 }
+<a name="l02866"></a>02866
+<a name="l02867"></a>02867 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a2dcef9e9a88a5601e3615bd024f89ebc">ARMISD::VLD3_UPD</a>: {
+<a name="l02868"></a>02868 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
+<a name="l02869"></a>02869 ARM::VLD3d16Pseudo_UPD,
+<a name="l02870"></a>02870 ARM::VLD3d32Pseudo_UPD,
+<a name="l02871"></a>02871 ARM::VLD1q64wb_fixed};
+<a name="l02872"></a>02872 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
+<a name="l02873"></a>02873 ARM::VLD3q16Pseudo_UPD,
+<a name="l02874"></a>02874 ARM::VLD3q32Pseudo_UPD };
+<a name="l02875"></a>02875 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
+<a name="l02876"></a>02876 ARM::VLD3q16oddPseudo_UPD,
+<a name="l02877"></a>02877 ARM::VLD3q32oddPseudo_UPD };
+<a name="l02878"></a>02878 <span class="keywordflow">return</span> SelectVLD(N, <span class="keyword">true</span>, 3, DOpcodes, QOpcodes0, QOpcodes1);
+<a name="l02879"></a>02879 }
+<a name="l02880"></a>02880
+<a name="l02881"></a>02881 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9acbc76b0e9da47cff86f227b76a101877">ARMISD::VLD4_UPD</a>: {
+<a name="l02882"></a>02882 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
+<a name="l02883"></a>02883 ARM::VLD4d16Pseudo_UPD,
+<a name="l02884"></a>02884 ARM::VLD4d32Pseudo_UPD,
+<a name="l02885"></a>02885 ARM::VLD1q64wb_fixed};
+<a name="l02886"></a>02886 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
+<a name="l02887"></a>02887 ARM::VLD4q16Pseudo_UPD,
+<a name="l02888"></a>02888 ARM::VLD4q32Pseudo_UPD };
+<a name="l02889"></a>02889 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
+<a name="l02890"></a>02890 ARM::VLD4q16oddPseudo_UPD,
+<a name="l02891"></a>02891 ARM::VLD4q32oddPseudo_UPD };
+<a name="l02892"></a>02892 <span class="keywordflow">return</span> SelectVLD(N, <span class="keyword">true</span>, 4, DOpcodes, QOpcodes0, QOpcodes1);
+<a name="l02893"></a>02893 }
+<a name="l02894"></a>02894
+<a name="l02895"></a>02895 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9aef111725b7a6bc348025dbe88c610e52">ARMISD::VLD2LN_UPD</a>: {
+<a name="l02896"></a>02896 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
+<a name="l02897"></a>02897 ARM::VLD2LNd16Pseudo_UPD,
+<a name="l02898"></a>02898 ARM::VLD2LNd32Pseudo_UPD };
+<a name="l02899"></a>02899 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
+<a name="l02900"></a>02900 ARM::VLD2LNq32Pseudo_UPD };
+<a name="l02901"></a>02901 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">true</span>, <span class="keyword">true</span>, 2, DOpcodes, QOpcodes);
+<a name="l02902"></a>02902 }
+<a name="l02903"></a>02903
+<a name="l02904"></a>02904 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9ad1a20b1fad0a456eeea32953e3711d67">ARMISD::VLD3LN_UPD</a>: {
+<a name="l02905"></a>02905 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
+<a name="l02906"></a>02906 ARM::VLD3LNd16Pseudo_UPD,
+<a name="l02907"></a>02907 ARM::VLD3LNd32Pseudo_UPD };
+<a name="l02908"></a>02908 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
+<a name="l02909"></a>02909 ARM::VLD3LNq32Pseudo_UPD };
+<a name="l02910"></a>02910 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">true</span>, <span class="keyword">true</span>, 3, DOpcodes, QOpcodes);
+<a name="l02911"></a>02911 }
+<a name="l02912"></a>02912
+<a name="l02913"></a>02913 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9af06cac064eb63dda89fc54210230c6c7">ARMISD::VLD4LN_UPD</a>: {
+<a name="l02914"></a>02914 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
+<a name="l02915"></a>02915 ARM::VLD4LNd16Pseudo_UPD,
+<a name="l02916"></a>02916 ARM::VLD4LNd32Pseudo_UPD };
+<a name="l02917"></a>02917 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
+<a name="l02918"></a>02918 ARM::VLD4LNq32Pseudo_UPD };
+<a name="l02919"></a>02919 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">true</span>, <span class="keyword">true</span>, 4, DOpcodes, QOpcodes);
+<a name="l02920"></a>02920 }
+<a name="l02921"></a>02921
+<a name="l02922"></a>02922 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a66260b6c8cb9ac5ae51cb28d85f8609a">ARMISD::VST1_UPD</a>: {
+<a name="l02923"></a>02923 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
+<a name="l02924"></a>02924 ARM::VST1d16wb_fixed,
+<a name="l02925"></a>02925 ARM::VST1d32wb_fixed,
+<a name="l02926"></a>02926 ARM::VST1d64wb_fixed };
+<a name="l02927"></a>02927 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
+<a name="l02928"></a>02928 ARM::VST1q16wb_fixed,
+<a name="l02929"></a>02929 ARM::VST1q32wb_fixed,
+<a name="l02930"></a>02930 ARM::VST1q64wb_fixed };
+<a name="l02931"></a>02931 <span class="keywordflow">return</span> SelectVST(N, <span class="keyword">true</span>, 1, DOpcodes, QOpcodes, 0);
+<a name="l02932"></a>02932 }
+<a name="l02933"></a>02933
+<a name="l02934"></a>02934 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9af6a4c6bf81470b0f47fb5ea7d02c9422">ARMISD::VST2_UPD</a>: {
+<a name="l02935"></a>02935 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
+<a name="l02936"></a>02936 ARM::VST2d16wb_fixed,
+<a name="l02937"></a>02937 ARM::VST2d32wb_fixed,
+<a name="l02938"></a>02938 ARM::VST1q64wb_fixed};
+<a name="l02939"></a>02939 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
+<a name="l02940"></a>02940 ARM::VST2q16PseudoWB_fixed,
+<a name="l02941"></a>02941 ARM::VST2q32PseudoWB_fixed };
+<a name="l02942"></a>02942 <span class="keywordflow">return</span> SelectVST(N, <span class="keyword">true</span>, 2, DOpcodes, QOpcodes, 0);
+<a name="l02943"></a>02943 }
+<a name="l02944"></a>02944
+<a name="l02945"></a>02945 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a46ce1e04c61117e5b760e27351c2c209">ARMISD::VST3_UPD</a>: {
+<a name="l02946"></a>02946 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
+<a name="l02947"></a>02947 ARM::VST3d16Pseudo_UPD,
+<a name="l02948"></a>02948 ARM::VST3d32Pseudo_UPD,
+<a name="l02949"></a>02949 ARM::VST1d64TPseudoWB_fixed};
+<a name="l02950"></a>02950 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
+<a name="l02951"></a>02951 ARM::VST3q16Pseudo_UPD,
+<a name="l02952"></a>02952 ARM::VST3q32Pseudo_UPD };
+<a name="l02953"></a>02953 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
+<a name="l02954"></a>02954 ARM::VST3q16oddPseudo_UPD,
+<a name="l02955"></a>02955 ARM::VST3q32oddPseudo_UPD };
+<a name="l02956"></a>02956 <span class="keywordflow">return</span> SelectVST(N, <span class="keyword">true</span>, 3, DOpcodes, QOpcodes0, QOpcodes1);
+<a name="l02957"></a>02957 }
+<a name="l02958"></a>02958
+<a name="l02959"></a>02959 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a8994129f9ac9818ba7865a6df6194a15">ARMISD::VST4_UPD</a>: {
+<a name="l02960"></a>02960 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
+<a name="l02961"></a>02961 ARM::VST4d16Pseudo_UPD,
+<a name="l02962"></a>02962 ARM::VST4d32Pseudo_UPD,
+<a name="l02963"></a>02963 ARM::VST1d64QPseudoWB_fixed};
+<a name="l02964"></a>02964 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
+<a name="l02965"></a>02965 ARM::VST4q16Pseudo_UPD,
+<a name="l02966"></a>02966 ARM::VST4q32Pseudo_UPD };
+<a name="l02967"></a>02967 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
+<a name="l02968"></a>02968 ARM::VST4q16oddPseudo_UPD,
+<a name="l02969"></a>02969 ARM::VST4q32oddPseudo_UPD };
+<a name="l02970"></a>02970 <span class="keywordflow">return</span> SelectVST(N, <span class="keyword">true</span>, 4, DOpcodes, QOpcodes0, QOpcodes1);
+<a name="l02971"></a>02971 }
+<a name="l02972"></a>02972
+<a name="l02973"></a>02973 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a4fb391704986986d277b0e9f9defe47d">ARMISD::VST2LN_UPD</a>: {
+<a name="l02974"></a>02974 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
+<a name="l02975"></a>02975 ARM::VST2LNd16Pseudo_UPD,
+<a name="l02976"></a>02976 ARM::VST2LNd32Pseudo_UPD };
+<a name="l02977"></a>02977 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
+<a name="l02978"></a>02978 ARM::VST2LNq32Pseudo_UPD };
+<a name="l02979"></a>02979 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">false</span>, <span class="keyword">true</span>, 2, DOpcodes, QOpcodes);
+<a name="l02980"></a>02980 }
+<a name="l02981"></a>02981
+<a name="l02982"></a>02982 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a0e4c9035a762f061faadf268d28ed841">ARMISD::VST3LN_UPD</a>: {
+<a name="l02983"></a>02983 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
+<a name="l02984"></a>02984 ARM::VST3LNd16Pseudo_UPD,
+<a name="l02985"></a>02985 ARM::VST3LNd32Pseudo_UPD };
+<a name="l02986"></a>02986 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
+<a name="l02987"></a>02987 ARM::VST3LNq32Pseudo_UPD };
+<a name="l02988"></a>02988 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">false</span>, <span class="keyword">true</span>, 3, DOpcodes, QOpcodes);
+<a name="l02989"></a>02989 }
+<a name="l02990"></a>02990
+<a name="l02991"></a>02991 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a1d949f0d6adbeca42c5d9084223611fa">ARMISD::VST4LN_UPD</a>: {
+<a name="l02992"></a>02992 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
+<a name="l02993"></a>02993 ARM::VST4LNd16Pseudo_UPD,
+<a name="l02994"></a>02994 ARM::VST4LNd32Pseudo_UPD };
+<a name="l02995"></a>02995 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
+<a name="l02996"></a>02996 ARM::VST4LNq32Pseudo_UPD };
+<a name="l02997"></a>02997 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">false</span>, <span class="keyword">true</span>, 4, DOpcodes, QOpcodes);
+<a name="l02998"></a>02998 }
+<a name="l02999"></a>02999
+<a name="l03000"></a>03000 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a2df96794a99f5d3b4415c4a84e616140">ISD::INTRINSIC_VOID</a>:
+<a name="l03001"></a>03001 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110afc09e0bddd693dcf9923e4df42473bd9">ISD::INTRINSIC_W_CHAIN</a>: {
+<a name="l03002"></a>03002 <span class="keywordtype">unsigned</span> IntNo = cast<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1))->getZExtValue();
+<a name="l03003"></a>03003 <span class="keywordflow">switch</span> (IntNo) {
+<a name="l03004"></a>03004 <span class="keywordflow">default</span>:
+<a name="l03005"></a>03005 <span class="keywordflow">break</span>;
+<a name="l03006"></a>03006
+<a name="l03007"></a>03007 <span class="keywordflow">case</span> Intrinsic::arm_ldrexd: {
+<a name="l03008"></a>03008 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MemAddr = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2);
+<a name="l03009"></a>03009 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l03010"></a>03010 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l03011"></a>03011
+<a name="l03012"></a>03012 <span class="keywordtype">unsigned</span> NewOpc = ARM::LDREXD;
+<a name="l03013"></a>03013 <span class="keywordflow">if</span> (Subtarget->isThumb() && Subtarget->hasThumb2())
+<a name="l03014"></a>03014 NewOpc = ARM::t2LDREXD;
+<a name="l03015"></a>03015
+<a name="l03016"></a>03016 <span class="comment">// arm_ldrexd returns a i64 value in {i32, i32}</span>
+<a name="l03017"></a>03017 std::vector<EVT> ResTys;
+<a name="l03018"></a>03018 ResTys.push_back(MVT::i32);
+<a name="l03019"></a>03019 ResTys.push_back(MVT::i32);
+<a name="l03020"></a>03020 ResTys.push_back(MVT::Other);
+<a name="l03021"></a>03021
+<a name="l03022"></a>03022 <span class="comment">// place arguments in the right order</span>
+<a name="l03023"></a>03023 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 7></a> Ops;
+<a name="l03024"></a>03024 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(MemAddr);
+<a name="l03025"></a>03025 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(<a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG));
+<a name="l03026"></a>03026 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(CurDAG->getRegister(0, MVT::i32));
+<a name="l03027"></a>03027 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l03028"></a>03028 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(),
+<a name="l03029"></a>03029 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l03030"></a>03030 <span class="comment">// Transfer memoperands.</span>
+<a name="l03031"></a>03031 <a class="code" href="classllvm_1_1MachineMemOperand.html">MachineSDNode::mmo_iterator</a> MemOp = MF->allocateMemRefsArray(1);
+<a name="l03032"></a>03032 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+<a name="l03033"></a>03033 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
+<a name="l03034"></a>03034
+<a name="l03035"></a>03035 <span class="comment">// Until there's support for specifing explicit register constraints</span>
+<a name="l03036"></a>03036 <span class="comment">// like the use of even/odd register pair, hardcode ldrexd to always</span>
+<a name="l03037"></a>03037 <span class="comment">// use the pair [R0, R1] to hold the load result.</span>
+<a name="l03038"></a>03038 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
+<a name="l03039"></a>03039 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Ld, 0), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(0,0));
+<a name="l03040"></a>03040 Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
+<a name="l03041"></a>03041 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Ld, 1), Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l03042"></a>03042
+<a name="l03043"></a>03043 <span class="comment">// Remap uses.</span>
+<a name="l03044"></a>03044 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Glue = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03045"></a>03045 <span class="keywordflow">if</span> (!<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 0).use_empty()) {
+<a name="l03046"></a>03046 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
+<a name="l03047"></a>03047 ARM::R0, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Glue);
+<a name="l03048"></a>03048 Glue = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(2);
+<a name="l03049"></a>03049 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 0), Result);
+<a name="l03050"></a>03050 }
+<a name="l03051"></a>03051 <span class="keywordflow">if</span> (!<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 1).use_empty()) {
+<a name="l03052"></a>03052 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
+<a name="l03053"></a>03053 ARM::R1, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Glue);
+<a name="l03054"></a>03054 Glue = Result.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(2);
+<a name="l03055"></a>03055 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 1), Result);
+<a name="l03056"></a>03056 }
+<a name="l03057"></a>03057
+<a name="l03058"></a>03058 ReplaceUses(<a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(N, 2), <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(Ld, 2));
+<a name="l03059"></a>03059 <span class="keywordflow">return</span> NULL;
+<a name="l03060"></a>03060 }
+<a name="l03061"></a>03061
+<a name="l03062"></a>03062 <span class="keywordflow">case</span> Intrinsic::arm_strexd: {
+<a name="l03063"></a>03063 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l03064"></a>03064 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Chain = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l03065"></a>03065 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2);
+<a name="l03066"></a>03066 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Val1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(3);
+<a name="l03067"></a>03067 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> MemAddr = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(4);
+<a name="l03068"></a>03068
+<a name="l03069"></a>03069 <span class="comment">// Until there's support for specifing explicit register constraints</span>
+<a name="l03070"></a>03070 <span class="comment">// like the use of even/odd register pair, hardcode strexd to always</span>
+<a name="l03071"></a>03071 <span class="comment">// use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.</span>
+<a name="l03072"></a>03072 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
+<a name="l03073"></a>03073 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(0, 0));
+<a name="l03074"></a>03074 Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1));
+<a name="l03075"></a>03075
+<a name="l03076"></a>03076 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> Glue = Chain.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03077"></a>03077 Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
+<a name="l03078"></a>03078 ARM::R2, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Glue);
+<a name="l03079"></a>03079 Glue = Val0.<a class="code" href="classllvm_1_1SDValue.html#a040481b9bda32faa6b1435532405d88f">getValue</a>(1);
+<a name="l03080"></a>03080 Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
+<a name="l03081"></a>03081 ARM::R3, <a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50ca04cca8bc12888d0a7238f55a6c550ad0">MVT::i32</a>, Glue);
+<a name="l03082"></a>03082
+<a name="l03083"></a>03083 <span class="comment">// Store exclusive double return a i32 value which is the return status</span>
+<a name="l03084"></a>03084 <span class="comment">// of the issued store.</span>
+<a name="l03085"></a>03085 std::vector<EVT> ResTys;
+<a name="l03086"></a>03086 ResTys.push_back(MVT::i32);
+<a name="l03087"></a>03087 ResTys.push_back(MVT::Other);
+<a name="l03088"></a>03088
+<a name="l03089"></a>03089 <span class="comment">// place arguments in the right order</span>
+<a name="l03090"></a>03090 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 7></a> Ops;
+<a name="l03091"></a>03091 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Val0);
+<a name="l03092"></a>03092 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Val1);
+<a name="l03093"></a>03093 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(MemAddr);
+<a name="l03094"></a>03094 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(<a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG));
+<a name="l03095"></a>03095 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(CurDAG->getRegister(0, MVT::i32));
+<a name="l03096"></a>03096 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(Chain);
+<a name="l03097"></a>03097
+<a name="l03098"></a>03098 <span class="keywordtype">unsigned</span> NewOpc = ARM::STREXD;
+<a name="l03099"></a>03099 <span class="keywordflow">if</span> (Subtarget->isThumb() && Subtarget->hasThumb2())
+<a name="l03100"></a>03100 NewOpc = ARM::t2STREXD;
+<a name="l03101"></a>03101
+<a name="l03102"></a>03102 <a class="code" href="classllvm_1_1SDNode.html">SDNode</a> *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(),
+<a name="l03103"></a>03103 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l03104"></a>03104 <span class="comment">// Transfer memoperands.</span>
+<a name="l03105"></a>03105 <a class="code" href="classllvm_1_1MachineMemOperand.html">MachineSDNode::mmo_iterator</a> MemOp = MF->allocateMemRefsArray(1);
+<a name="l03106"></a>03106 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
+<a name="l03107"></a>03107 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
+<a name="l03108"></a>03108
+<a name="l03109"></a>03109 <span class="keywordflow">return</span> St;
+<a name="l03110"></a>03110 }
+<a name="l03111"></a>03111
+<a name="l03112"></a>03112 <span class="keywordflow">case</span> Intrinsic::arm_neon_vld1: {
+<a name="l03113"></a>03113 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
+<a name="l03114"></a>03114 ARM::VLD1d32, ARM::VLD1d64 };
+<a name="l03115"></a>03115 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
+<a name="l03116"></a>03116 ARM::VLD1q32, ARM::VLD1q64};
+<a name="l03117"></a>03117 <span class="keywordflow">return</span> SelectVLD(N, <span class="keyword">false</span>, 1, DOpcodes, QOpcodes, 0);
+<a name="l03118"></a>03118 }
+<a name="l03119"></a>03119
+<a name="l03120"></a>03120 <span class="keywordflow">case</span> Intrinsic::arm_neon_vld2: {
+<a name="l03121"></a>03121 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
+<a name="l03122"></a>03122 ARM::VLD2d32, ARM::VLD1q64 };
+<a name="l03123"></a>03123 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
+<a name="l03124"></a>03124 ARM::VLD2q32Pseudo };
+<a name="l03125"></a>03125 <span class="keywordflow">return</span> SelectVLD(N, <span class="keyword">false</span>, 2, DOpcodes, QOpcodes, 0);
+<a name="l03126"></a>03126 }
+<a name="l03127"></a>03127
+<a name="l03128"></a>03128 <span class="keywordflow">case</span> Intrinsic::arm_neon_vld3: {
+<a name="l03129"></a>03129 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
+<a name="l03130"></a>03130 ARM::VLD3d16Pseudo,
+<a name="l03131"></a>03131 ARM::VLD3d32Pseudo,
+<a name="l03132"></a>03132 ARM::VLD1d64TPseudo };
+<a name="l03133"></a>03133 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
+<a name="l03134"></a>03134 ARM::VLD3q16Pseudo_UPD,
+<a name="l03135"></a>03135 ARM::VLD3q32Pseudo_UPD };
+<a name="l03136"></a>03136 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
+<a name="l03137"></a>03137 ARM::VLD3q16oddPseudo,
+<a name="l03138"></a>03138 ARM::VLD3q32oddPseudo };
+<a name="l03139"></a>03139 <span class="keywordflow">return</span> SelectVLD(N, <span class="keyword">false</span>, 3, DOpcodes, QOpcodes0, QOpcodes1);
+<a name="l03140"></a>03140 }
+<a name="l03141"></a>03141
+<a name="l03142"></a>03142 <span class="keywordflow">case</span> Intrinsic::arm_neon_vld4: {
+<a name="l03143"></a>03143 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
+<a name="l03144"></a>03144 ARM::VLD4d16Pseudo,
+<a name="l03145"></a>03145 ARM::VLD4d32Pseudo,
+<a name="l03146"></a>03146 ARM::VLD1d64QPseudo };
+<a name="l03147"></a>03147 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
+<a name="l03148"></a>03148 ARM::VLD4q16Pseudo_UPD,
+<a name="l03149"></a>03149 ARM::VLD4q32Pseudo_UPD };
+<a name="l03150"></a>03150 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
+<a name="l03151"></a>03151 ARM::VLD4q16oddPseudo,
+<a name="l03152"></a>03152 ARM::VLD4q32oddPseudo };
+<a name="l03153"></a>03153 <span class="keywordflow">return</span> SelectVLD(N, <span class="keyword">false</span>, 4, DOpcodes, QOpcodes0, QOpcodes1);
+<a name="l03154"></a>03154 }
+<a name="l03155"></a>03155
+<a name="l03156"></a>03156 <span class="keywordflow">case</span> Intrinsic::arm_neon_vld2lane: {
+<a name="l03157"></a>03157 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
+<a name="l03158"></a>03158 ARM::VLD2LNd16Pseudo,
+<a name="l03159"></a>03159 ARM::VLD2LNd32Pseudo };
+<a name="l03160"></a>03160 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
+<a name="l03161"></a>03161 ARM::VLD2LNq32Pseudo };
+<a name="l03162"></a>03162 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">true</span>, <span class="keyword">false</span>, 2, DOpcodes, QOpcodes);
+<a name="l03163"></a>03163 }
+<a name="l03164"></a>03164
+<a name="l03165"></a>03165 <span class="keywordflow">case</span> Intrinsic::arm_neon_vld3lane: {
+<a name="l03166"></a>03166 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
+<a name="l03167"></a>03167 ARM::VLD3LNd16Pseudo,
+<a name="l03168"></a>03168 ARM::VLD3LNd32Pseudo };
+<a name="l03169"></a>03169 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
+<a name="l03170"></a>03170 ARM::VLD3LNq32Pseudo };
+<a name="l03171"></a>03171 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">true</span>, <span class="keyword">false</span>, 3, DOpcodes, QOpcodes);
+<a name="l03172"></a>03172 }
+<a name="l03173"></a>03173
+<a name="l03174"></a>03174 <span class="keywordflow">case</span> Intrinsic::arm_neon_vld4lane: {
+<a name="l03175"></a>03175 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
+<a name="l03176"></a>03176 ARM::VLD4LNd16Pseudo,
+<a name="l03177"></a>03177 ARM::VLD4LNd32Pseudo };
+<a name="l03178"></a>03178 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
+<a name="l03179"></a>03179 ARM::VLD4LNq32Pseudo };
+<a name="l03180"></a>03180 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">true</span>, <span class="keyword">false</span>, 4, DOpcodes, QOpcodes);
+<a name="l03181"></a>03181 }
+<a name="l03182"></a>03182
+<a name="l03183"></a>03183 <span class="keywordflow">case</span> Intrinsic::arm_neon_vst1: {
+<a name="l03184"></a>03184 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
+<a name="l03185"></a>03185 ARM::VST1d32, ARM::VST1d64 };
+<a name="l03186"></a>03186 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
+<a name="l03187"></a>03187 ARM::VST1q32, ARM::VST1q64 };
+<a name="l03188"></a>03188 <span class="keywordflow">return</span> SelectVST(N, <span class="keyword">false</span>, 1, DOpcodes, QOpcodes, 0);
+<a name="l03189"></a>03189 }
+<a name="l03190"></a>03190
+<a name="l03191"></a>03191 <span class="keywordflow">case</span> Intrinsic::arm_neon_vst2: {
+<a name="l03192"></a>03192 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
+<a name="l03193"></a>03193 ARM::VST2d32, ARM::VST1q64 };
+<a name="l03194"></a>03194 <span class="keyword">static</span> uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
+<a name="l03195"></a>03195 ARM::VST2q32Pseudo };
+<a name="l03196"></a>03196 <span class="keywordflow">return</span> SelectVST(N, <span class="keyword">false</span>, 2, DOpcodes, QOpcodes, 0);
+<a name="l03197"></a>03197 }
+<a name="l03198"></a>03198
+<a name="l03199"></a>03199 <span class="keywordflow">case</span> Intrinsic::arm_neon_vst3: {
+<a name="l03200"></a>03200 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
+<a name="l03201"></a>03201 ARM::VST3d16Pseudo,
+<a name="l03202"></a>03202 ARM::VST3d32Pseudo,
+<a name="l03203"></a>03203 ARM::VST1d64TPseudo };
+<a name="l03204"></a>03204 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
+<a name="l03205"></a>03205 ARM::VST3q16Pseudo_UPD,
+<a name="l03206"></a>03206 ARM::VST3q32Pseudo_UPD };
+<a name="l03207"></a>03207 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
+<a name="l03208"></a>03208 ARM::VST3q16oddPseudo,
+<a name="l03209"></a>03209 ARM::VST3q32oddPseudo };
+<a name="l03210"></a>03210 <span class="keywordflow">return</span> SelectVST(N, <span class="keyword">false</span>, 3, DOpcodes, QOpcodes0, QOpcodes1);
+<a name="l03211"></a>03211 }
+<a name="l03212"></a>03212
+<a name="l03213"></a>03213 <span class="keywordflow">case</span> Intrinsic::arm_neon_vst4: {
+<a name="l03214"></a>03214 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
+<a name="l03215"></a>03215 ARM::VST4d16Pseudo,
+<a name="l03216"></a>03216 ARM::VST4d32Pseudo,
+<a name="l03217"></a>03217 ARM::VST1d64QPseudo };
+<a name="l03218"></a>03218 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
+<a name="l03219"></a>03219 ARM::VST4q16Pseudo_UPD,
+<a name="l03220"></a>03220 ARM::VST4q32Pseudo_UPD };
+<a name="l03221"></a>03221 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
+<a name="l03222"></a>03222 ARM::VST4q16oddPseudo,
+<a name="l03223"></a>03223 ARM::VST4q32oddPseudo };
+<a name="l03224"></a>03224 <span class="keywordflow">return</span> SelectVST(N, <span class="keyword">false</span>, 4, DOpcodes, QOpcodes0, QOpcodes1);
+<a name="l03225"></a>03225 }
+<a name="l03226"></a>03226
+<a name="l03227"></a>03227 <span class="keywordflow">case</span> Intrinsic::arm_neon_vst2lane: {
+<a name="l03228"></a>03228 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
+<a name="l03229"></a>03229 ARM::VST2LNd16Pseudo,
+<a name="l03230"></a>03230 ARM::VST2LNd32Pseudo };
+<a name="l03231"></a>03231 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
+<a name="l03232"></a>03232 ARM::VST2LNq32Pseudo };
+<a name="l03233"></a>03233 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">false</span>, <span class="keyword">false</span>, 2, DOpcodes, QOpcodes);
+<a name="l03234"></a>03234 }
+<a name="l03235"></a>03235
+<a name="l03236"></a>03236 <span class="keywordflow">case</span> Intrinsic::arm_neon_vst3lane: {
+<a name="l03237"></a>03237 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
+<a name="l03238"></a>03238 ARM::VST3LNd16Pseudo,
+<a name="l03239"></a>03239 ARM::VST3LNd32Pseudo };
+<a name="l03240"></a>03240 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
+<a name="l03241"></a>03241 ARM::VST3LNq32Pseudo };
+<a name="l03242"></a>03242 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">false</span>, <span class="keyword">false</span>, 3, DOpcodes, QOpcodes);
+<a name="l03243"></a>03243 }
+<a name="l03244"></a>03244
+<a name="l03245"></a>03245 <span class="keywordflow">case</span> Intrinsic::arm_neon_vst4lane: {
+<a name="l03246"></a>03246 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
+<a name="l03247"></a>03247 ARM::VST4LNd16Pseudo,
+<a name="l03248"></a>03248 ARM::VST4LNd32Pseudo };
+<a name="l03249"></a>03249 <span class="keyword">static</span> <span class="keyword">const</span> uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
+<a name="l03250"></a>03250 ARM::VST4LNq32Pseudo };
+<a name="l03251"></a>03251 <span class="keywordflow">return</span> SelectVLDSTLane(N, <span class="keyword">false</span>, <span class="keyword">false</span>, 4, DOpcodes, QOpcodes);
+<a name="l03252"></a>03252 }
+<a name="l03253"></a>03253 }
+<a name="l03254"></a>03254 <span class="keywordflow">break</span>;
+<a name="l03255"></a>03255 }
+<a name="l03256"></a>03256
+<a name="l03257"></a>03257 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110ac771b9cda3b889242d457cc4d9b2159c">ISD::INTRINSIC_WO_CHAIN</a>: {
+<a name="l03258"></a>03258 <span class="keywordtype">unsigned</span> IntNo = cast<ConstantSDNode>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0))->getZExtValue();
+<a name="l03259"></a>03259 <span class="keywordflow">switch</span> (IntNo) {
+<a name="l03260"></a>03260 <span class="keywordflow">default</span>:
+<a name="l03261"></a>03261 <span class="keywordflow">break</span>;
+<a name="l03262"></a>03262
+<a name="l03263"></a>03263 <span class="keywordflow">case</span> Intrinsic::arm_neon_vtbl2:
+<a name="l03264"></a>03264 <span class="keywordflow">return</span> SelectVTBL(N, <span class="keyword">false</span>, 2, <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9abf641d085a1191fdfe9f91624d8078a6">ARM::VTBL2</a>);
+<a name="l03265"></a>03265 <span class="keywordflow">case</span> Intrinsic::arm_neon_vtbl3:
+<a name="l03266"></a>03266 <span class="keywordflow">return</span> SelectVTBL(N, <span class="keyword">false</span>, 3, ARM::VTBL3Pseudo);
+<a name="l03267"></a>03267 <span class="keywordflow">case</span> Intrinsic::arm_neon_vtbl4:
+<a name="l03268"></a>03268 <span class="keywordflow">return</span> SelectVTBL(N, <span class="keyword">false</span>, 4, ARM::VTBL4Pseudo);
+<a name="l03269"></a>03269
+<a name="l03270"></a>03270 <span class="keywordflow">case</span> Intrinsic::arm_neon_vtbx2:
+<a name="l03271"></a>03271 <span class="keywordflow">return</span> SelectVTBL(N, <span class="keyword">true</span>, 2, ARM::VTBX2);
+<a name="l03272"></a>03272 <span class="keywordflow">case</span> Intrinsic::arm_neon_vtbx3:
+<a name="l03273"></a>03273 <span class="keywordflow">return</span> SelectVTBL(N, <span class="keyword">true</span>, 3, ARM::VTBX3Pseudo);
+<a name="l03274"></a>03274 <span class="keywordflow">case</span> Intrinsic::arm_neon_vtbx4:
+<a name="l03275"></a>03275 <span class="keywordflow">return</span> SelectVTBL(N, <span class="keyword">true</span>, 4, ARM::VTBX4Pseudo);
+<a name="l03276"></a>03276 }
+<a name="l03277"></a>03277 <span class="keywordflow">break</span>;
+<a name="l03278"></a>03278 }
+<a name="l03279"></a>03279
+<a name="l03280"></a>03280 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a23b7689832a24fd3eea55be8583bee87">ARMISD::VTBL1</a>: {
+<a name="l03281"></a>03281 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l03282"></a>03282 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l03283"></a>03283 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 6></a> Ops;
+<a name="l03284"></a>03284
+<a name="l03285"></a>03285 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0));
+<a name="l03286"></a>03286 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1));
+<a name="l03287"></a>03287 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(<a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG)); <span class="comment">// Predicate</span>
+<a name="l03288"></a>03288 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(CurDAG->getRegister(0, MVT::i32)); <span class="comment">// Predicate Register</span>
+<a name="l03289"></a>03289 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a23b7689832a24fd3eea55be8583bee87">ARM::VTBL1</a>, dl, VT, Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l03290"></a>03290 }
+<a name="l03291"></a>03291 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9abf641d085a1191fdfe9f91624d8078a6">ARMISD::VTBL2</a>: {
+<a name="l03292"></a>03292 <a class="code" href="classllvm_1_1DebugLoc.html">DebugLoc</a> dl = N-><a class="code" href="classllvm_1_1SDNode.html#a630d6793e4444e4996dfa80f1fce18c8" title="getDebugLoc - Return the source location info.">getDebugLoc</a>();
+<a name="l03293"></a>03293 <a class="code" href="structllvm_1_1EVT.html">EVT</a> VT = N-><a class="code" href="classllvm_1_1SDNode.html#aed0958deb6d25f9fdccd7518e26b50f8">getValueType</a>(0);
+<a name="l03294"></a>03294
+<a name="l03295"></a>03295 <span class="comment">// Form a REG_SEQUENCE to force register allocation.</span>
+<a name="l03296"></a>03296 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V0 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(0);
+<a name="l03297"></a>03297 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> V1 = N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(1);
+<a name="l03298"></a>03298 <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> RegSeq = <a class="code" href="classllvm_1_1SDValue.html">SDValue</a>(PairDRegs(<a class="code" href="classllvm_1_1MVT.html#afd69b4f2dff97a2d7c0192cc769ef50cae3d1acb736016d92ec470470f1c26065">MVT::v16i8</a>, V0, V1), 0);
+<a name="l03299"></a>03299
+<a name="l03300"></a>03300 <a class="code" href="classllvm_1_1SmallVector.html">SmallVector<SDValue, 6></a> Ops;
+<a name="l03301"></a>03301 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(RegSeq);
+<a name="l03302"></a>03302 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(N-><a class="code" href="classllvm_1_1SDNode.html#a836c27481205f56e708fe0c15538d5ff">getOperand</a>(2));
+<a name="l03303"></a>03303 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(<a class="code" href="ARMISelDAGToDAG_8cpp.html#ab8c93fd1f8226d1a05590996f0928551" title="getAL - Returns a ARMCC::AL immediate node.">getAL</a>(CurDAG)); <span class="comment">// Predicate</span>
+<a name="l03304"></a>03304 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateBase.html#ae1a10b90f22c0478960fb5798ff73916">push_back</a>(CurDAG->getRegister(0, MVT::i32)); <span class="comment">// Predicate Register</span>
+<a name="l03305"></a>03305 <span class="keywordflow">return</span> CurDAG->getMachineNode(<a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9abf641d085a1191fdfe9f91624d8078a6">ARM::VTBL2</a>, dl, VT,
+<a name="l03306"></a>03306 Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a7b68be12c974b6b70bc86062f221a344" title="data - Return a pointer to the vector's buffer, even if empty().">data</a>(), Ops.<a class="code" href="classllvm_1_1SmallVectorTemplateCommon.html#a22a311dfe4c28a897de8a9365a4f0a84">size</a>());
+<a name="l03307"></a>03307 }
+<a name="l03308"></a>03308
+<a name="l03309"></a>03309 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ISD.html#a22ea9cec080dd5f4f47ba234c2f59110a320898056eadc3254fc601e1362eb9f5">ISD::CONCAT_VECTORS</a>:
+<a name="l03310"></a>03310 <span class="keywordflow">return</span> SelectConcatVector(N);
+<a name="l03311"></a>03311
+<a name="l03312"></a>03312 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a8838f473fb2d74845bad63a598784a85">ARMISD::ATOMOR64_DAG</a>:
+<a name="l03313"></a>03313 <span class="keywordflow">return</span> SelectAtomic64(N, ARM::ATOMOR6432);
+<a name="l03314"></a>03314 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9aa4475f4f0f2f28c43f2b65f2a923875c">ARMISD::ATOMXOR64_DAG</a>:
+<a name="l03315"></a>03315 <span class="keywordflow">return</span> SelectAtomic64(N, ARM::ATOMXOR6432);
+<a name="l03316"></a>03316 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9ae0f5a2c9aebaaffc2d1f4b6fa4f5d230">ARMISD::ATOMADD64_DAG</a>:
+<a name="l03317"></a>03317 <span class="keywordflow">return</span> SelectAtomic64(N, ARM::ATOMADD6432);
+<a name="l03318"></a>03318 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a347a448051be247194ad3170a73ddc4e">ARMISD::ATOMSUB64_DAG</a>:
+<a name="l03319"></a>03319 <span class="keywordflow">return</span> SelectAtomic64(N, ARM::ATOMSUB6432);
+<a name="l03320"></a>03320 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9ab4d8da8625f052200681d94e67c2d4f2">ARMISD::ATOMNAND64_DAG</a>:
+<a name="l03321"></a>03321 <span class="keywordflow">return</span> SelectAtomic64(N, ARM::ATOMNAND6432);
+<a name="l03322"></a>03322 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9ae42a9942b8bef51ce754b66658448ef6">ARMISD::ATOMAND64_DAG</a>:
+<a name="l03323"></a>03323 <span class="keywordflow">return</span> SelectAtomic64(N, ARM::ATOMAND6432);
+<a name="l03324"></a>03324 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9a9a354380775d7d3e7bddac2a61b48077">ARMISD::ATOMSWAP64_DAG</a>:
+<a name="l03325"></a>03325 <span class="keywordflow">return</span> SelectAtomic64(N, ARM::ATOMSWAP6432);
+<a name="l03326"></a>03326 <span class="keywordflow">case</span> <a class="code" href="namespacellvm_1_1ARMISD.html#a2e41e02d8e1c0ff6c5a48860e87476b9abf9b3ddadbbef9843c2e738cc52170b6">ARMISD::ATOMCMPXCHG64_DAG</a>:
+<a name="l03327"></a>03327 <span class="keywordflow">return</span> SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
+<a name="l03328"></a>03328 }
+<a name="l03329"></a>03329
+<a name="l03330"></a>03330 <span class="keywordflow">return</span> SelectCode(N);
+<a name="l03331"></a>03331 }
+<a name="l03332"></a>03332
+<a name="l03333"></a>03333 <span class="keywordtype">bool</span> ARMDAGToDAGISel::
+<a name="l03334"></a>03334 SelectInlineAsmMemoryOperand(<span class="keyword">const</span> <a class="code" href="classllvm_1_1SDValue.html">SDValue</a> &Op, <span class="keywordtype">char</span> ConstraintCode,
+<a name="l03335"></a>03335 std::vector<SDValue> &OutOps) {
+<a name="l03336"></a>03336 assert(ConstraintCode == <span class="charliteral">'m'</span> && <span class="stringliteral">"unexpected asm memory constraint"</span>);
+<a name="l03337"></a>03337 <span class="comment">// Require the address to be in a register. That is safe for all ARM</span>
+<a name="l03338"></a>03338 <span class="comment">// variants and it is hard to do anything much smarter without knowing</span>
+<a name="l03339"></a>03339 <span class="comment">// how the operand is used.</span>
+<a name="l03340"></a>03340 OutOps.push_back(Op);
+<a name="l03341"></a>03341 <span class="keywordflow">return</span> <span class="keyword">false</span>;
+<a name="l03342"></a>03342 }
+<a name="l03343"></a>03343 <span class="comment"></span>
+<a name="l03344"></a>03344 <span class="comment">/// createARMISelDag - This pass converts a legalized DAG into a</span>
+<a name="l03345"></a>03345 <span class="comment">/// ARM-specific DAG, ready for instruction scheduling.</span>
+<a name="l03346"></a>03346 <span class="comment">///</span>
+<a name="l03347"></a><a class="code" href="namespacellvm.html#aa08eb43a751faa625ac041bdbfecd851">03347</a> <span class="comment"></span><a class="code" href="classllvm_1_1FunctionPass.html">FunctionPass</a> *<a class="code" href="namespacellvm.html#aa08eb43a751faa625ac041bdbfecd851">llvm::createARMISelDag</a>(<a class="code" href="classllvm_1_1ARMBaseTargetMachine.html">ARMBaseTargetMachine</a> &TM,
+<a name="l03348"></a>03348 <a class="code" href="namespacellvm_1_1CodeGenOpt.html#a411055ea15209051c2370bbf655ec8d4">CodeGenOpt::Level</a> OptLevel) {
+<a name="l03349"></a>03349 <span class="keywordflow">return</span> <span class="keyword">new</span> ARMDAGToDAGISel(TM, OptLevel);
+<a name="l03350"></a>03350 }
+</pre></div></div>
+</div>
+<hr>
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+<a href="http://www.doxygen.org"><img src="doxygen.png" alt="Doxygen"
+align="middle" border="0"/>1.7.5.1</a><br>
+Copyright © 2003-2012 University of Illinois at Urbana-Champaign.
+All Rights Reserved.</p>
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