[llvm-commits] [llvm] r170651 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsInstrInfo.td
Akira Hatanaka
ahatanaka at mips.com
Wed Dec 19 19:52:08 PST 2012
Author: ahatanak
Date: Wed Dec 19 21:52:08 2012
New Revision: 170651
URL: http://llvm.org/viewvc/llvm-project?rev=170651&view=rev
Log:
[mips] Change the order of template parameters. Move the default parameters to
the end.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=170651&r1=170650&r2=170651&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Dec 19 21:52:08 2012
@@ -81,29 +81,28 @@
//===----------------------------------------------------------------------===//
let DecoderNamespace = "Mips64" in {
/// Arithmetic Instructions (ALU Immediate)
-def DADDi : ArithLogicI<"daddi", simm16_64, immSExt16, CPU64Regs>,
- ADDI_FM<0x18>;
-def DADDiu : ArithLogicI<"daddiu", simm16_64, immSExt16, CPU64Regs, add>,
+def DADDi : ArithLogicI<"daddi", simm16_64, CPU64Regs>, ADDI_FM<0x18>;
+def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>,
ADDI_FM<0x19>, IsAsCheapAsAMove;
-def DANDi : ArithLogicI<"andi", uimm16_64, immZExt16, CPU64Regs, and>,
+def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>,
ADDI_FM<0xc>;
def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
-def ORi64 : ArithLogicI<"ori", uimm16_64, immZExt16, CPU64Regs, or>,
+def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>,
ADDI_FM<0xd>;
-def XORi64 : ArithLogicI<"xori", uimm16_64, immZExt16, CPU64Regs, xor>,
+def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>,
ADDI_FM<0xe>;
def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
/// Arithmetic Instructions (3-Operand, R-Type)
-def DADD : ArithLogicR<"dadd", IIAlu, CPU64Regs, 1>, ADD_FM<0, 0x2c>;
-def DADDu : ArithLogicR<"daddu", IIAlu, CPU64Regs, 1, add>, ADD_FM<0, 0x2d>;
-def DSUBu : ArithLogicR<"dsubu", IIAlu, CPU64Regs, 0, sub>, ADD_FM<0, 0x2f>;
+def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>;
+def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>;
+def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>;
def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
-def AND64 : ArithLogicR<"and", IIAlu, CPU64Regs, 1, and>, ADD_FM<0, 0x24>;
-def OR64 : ArithLogicR<"or", IIAlu, CPU64Regs, 1, or>, ADD_FM<0, 0x25>;
-def XOR64 : ArithLogicR<"xor", IIAlu, CPU64Regs, 1, xor>, ADD_FM<0, 0x26>;
+def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
+def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
+def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
/// Shift Instructions
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=170651&r1=170650&r2=170651&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Dec 19 21:52:08 2012
@@ -345,8 +345,9 @@
def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
// Arithmetic and logical instructions with 3 register operands.
-class ArithLogicR<string opstr, InstrItinClass Itin, RegisterClass RC,
- bit isComm = 0, SDPatternOperator OpNode = null_frag>:
+class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0,
+ InstrItinClass Itin = NoItinerary,
+ SDPatternOperator OpNode = null_frag>:
InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> {
@@ -355,8 +356,9 @@
}
// Arithmetic and logical instructions with 2 register operands.
-class ArithLogicI<string opstr, Operand Od, PatLeaf imm_type,
- RegisterClass RC, SDPatternOperator OpNode = null_frag> :
+class ArithLogicI<string opstr, Operand Od, RegisterClass RC,
+ SDPatternOperator imm_type = null_frag,
+ SDPatternOperator OpNode = null_frag> :
InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16),
!strconcat(opstr, "\t$rt, $rs, $imm16"),
[(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> {
@@ -910,26 +912,26 @@
//===----------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate)
-def ADDiu : ArithLogicI<"addiu", simm16, immSExt16, CPURegs, add>,
+def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>,
ADDI_FM<0x9>, IsAsCheapAsAMove;
-def ADDi : ArithLogicI<"addi", simm16, immSExt16, CPURegs>, ADDI_FM<0x8>;
+def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>;
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
-def ANDi : ArithLogicI<"andi", uimm16, immZExt16, CPURegs, and>, ADDI_FM<0xc>;
-def ORi : ArithLogicI<"ori", uimm16, immZExt16, CPURegs, or>, ADDI_FM<0xd>;
-def XORi : ArithLogicI<"xori", uimm16, immZExt16, CPURegs, xor>, ADDI_FM<0xe>;
+def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>;
+def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>;
+def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>;
def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
/// Arithmetic Instructions (3-Operand, R-Type)
-def ADDu : ArithLogicR<"addu", IIAlu, CPURegs, 1, add>, ADD_FM<0, 0x21>;
-def SUBu : ArithLogicR<"subu", IIAlu, CPURegs, 0, sub>, ADD_FM<0, 0x23>;
-def ADD : ArithLogicR<"add", IIAlu, CPURegs, 1>, ADD_FM<0, 0x20>;
-def SUB : ArithLogicR<"sub", IIAlu, CPURegs, 0>, ADD_FM<0, 0x22>;
+def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>;
+def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
+def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>;
+def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>;
def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
-def AND : ArithLogicR<"and", IIAlu, CPURegs, 1, and>, ADD_FM<0, 0x24>;
-def OR : ArithLogicR<"or", IIAlu, CPURegs, 1, or>, ADD_FM<0, 0x25>;
-def XOR : ArithLogicR<"xor", IIAlu, CPURegs, 1, xor>, ADD_FM<0, 0x26>;
+def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
+def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
+def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
/// Shift Instructions
@@ -1054,7 +1056,7 @@
// MUL is a assembly macro in the current used ISAs. In recent ISA's
// it is a real instruction.
-def MUL : ArithLogicR<"mul", IIImul, CPURegs, 1, mul>, ADD_FM<0x1c, 0x02>;
+def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 0x02>;
def RDHWR : ReadHardware<CPURegs, HWRegs>;
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