[llvm-commits] [llvm] r170593 - /llvm/trunk/lib/Target/R600/SIRegisterInfo.td

[Tom Stellard]

Author: tstellar
Date: Wed Dec 19 16:10:34 2012
New Revision: 170593

URL: http://llvm.org/viewvc/llvm-project?rev=170593&view=rev
Log:
R600: Remove unecessary VREG alignment.

Unlike SGPRs VGPRs doesn't need to be aligned.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
Signed-off-by: Christian König <deathsimple at vodafone.de>

Modified:
    llvm/trunk/lib/Target/R600/SIRegisterInfo.td

Modified: llvm/trunk/lib/Target/R600/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIRegisterInfo.td?rev=170593&r1=170592&r2=170593&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIRegisterInfo.td Wed Dec 19 16:10:34 2012
@@ -105,15 +105,15 @@
 
 // VGPR 64-bit registers
 def VGPR_64 : RegisterTuples<[low, high],
-                             [(add (decimate VGPR_32, 2)),
-                              (add (decimate (rotl VGPR_32, 1), 2))]>;
+                             [(add VGPR_32),
+                              (add (rotl VGPR_32, 1))]>;
 
 // VGPR 128-bit registers
 def VGPR_128 : RegisterTuples<[sel_x, sel_y, sel_z, sel_w],
-                              [(add (decimate VGPR_32, 4)),
-                               (add (decimate (rotl VGPR_32, 1), 4)),
-                               (add (decimate (rotl VGPR_32, 2), 4)),
-                               (add (decimate (rotl VGPR_32, 3), 4))]>;
+                              [(add VGPR_32),
+                               (add (rotl VGPR_32, 1)),
+                               (add (rotl VGPR_32, 2)),
+                               (add (rotl VGPR_32, 3))]>;
 
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,