[llvm-commits] [llvm] r170592 - /llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp

[Tom Stellard]

Author: tstellar
Date: Wed Dec 19 16:10:33 2012
New Revision: 170592

URL: http://llvm.org/viewvc/llvm-project?rev=170592&view=rev
Log:
R600: control flow optimization

Branch if we have enough instructions so that it makes sense.
Also remove branches if they don't make sense.

Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
Tested-by: Michel Dänzer <michel.daenzer at amd.com>
Signed-off-by: Christian König <deathsimple at vodafone.de>

Modified:
    llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp

Modified: llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp?rev=170592&r1=170591&r2=170592&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp (original)
+++ llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp Wed Dec 19 16:10:33 2012
@@ -63,9 +63,13 @@
 class SILowerControlFlowPass : public MachineFunctionPass {
 
 private:
+  static const unsigned SkipThreshold = 12;
+
   static char ID;
   const TargetInstrInfo *TII;
 
+  void Skip(MachineInstr &MI, MachineOperand &To);
+
   void If(MachineInstr &MI);
   void Else(MachineInstr &MI);
   void Break(MachineInstr &MI);
@@ -74,6 +78,8 @@
   void Loop(MachineInstr &MI);
   void EndCf(MachineInstr &MI);
 
+  void Branch(MachineInstr &MI);
+
 public:
   SILowerControlFlowPass(TargetMachine &tm) :
     MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
@@ -94,6 +100,31 @@
   return new SILowerControlFlowPass(tm);
 }
 
+void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
+
+  unsigned NumInstr = 0;
+
+  for (MachineBasicBlock *MBB = *From.getParent()->succ_begin();
+       NumInstr < SkipThreshold && MBB != To.getMBB() && !MBB->succ_empty();
+       MBB = *MBB->succ_begin()) {
+
+    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
+         NumInstr < SkipThreshold && I != E; ++I) {
+
+      if (I->isBundle() || !I->isBundled())
+        ++NumInstr;
+    }
+  }
+
+  if (NumInstr < SkipThreshold)
+    return;
+
+  DebugLoc DL = From.getDebugLoc();
+  BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
+          .addOperand(To)
+          .addReg(AMDGPU::EXEC);
+}
+
 void SILowerControlFlowPass::If(MachineInstr &MI) {
 
   MachineBasicBlock &MBB = *MI.getParent();
@@ -108,6 +139,8 @@
           .addReg(AMDGPU::EXEC)
           .addReg(Reg);
 
+  Skip(MI, MI.getOperand(2));
+
   MI.eraseFromParent();
 }
 
@@ -125,6 +158,8 @@
           .addReg(AMDGPU::EXEC)
           .addReg(Dst);
 
+  Skip(MI, MI.getOperand(2));
+
   MI.eraseFromParent();
 }
 
@@ -206,6 +241,16 @@
   MI.eraseFromParent();
 }
 
+void SILowerControlFlowPass::Branch(MachineInstr &MI) {
+
+  MachineBasicBlock *Next = MI.getParent()->getNextNode();
+  MachineBasicBlock *Target = MI.getOperand(0).getMBB();
+  if (Target == Next)
+    MI.eraseFromParent();
+  else
+    assert(0);
+}
+
 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
 
   bool HaveCf = false;
@@ -249,6 +294,10 @@
           HaveCf = true;
           EndCf(MI);
           break;
+
+        case AMDGPU::S_BRANCH:
+          Branch(MI);
+          break;
       }
     }
   }