[llvm-commits] [PATCH] Disable ARM partial flag dependency optimization at -Oz

[Quentin Colombet]

Hi,

To not over constrain the scheduler for ARM in thumb mode, some optimizations  for code size reduction, specific to ARM thumb, are blocked when they add a dependency (like write after read dependency).

This patch disables this check when code size is the priority, i.e., code is compiled with -Oz.

The patch also contains a test case.

http://llvm-reviews.chandlerc.com/D219

Files:
  test/CodeGen/ARM/avoid-cpsr-rmw.ll
  lib/Target/ARM/Thumb2SizeReduction.cpp

Index: test/CodeGen/ARM/avoid-cpsr-rmw.ll
===================================================================
--- test/CodeGen/ARM/avoid-cpsr-rmw.ll
+++ test/CodeGen/ARM/avoid-cpsr-rmw.ll
@@ -49,3 +49,37 @@
 while.end:
   ret void
 }
+
+; Allow partial CPSR dependency when code size is the priority.
+; rdar://12878928
+define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
+entry:
+; CHECK: t3:
+  %tobool7 = icmp eq i32* %ptr2, null
+  br i1 %tobool7, label %while.end, label %while.body
+
+while.body:
+; CHECK: while.body
+; CHECK: mul r{{[0-9]+}}
+; CHECK: muls
+  %ptr1.addr.09 = phi i32* [ %add.ptr, %while.body ], [ %ptr1, %entry ]
+  %ptr2.addr.08 = phi i32* [ %incdec.ptr, %while.body ], [ %ptr2, %entry ]
+  %0 = load i32* %ptr1.addr.09, align 4
+  %arrayidx1 = getelementptr inbounds i32* %ptr1.addr.09, i32 1
+  %1 = load i32* %arrayidx1, align 4
+  %arrayidx3 = getelementptr inbounds i32* %ptr1.addr.09, i32 2
+  %2 = load i32* %arrayidx3, align 4
+  %arrayidx4 = getelementptr inbounds i32* %ptr1.addr.09, i32 3
+  %3 = load i32* %arrayidx4, align 4
+  %add.ptr = getelementptr inbounds i32* %ptr1.addr.09, i32 4
+  %mul = mul i32 %1, %0
+  %mul5 = mul i32 %mul, %2
+  %mul6 = mul i32 %mul5, %3
+  store i32 %mul6, i32* %ptr2.addr.08, align 4
+  %incdec.ptr = getelementptr inbounds i32* %ptr2.addr.08, i32 -1
+  %tobool = icmp eq i32* %incdec.ptr, null
+  br i1 %tobool, label %while.end, label %while.body
+
+while.end:
+  ret void
+}
Index: lib/Target/ARM/Thumb2SizeReduction.cpp
===================================================================
--- lib/Target/ARM/Thumb2SizeReduction.cpp
+++ lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -22,6 +22,7 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Function.h"        // To access Function attributes
 using namespace llvm;
 
 STATISTIC(NumNarrows,  "Number of 32-bit instrs reduced to 16-bit ones");
@@ -216,8 +217,24 @@
 bool
 Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use,
                                       bool FirstInSelfLoop) {
-  // FIXME: Disable check for -Oz (aka OptimizeForSizeHarder).
-  if (!STI->avoidCPSRPartialUpdate())
+  // When -Oz is set, the function carries MinSize attribute.
+  bool MinimizeSize = false;
+
+  // Grab the function.
+  MachineInstr *LinkToFunction = Def;
+  if (!LinkToFunction)
+    LinkToFunction = Use;
+  
+  if (LinkToFunction) {
+    const MachineBasicBlock *MBB = LinkToFunction->getParent();
+    assert(MBB && "Optimizing an instruction that does not belong to anything?!");
+    const Function *Fn = MBB->getParent()->getFunction();
+    // Grab the attribute
+    MinimizeSize = Fn->getFnAttributes().hasAttribute(Attributes::MinSize);
+  }
+
+  // Disable the check for -Oz (aka OptimizeForSizeHarder).
+  if (!STI->avoidCPSRPartialUpdate() || MinimizeSize)
     return false;
 
   if (!Def)
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