[llvm-commits] [llvm] r170327 - in /llvm/trunk: lib/Target/XCore/XCoreInstrInfo.td test/MC/Disassembler/XCore/xcore.txt

[Richard Osborne]

Author: friedgold
Date: Mon Dec 17 07:20:37 2012
New Revision: 170327

URL: http://llvm.org/viewvc/llvm-project?rev=170327&view=rev
Log:
Add instruction encodings for ZEXT and SEXT.

Previously these were marked with the wrong format.

Modified:
    llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
    llvm/trunk/test/MC/Disassembler/XCore/xcore.txt

Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=170327&r1=170326&r2=170327&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Mon Dec 17 07:20:37 2012
@@ -764,20 +764,20 @@
                       [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
                                                          immBitp:$src2))]>;
 
-def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
-                     "sext $dst, $src2",
-                     [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
-                                                        GRRegs:$src2))]>;
+def SEXT_2r :
+  _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
+             "sext $dst, $src2",
+             [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
 
 def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
                       "zext $dst, $src2",
                       [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
                                                          immBitp:$src2))]>;
 
-def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src2, GRRegs:$src1),
-                     "zext $dst, $src2",
-                     [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
-                                                        GRRegs:$src2))]>;
+def ZEXT_2r :
+  _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
+             "zext $dst, $src2",
+             [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
 
 def ANDNOT_2r :
   _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),

Modified: llvm/trunk/test/MC/Disassembler/XCore/xcore.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/XCore/xcore.txt?rev=170327&r1=170326&r2=170327&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/XCore/xcore.txt (original)
+++ llvm/trunk/test/MC/Disassembler/XCore/xcore.txt Mon Dec 17 07:20:37 2012
@@ -132,3 +132,9 @@
 
 # CHECK: setpsc res[r8], r2
 0x28 0xc7
+
+# CHECK: zext r3, r8
+0x2c 0x47
+
+# CHECK: sext r9, r1
+0x45 0x37