[llvm-commits] [llvm] r170209 - in /llvm/trunk: include/llvm/MC/MCExpr.h include/llvm/Support/ELF.h lib/MC/MCExpr.cpp lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/PowerPC/PPCCodeEmitter.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.h lib/Target/PowerPC/PPCInstr64Bit.td lib/Target/PowerPC/PPCInstrInfo.td test/CodeGen/PowerPC/tls-ie-obj.ll test/CodeGen/PowerPC/tls-ie.ll
Bill Schmidt
wschmidt at linux.vnet.ibm.com
Fri Dec 14 09:02:38 PST 2012
Author: wschmidt
Date: Fri Dec 14 11:02:38 2012
New Revision: 170209
URL: http://llvm.org/viewvc/llvm-project?rev=170209&view=rev
Log:
This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x at got@tprel(2)
add 9,9,x at tls
New sequence:
addis 9,2,x at got@tprel at ha
ld 9,x at got@tprel at l(9)
add 9,9,x at tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
Modified:
llvm/trunk/include/llvm/MC/MCExpr.h
llvm/trunk/include/llvm/Support/ELF.h
llvm/trunk/lib/MC/MCExpr.cpp
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
llvm/trunk/test/CodeGen/PowerPC/tls-ie-obj.ll
llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll
Modified: llvm/trunk/include/llvm/MC/MCExpr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCExpr.h (original)
+++ llvm/trunk/include/llvm/MC/MCExpr.h Fri Dec 14 11:02:38 2012
@@ -183,7 +183,8 @@
VK_PPC_DTPREL16_LO, // symbol at dtprel@l
VK_PPC_TOC16_HA, // symbol at toc@ha
VK_PPC_TOC16_LO, // symbol at toc@l
- VK_PPC_GOT_TPREL16_DS, // symbol at got@tprel
+ VK_PPC_GOT_TPREL16_HA, // symbol at got@tprel at ha
+ VK_PPC_GOT_TPREL16_LO, // symbol at got@tprel at l
VK_PPC_TLS, // symbol at tls
VK_PPC_GOT_TLSGD16_HA, // symbol at got@tlsgd at ha
VK_PPC_GOT_TLSGD16_LO, // symbol at got@tlsgd at l
Modified: llvm/trunk/include/llvm/Support/ELF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/ELF.h?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/ELF.h (original)
+++ llvm/trunk/include/llvm/Support/ELF.h Fri Dec 14 11:02:38 2012
@@ -484,7 +484,8 @@
R_PPC64_GOT_TLSGD16_HA = 82,
R_PPC64_GOT_TLSLD16_LO = 84,
R_PPC64_GOT_TLSLD16_HA = 86,
- R_PPC64_GOT_TPREL16_DS = 87,
+ R_PPC64_GOT_TPREL16_LO_DS = 88,
+ R_PPC64_GOT_TPREL16_HA = 90,
R_PPC64_TLSGD = 107,
R_PPC64_TLSLD = 108
};
Modified: llvm/trunk/lib/MC/MCExpr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCExpr.cpp (original)
+++ llvm/trunk/lib/MC/MCExpr.cpp Fri Dec 14 11:02:38 2012
@@ -217,7 +217,8 @@
case VK_PPC_DTPREL16_LO: return "dtprel at l";
case VK_PPC_TOC16_HA: return "toc at ha";
case VK_PPC_TOC16_LO: return "toc at l";
- case VK_PPC_GOT_TPREL16_DS: return "got at tprel";
+ case VK_PPC_GOT_TPREL16_HA: return "got at tprel@ha";
+ case VK_PPC_GOT_TPREL16_LO: return "got at tprel@l";
case VK_PPC_TLS: return "tls";
case VK_PPC_GOT_TLSGD16_HA: return "got at tlsgd@ha";
case VK_PPC_GOT_TLSGD16_LO: return "got at tlsgd@l";
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp Fri Dec 14 11:02:38 2012
@@ -88,6 +88,9 @@
case MCSymbolRefExpr::VK_PPC_TOC16_HA:
Type = ELF::R_PPC64_TOC16_HA;
break;
+ case MCSymbolRefExpr::VK_PPC_GOT_TPREL16_HA:
+ Type = ELF::R_PPC64_GOT_TPREL16_HA;
+ break;
case MCSymbolRefExpr::VK_PPC_GOT_TLSGD16_HA:
Type = ELF::R_PPC64_GOT_TLSGD16_HA;
break;
@@ -137,8 +140,8 @@
case MCSymbolRefExpr::VK_PPC_TOC16_LO:
Type = ELF::R_PPC64_TOC16_LO_DS;
break;
- case MCSymbolRefExpr::VK_PPC_GOT_TPREL16_DS:
- Type = ELF::R_PPC64_GOT_TPREL16_DS;
+ case MCSymbolRefExpr::VK_PPC_GOT_TPREL16_LO:
+ Type = ELF::R_PPC64_GOT_TPREL16_LO_DS;
break;
}
break;
Modified: llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp Fri Dec 14 11:02:38 2012
@@ -63,8 +63,6 @@
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getTLSOffsetEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
@@ -212,17 +210,6 @@
}
-unsigned PPCMCCodeEmitter::getTLSOffsetEncoding(const MCInst &MI, unsigned OpNo,
- SmallVectorImpl<MCFixup> &Fixups) const {
- const MCOperand &MO = MI.getOperand(OpNo);
-
- // Add a fixup for the GOT displacement to the TLS block offset.
- Fixups.push_back(MCFixup::Create(0, MO.getExpr(),
- (MCFixupKind)PPC::fixup_ppc_toc16_ds));
- return 0;
-}
-
-
unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Dec 14 11:02:38 2012
@@ -513,8 +513,24 @@
OutStreamer.EmitInstruction(TmpInst);
return;
}
- case PPC::LDgotTPREL: {
- // Transform %Xd = LDgotTPREL <ga:@sym>, %Xs
+ case PPC::ADDISgotTprelHA: {
+ // Transform: %Xd = ADDISgotTprelHA %X2, <ga:@sym>
+ // Into: %Xd = ADDIS8 %X2, sym at got@tlsgd at ha
+ assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
+ const MachineOperand &MO = MI->getOperand(2);
+ const GlobalValue *GValue = MO.getGlobal();
+ MCSymbol *MOSymbol = Mang->getSymbol(GValue);
+ const MCExpr *SymGotTprel =
+ MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL16_HA,
+ OutContext);
+ OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
+ .addReg(MI->getOperand(0).getReg())
+ .addReg(PPC::X2)
+ .addExpr(SymGotTprel));
+ return;
+ }
+ case PPC::LDgotTprelL: {
+ // Transform %Xd = LDgotTprelL <ga:@sym>, %Xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LDrs, which is a form of LD with the offset
@@ -524,7 +540,7 @@
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *Exp =
- MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL16_DS,
+ MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL16_LO,
OutContext);
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
Modified: llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCCodeEmitter.cpp Fri Dec 14 11:02:38 2012
@@ -68,7 +68,6 @@
unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
- unsigned getTLSOffsetEncoding(const MachineInstr &MI, unsigned OpNo) const;
unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
@@ -245,13 +244,6 @@
}
-unsigned PPCCodeEmitter::getTLSOffsetEncoding(const MachineInstr &MI,
- unsigned OpNo) const {
- llvm_unreachable("TLS not supported on the old JIT.");
- return 0;
-}
-
-
unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI,
unsigned OpNo) const {
llvm_unreachable("TLS not supported on the old JIT.");
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 14 11:02:38 2012
@@ -578,7 +578,8 @@
case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
- case PPCISD::LD_GOT_TPREL: return "PPCISD::LD_GOT_TPREL";
+ case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
+ case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
@@ -1353,8 +1354,10 @@
if (Model == TLSModel::InitialExec) {
SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
- SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL, dl,
- PtrVT, TGA, GOTReg);
+ SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
+ PtrVT, GOTReg, TGA);
+ SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
+ PtrVT, TGA, TPOffsetHi);
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
}
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Fri Dec 14 11:02:38 2012
@@ -178,11 +178,16 @@
CR6SET,
CR6UNSET,
- /// G8RC = LD_GOT_TPREL Symbol, G8RReg - Used by the initial-exec
+ /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
+ /// TLS model, produces an ADDIS8 instruction that adds the GOT
+ /// base to sym at got@tprel at ha.
+ ADDIS_GOT_TPREL_HA,
+
+ /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
/// TLS model, produces a LD instruction with base register G8RReg
- /// and offset sym at got@tprel. The latter identifies the GOT entry
- /// containing the offset of "sym" relative to the thread pointer.
- LD_GOT_TPREL,
+ /// and offset sym at got@tprel at l. This completes the addition that
+ /// finds the offset of "sym" relative to the thread pointer.
+ LD_GOT_TPREL_L,
/// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
/// model, produces an ADD instruction that adds the contents of
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Fri Dec 14 11:02:38 2012
@@ -37,9 +37,6 @@
let EncoderMethod = "getMemRIXEncoding";
let MIOperandInfo = (ops symbolLo64:$off, ptr_rc:$reg);
}
-def tlsaddr : Operand<i64> {
- let EncoderMethod = "getTLSOffsetEncoding";
-}
def tlsreg : Operand<i64> {
let EncoderMethod = "getTLSRegEncoding";
}
@@ -720,11 +717,17 @@
(PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64;
// Support for thread-local storage.
-def LDgotTPREL: Pseudo<(outs G8RC:$rD), (ins tlsaddr:$disp, G8RC:$reg),
- "#LDgotTPREL",
- [(set G8RC:$rD,
- (PPCldGotTprel tglobaltlsaddr:$disp, G8RC:$reg))]>,
- isPPC64;
+def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
+ "#ADDISgotTprelHA",
+ [(set G8RC:$rD,
+ (PPCaddisGotTprelHA G8RC:$reg,
+ tglobaltlsaddr:$disp))]>,
+ isPPC64;
+def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg),
+ "#LDgotTprelL",
+ [(set G8RC:$rD,
+ (PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>,
+ isPPC64;
def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g),
(ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>;
def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Fri Dec 14 11:02:38 2012
@@ -91,7 +91,9 @@
def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
-def PPCldGotTprel : SDNode<"PPCISD::LD_GOT_TPREL", SDTIntBinOp, [SDNPMayLoad]>;
+def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>;
+def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp,
+ [SDNPMayLoad]>;
def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>;
def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>;
def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>;
Modified: llvm/trunk/test/CodeGen/PowerPC/tls-ie-obj.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-ie-obj.ll?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-ie-obj.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-ie-obj.ll Fri Dec 14 11:02:38 2012
@@ -24,9 +24,13 @@
; CHECK: Relocation 0
; CHECK-NEXT: 'r_offset'
; CHECK-NEXT: 'r_sym', 0x[[SYM1:[0-9a-f]+]]
-; CHECK-NEXT: 'r_type', 0x00000057
+; CHECK-NEXT: 'r_type', 0x0000005a
; CHECK: Relocation 1
; CHECK-NEXT: 'r_offset'
; CHECK-NEXT: 'r_sym', 0x[[SYM1]]
+; CHECK-NEXT: 'r_type', 0x00000058
+; CHECK: Relocation 2
+; CHECK-NEXT: 'r_offset'
+; CHECK-NEXT: 'r_sym', 0x[[SYM1]]
; CHECK-NEXT: 'r_type', 0x00000043
Modified: llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll?rev=170209&r1=170208&r2=170209&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls-ie.ll Fri Dec 14 11:02:38 2012
@@ -16,6 +16,7 @@
ret i32 %0
}
-; CHECK: ld [[REG:[0-9]+]], a at got@tprel(2)
-; CHECK: add {{[0-9]+}}, [[REG]], a at tls
+; CHECK: addis [[REG1:[0-9]+]], 2, a at got@tprel at ha
+; CHECK: ld [[REG2:[0-9]+]], a at got@tprel at l([[REG1]])
+; CHECK: add {{[0-9]+}}, [[REG2]], a at tls
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