[llvm-commits] [PATCH] Make '-mtune=x86_64' assume fast unaligned memory accesses.

[Dan Gohman]

Makes sense to me.

Dan

On Mon, Dec 10, 2012 at 1:27 AM, Chandler Carruth <chandlerc at gmail.com> wrote:
> Not all chips targeted by x86_64 have this feature, but a dramatically
> increasing number do. Specifying a chip-specific tuning parameter will
> continue to turn the feature on or off as appropriate for that
> particular chip, but the generic flag should try to achieve the best
> performance on the most widely available hardware. Today, the number of
> chips with fast UA access dwarfs those without in the x86-64 space.
>
> Note that this also brings LLVM's code generation for this '-march' flag
> more in line with that of modern GCCs.
>
> http://llvm-reviews.chandlerc.com/D195
>
> Files:
>   lib/Target/X86/X86.td
>
> Index: lib/Target/X86/X86.td
> ===================================================================
> --- lib/Target/X86/X86.td
> +++ lib/Target/X86/X86.td
> @@ -155,7 +155,8 @@
>  def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
>  def : Proc<"pentium4",        [FeatureSSE2]>;
>  def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
> -def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
> +def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem,
> +                               FeatureFastUAMem]>;
>  def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
>  def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
>  def : Proc<"nocona",          [FeatureSSE3, FeatureCMPXCHG16B,
>
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