[llvm-commits] [PATCH] Simplify negated bit test

[David Majnemer]

Reply is inline.


On Sun, Dec 9, 2012 at 6:57 AM, Jakub Staszak <kubastaszak at gmail.com> wrote:

> Hi David,
>
> In general your patch looks fine for me, but I see some areas for the
> improvement:
> 1. Your patch works only one way:
> (1 << x)&~y != 0  into (1 << x)&y == 0, however
> (1 << x)&~y == 0  into (1 << x)&y != 0 is not supported.
>

Thanks, I will add this case.


>
> 2. It doesn't have to be 1 which is shifted. It works with any
> power-of-two value (you can use m_Power2 pattern).
>
I was under the impression that m_Power2 does not handle values generated
from shl instructions.
Further, it seems that LLVM already turns !!(~A & C) into !(A & C) where C
is a constant and a power of 2. Should I add such a transform anyway?


>
> - Kuba
>
> On Dec 9, 2012, at 12:53 AM, David Majnemer <david.majnemer at gmail.com>
> wrote:
>
> > The attached patched takes a sequence like:
> >  %neg = xor i32 %A, -1
> >  %shl = shl i32 1, %B
> >  %and = and i32 %shl, %neg
> >  %cmp = icmp ne i32 %and, 0
> >
> > and turns it into:
> >  %shl = shl i32 1, %B
> >  %and = and i32 %shl, %A
> >  %cmp = icmp eq i32 %and, 0
> >
> > The patch includes a test case that exercises this transform.
> >
> > Examples of frontend code that could generate sequence 1 is:
> >
> > bool fun1(unsigned A, unsigned B) { return ~A & (1 << B); }
> >
> > An example of sequence 2 is:
> > bool fun2(unsigned A, unsigned B) { return !(A & (1 << B)); }
> >
> > With this patch, they would have the same IR.
> > <bit_test.patch>_______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
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