[llvm-commits] [llvm] r169634 - in /llvm/trunk: lib/Target/Hexagon/HexagonHardwareLoops.cpp test/CodeGen/Hexagon/postinc-load.ll

[Matthew Curtis]

Author: mcurtis
Date: Fri Dec  7 15:03:15 2012
New Revision: 169634

URL: http://llvm.org/viewvc/llvm-project?rev=169634&view=rev
Log:
In hexagon convertToHardwareLoop, don't deref end() iterator

In particular, check if MachineBasicBlock::iterator is end() before
using it to call getDebugLoc();

See also this thread on llvm-commits:
   http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121112/155914.html

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
    llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll

Modified: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp?rev=169634&r1=169633&r2=169634&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp Fri Dec  7 15:03:15 2012
@@ -461,6 +461,9 @@
     return false;
   }
   MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
+  if (LastI == LastMBB->end()) {
+    return false;
+  }
 
   // Determine the loop start.
   MachineBasicBlock *LoopStart = L->getTopBlock();
@@ -478,6 +481,9 @@
 
   // Convert the loop to a hardware loop
   DEBUG(dbgs() << "Change to hardware loop at "; L->dump());
+  DebugLoc InsertPosDL;
+  if (InsertPos != Preheader->end())
+    InsertPosDL = InsertPos->getDebugLoc();
 
   if (TripCount->isReg()) {
     // Create a copy of the loop count register.
@@ -485,23 +491,23 @@
     const TargetRegisterClass *RC =
       MF->getRegInfo().getRegClass(TripCount->getReg());
     unsigned CountReg = MF->getRegInfo().createVirtualRegister(RC);
-    BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
+    BuildMI(*Preheader, InsertPos, InsertPosDL,
             TII->get(TargetOpcode::COPY), CountReg).addReg(TripCount->getReg());
     if (TripCount->isNeg()) {
       unsigned CountReg1 = CountReg;
       CountReg = MF->getRegInfo().createVirtualRegister(RC);
-      BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
+      BuildMI(*Preheader, InsertPos, InsertPosDL,
               TII->get(Hexagon::NEG), CountReg).addReg(CountReg1);
     }
 
     // Add the Loop instruction to the beginning of the loop.
-    BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
+    BuildMI(*Preheader, InsertPos, InsertPosDL,
             TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg);
   } else {
     assert(TripCount->isImm() && "Expecting immedate vaule for trip count");
     // Add the Loop immediate instruction to the beginning of the loop.
     int64_t CountImm = TripCount->getImm();
-    BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
+    BuildMI(*Preheader, InsertPos, InsertPosDL,
             TII->get(Hexagon::LOOP0_i)).addMBB(LoopStart).addImm(CountImm);
   }
 
@@ -514,8 +520,9 @@
   BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
 
   // Replace the loop branch with an endloop instruction.
-  DebugLoc dl = LastI->getDebugLoc();
-  BuildMI(*LastMBB, LastI, dl, TII->get(Hexagon::ENDLOOP0)).addMBB(LoopStart);
+  DebugLoc LastIDL = LastI->getDebugLoc();
+  BuildMI(*LastMBB, LastI, LastIDL,
+          TII->get(Hexagon::ENDLOOP0)).addMBB(LoopStart);
 
   // The loop ends with either:
   //  - a conditional branch followed by an unconditional branch, or
@@ -530,7 +537,7 @@
         TII->RemoveBranch(*LastMBB);
       }
       SmallVector<MachineOperand, 0> Cond;
-      TII->InsertBranch(*LastMBB, BranchTarget, 0, Cond, dl);
+      TII->InsertBranch(*LastMBB, BranchTarget, 0, Cond, LastIDL);
     }
   } else {
     // Conditional branch to loop start; just delete it.

Modified: llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll?rev=169634&r1=169633&r2=169634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/postinc-load.ll Fri Dec  7 15:03:15 2012
@@ -1,4 +1,4 @@
-; RUN: true || llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
 
 ; Check that post-increment load instructions are being generated.
 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}++{{ *}}#4{{ *}})