[llvm-commits] [llvm] r169577 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsCondMov.td MipsInstrInfo.td
Akira Hatanaka
ahatanaka at mips.com
Thu Dec 6 19:01:24 PST 2012
Author: ahatanak
Date: Thu Dec 6 21:01:24 2012
New Revision: 169577
URL: http://llvm.org/viewvc/llvm-project?rev=169577&view=rev
Log:
[mips] Remove unnecessary predicates.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsCondMov.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=169577&r1=169576&r2=169577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Thu Dec 6 21:01:24 2012
@@ -66,7 +66,7 @@
}
}
}
-let usesCustomInserter = 1, Predicates = [HasMips64, HasStandardEncoding],
+let usesCustomInserter = 1, Predicates = [HasStandardEncoding],
DecoderNamespace = "Mips64" in {
defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
Modified: llvm/trunk/lib/Target/Mips/MipsCondMov.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCondMov.td?rev=169577&r1=169576&r2=169577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCondMov.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsCondMov.td Thu Dec 6 21:01:24 2012
@@ -107,7 +107,7 @@
// Instantiation of instructions.
def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
-let Predicates = [HasMips64, HasStandardEncoding],
+let Predicates = [HasStandardEncoding],
DecoderNamespace = "Mips64" in {
def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> {
@@ -119,7 +119,7 @@
}
def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
-let Predicates = [HasMips64, HasStandardEncoding],
+let Predicates = [HasStandardEncoding],
DecoderNamespace = "Mips64" in {
def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn"> {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=169577&r1=169576&r2=169577&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Dec 6 21:01:24 2012
@@ -1084,7 +1084,7 @@
// MUL is a assembly macro in the current used ISAs. In recent ISA's
// it is a real instruction.
def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
- Requires<[HasMips32, HasStandardEncoding]>;
+ Requires<[HasStandardEncoding]>;
def RDHWR : ReadHardware<CPURegs, HWRegs>;
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