[llvm-commits] [llvm] r169173 - in /llvm/trunk/lib/CodeGen: AllocationOrder.cpp AllocationOrder.h
Jakob Stoklund Olesen
stoklund at 2pi.dk
Mon Dec 3 14:51:04 PST 2012
Author: stoklund
Date: Mon Dec 3 16:51:04 2012
New Revision: 169173
URL: http://llvm.org/viewvc/llvm-project?rev=169173&view=rev
Log:
Use the new getRegAllocationHints() hook from AllocationOrder.
This simplifies the hinting code quite a bit while making the targets
easier to write at the same time.
Modified:
llvm/trunk/lib/CodeGen/AllocationOrder.cpp
llvm/trunk/lib/CodeGen/AllocationOrder.h
Modified: llvm/trunk/lib/CodeGen/AllocationOrder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AllocationOrder.cpp?rev=169173&r1=169172&r2=169173&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AllocationOrder.cpp (original)
+++ llvm/trunk/lib/CodeGen/AllocationOrder.cpp Mon Dec 3 16:51:04 2012
@@ -14,10 +14,15 @@
//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "regalloc"
#include "AllocationOrder.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -25,56 +30,36 @@
AllocationOrder::AllocationOrder(unsigned VirtReg,
const VirtRegMap &VRM,
const RegisterClassInfo &RegClassInfo)
- : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
- const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
- std::pair<unsigned, unsigned> HintPair =
- VRM.getRegInfo().getRegAllocationHint(VirtReg);
- const MachineRegisterInfo &MRI = VRM.getRegInfo();
-
- // HintPair.second is a register, phys or virt.
- Hint = HintPair.second;
-
- // Translate to physreg, or 0 if not assigned yet.
- if (TargetRegisterInfo::isVirtualRegister(Hint))
- Hint = VRM.getPhys(Hint);
-
- // The first hint pair component indicates a target-specific hint.
- if (HintPair.first) {
- const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
- // The remaining allocation order may depend on the hint.
- ArrayRef<MCPhysReg> Order =
- TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
- VRM.getMachineFunction());
- if (Order.empty())
- return;
-
- // Copy the allocation order with reserved registers removed.
- OwnedBegin = true;
- MCPhysReg *P = new MCPhysReg[Order.size()];
- Begin = P;
- for (unsigned i = 0; i != Order.size(); ++i)
- if (!MRI.isReserved(Order[i]))
- *P++ = Order[i];
- End = P;
-
- // Target-dependent hints require resolution.
- Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint,
- VRM.getMachineFunction());
- } else {
- // If there is no hint or just a normal hint, use the cached allocation
- // order from RegisterClassInfo.
- ArrayRef<MCPhysReg> O = RCI.getOrder(RC);
- Begin = O.begin();
- End = O.end();
- }
+ : Pos(0) {
+ const MachineFunction &MF = VRM.getMachineFunction();
+ const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
+ Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
+ TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
+
+ DEBUG({
+ if (!Hints.empty()) {
+ dbgs() << "hints:";
+ for (unsigned I = 0, E = Hints.size(); I != E; ++I)
+ dbgs() << ' ' << PrintReg(Hints[I], TRI);
+ dbgs() << '\n';
+ }
+ });
+}
- // The hint must be a valid physreg for allocation.
- if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) ||
- !RC->contains(Hint) || MRI.isReserved(Hint)))
- Hint = 0;
+bool AllocationOrder::isHint(unsigned PhysReg) const {
+ return std::find(Hints.begin(), Hints.end(), PhysReg) != Hints.end();
}
-AllocationOrder::~AllocationOrder() {
- if (OwnedBegin)
- delete [] Begin;
+unsigned AllocationOrder::next() {
+ if (Pos < Hints.size())
+ return Hints[Pos++];
+ ArrayRef<MCPhysReg>::iterator I = Order.begin() + (Pos - Hints.size());
+ ArrayRef<MCPhysReg>::iterator E = Order.end();
+ while (I != E) {
+ unsigned Reg = *I++;
+ ++Pos;
+ if (!isHint(Reg))
+ return Reg;
+ }
+ return 0;
}
Modified: llvm/trunk/lib/CodeGen/AllocationOrder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AllocationOrder.h?rev=169173&r1=169172&r2=169173&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AllocationOrder.h (original)
+++ llvm/trunk/lib/CodeGen/AllocationOrder.h Mon Dec 3 16:51:04 2012
@@ -18,6 +18,7 @@
#define LLVM_CODEGEN_ALLOCATIONORDER_H
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/ADT/ArrayRef.h"
namespace llvm {
@@ -25,15 +26,12 @@
class VirtRegMap;
class AllocationOrder {
- const MCPhysReg *Begin;
- const MCPhysReg *End;
- const MCPhysReg *Pos;
- const RegisterClassInfo &RCI;
- unsigned Hint;
- bool OwnedBegin;
-public:
+ SmallVector<MCPhysReg, 16> Hints;
+ ArrayRef<MCPhysReg> Order;
+ unsigned Pos;
- /// AllocationOrder - Create a new AllocationOrder for VirtReg.
+public:
+ /// Create a new AllocationOrder for VirtReg.
/// @param VirtReg Virtual register to allocate for.
/// @param VRM Virtual register map for function.
/// @param RegClassInfo Information about reserved and allocatable registers.
@@ -41,32 +39,19 @@
const VirtRegMap &VRM,
const RegisterClassInfo &RegClassInfo);
- ~AllocationOrder();
+ /// Return the next physical register in the allocation order, or 0.
+ /// It is safe to call next() again after it returned 0, it will keep
+ /// returning 0 until rewind() is called.
+ unsigned next();
- /// next - Return the next physical register in the allocation order, or 0.
- /// It is safe to call next again after it returned 0.
- /// It will keep returning 0 until rewind() is called.
- unsigned next() {
- // First take the hint.
- if (!Pos) {
- Pos = Begin;
- if (Hint)
- return Hint;
- }
- // Then look at the order from TRI.
- while (Pos != End) {
- unsigned Reg = *Pos++;
- if (Reg != Hint)
- return Reg;
- }
- return 0;
- }
-
- /// rewind - Start over from the beginning.
+ /// Start over from the beginning.
void rewind() { Pos = 0; }
- /// isHint - Return true if PhysReg is a preferred register.
- bool isHint(unsigned PhysReg) const { return PhysReg == Hint; }
+ /// Return true if the last register returned from next() was a preferred register.
+ bool isHint() const { return Pos <= Hints.size(); }
+
+ /// Return true if PhysReg is a preferred register.
+ bool isHint(unsigned PhysReg) const;
};
} // end namespace llvm
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