[llvm-commits] Fwd: [llvm] r168837 - in /llvm/trunk: lib/CodeGen/RegisterCoalescer.cpp test/CodeGen/ARM/coalesce-subregs.ll

[Pawel Wodnicki]

Hi,

> Hi Pawel,
> 
> Would you merge this bugfix to the release branch, please?

Committed revision 168849.

Pawel

> 
> I am the code owner.
> 
> Thanks,
> /jakob
> 
> Begin forwarded message:
> 
>> From: Jakob Stoklund Olesen <stoklund at 2pi.dk>
>> Subject: [llvm-commits] [llvm] r168837 - in /llvm/trunk: lib/CodeGen/RegisterCoalescer.cpp test/CodeGen/ARM/coalesce-subregs.ll
>> Date: November 28, 2012 4:26:12 PM PST
>> To: llvm-commits at cs.uiuc.edu
>>
>> Author: stoklund
>> Date: Wed Nov 28 18:26:11 2012
>> New Revision: 168837
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=168837&view=rev
>> Log:
>> Avoid rewriting instructions twice.
>>
>> This could cause miscompilations in targets where sub-register
>> composition is not always idempotent (ARM).
>>
>> <rdar://problem/12758887>
>>
>> Modified:
>>    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
>>    llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll
>>
>> Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=168837&r1=168836&r2=168837&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Wed Nov 28 18:26:11 2012
>> @@ -887,8 +887,17 @@
>>   // Update LiveDebugVariables.
>>   LDV->renameRegister(SrcReg, DstReg, SubIdx);
>>
>> +  SmallPtrSet<MachineInstr*, 8> Visited;
>>   for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg);
>>        MachineInstr *UseMI = I.skipInstruction();) {
>> +    // Each instruction can only be rewritten once because sub-register
>> +    // composition is not always idempotent. When SrcReg != DstReg, rewriting
>> +    // the UseMI operands removes them from the SrcReg use-def chain, but when
>> +    // SrcReg is DstReg we could encounter UseMI twice if it has multiple
>> +    // operands mentioning the virtual register.
>> +    if (SrcReg == DstReg && !Visited.insert(UseMI))
>> +      continue;
>> +
>>     SmallVector<unsigned,8> Ops;
>>     bool Reads, Writes;
>>     tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll?rev=168837&r1=168836&r2=168837&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/coalesce-subregs.ll Wed Nov 28 18:26:11 2012
>> @@ -317,3 +317,44 @@
>>   store <2 x i64> %result.2, <2 x i64>* %agg.result, align 128
>>   ret void
>> }
>> +
>> +; <rdar://problem/12758887>
>> +; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than
>> +; once under rare circumstances. When widening a register from QPR to DTriple
>> +; with the original virtual register in dsub_1_dsub_2, the double rewrite would
>> +; produce an invalid sub-register.
>> +;
>> +; This is because dsub_1_dsub_2 is not an idempotent sub-register index.
>> +; It will translate %vr:dsub_0 -> %vr:dsub_1.
>> +define hidden fastcc void @radar12758887() nounwind optsize ssp {
>> +entry:
>> +  br i1 undef, label %for.body, label %for.end70
>> +
>> +for.body:                                         ; preds = %for.end, %entry
>> +  br i1 undef, label %for.body29, label %for.end
>> +
>> +for.body29:                                       ; preds = %for.body29, %for.body
>> +  %0 = load <2 x double>* null, align 1
>> +  %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer
>> +  %mul41 = fmul <2 x double> undef, %splat40
>> +  %add42 = fadd <2 x double> undef, %mul41
>> +  %splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 1, i32 1>
>> +  %mul45 = fmul <2 x double> undef, %splat44
>> +  %add46 = fadd <2 x double> undef, %mul45
>> +  br i1 undef, label %for.end, label %for.body29
>> +
>> +for.end:                                          ; preds = %for.body29, %for.body
>> +  %accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ]
>> +  %accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ]
>> +  %1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32> <i32 1, i32 0>
>> +  %add58 = fadd <2 x double> undef, %1
>> +  %mul61 = fmul <2 x double> %add58, undef
>> +  %add63 = fadd <2 x double> undef, %mul61
>> +  %add64 = fadd <2 x double> undef, %add63
>> +  %add67 = fadd <2 x double> undef, %add64
>> +  store <2 x double> %add67, <2 x double>* undef, align 1
>> +  br i1 undef, label %for.end70, label %for.body
>> +
>> +for.end70:                                        ; preds = %for.end, %entry
>> +  ret void
>> +}
>>
>>
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