[llvm-commits] [llvm] r168360 - in /llvm/trunk: include/llvm/CodeGen/MachineInstrBundle.h lib/CodeGen/MachineBasicBlock.cpp lib/CodeGen/MachineInstrBundle.cpp test/CodeGen/ARM/domain-conv-vmovs.ll
Tim Northover
Tim.Northover at arm.com
Tue Nov 20 01:56:11 PST 2012
Author: tnorthover
Date: Tue Nov 20 03:56:11 2012
New Revision: 168360
URL: http://llvm.org/viewvc/llvm-project?rev=168360&view=rev
Log:
Fix physical register liveness calculations:
+ Take account of clobbers
+ Give outputs priority over inputs since they happen later.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineInstrBundle.h
llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp
llvm/trunk/test/CodeGen/ARM/domain-conv-vmovs.ll
Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBundle.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBundle.h?rev=168360&r1=168359&r2=168360&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstrBundle.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstrBundle.h Tue Nov 20 03:56:11 2012
@@ -149,16 +149,13 @@
/// PhysRegInfo - Information about a physical register used by a set of
/// operands.
struct PhysRegInfo {
- /// Clobbers - Reg or an overlapping register is defined, or a regmask
+ /// Clobbers - Reg or an overlapping register is defined, or a regmask
/// clobbers Reg.
bool Clobbers;
/// Defines - Reg or a super-register is defined.
bool Defines;
- /// DefinesOverlap - Reg or an overlapping register is defined.
- bool DefinesOverlap;
-
/// Reads - Read or a super-register is read.
bool Reads;
Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=168360&r1=168359&r2=168360&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Nov 20 03:56:11 2012
@@ -982,7 +982,6 @@
MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
unsigned Reg, MachineInstr *MI,
unsigned Neighborhood) {
-
unsigned N = Neighborhood;
MachineBasicBlock *MBB = MI->getParent();
@@ -997,14 +996,18 @@
MachineOperandIteratorBase::PhysRegInfo Analysis =
MIOperands(I).analyzePhysReg(Reg, TRI);
- if (Analysis.Kills)
+ if (Analysis.Defines)
+ // Outputs happen after inputs so they take precedence if both are
+ // present.
+ return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
+
+ if (Analysis.Kills || Analysis.Clobbers)
// Register killed, so isn't live.
return LQR_Dead;
- else if (Analysis.DefinesOverlap || Analysis.ReadsOverlap)
+ else if (Analysis.ReadsOverlap)
// Defined or read without a previous kill - live.
- return (Analysis.Defines || Analysis.Reads) ?
- LQR_Live : LQR_OverlappingLive;
+ return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
} while (I != MBB->begin() && --N > 0);
}
@@ -1036,7 +1039,7 @@
return (Analysis.Reads) ?
LQR_Live : LQR_OverlappingLive;
- else if (Analysis.DefinesOverlap)
+ else if (Analysis.Clobbers || Analysis.Defines)
// Defined (but not read) therefore cannot have been live.
return LQR_Dead;
}
Modified: llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp?rev=168360&r1=168359&r2=168360&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstrBundle.cpp Tue Nov 20 03:56:11 2012
@@ -281,7 +281,7 @@
MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
const TargetRegisterInfo *TRI) {
bool AllDefsDead = true;
- PhysRegInfo PRI = {false, false, false, false, false, false, false};
+ PhysRegInfo PRI = {false, false, false, false, false, false};
assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
"analyzePhysReg not given a physical register!");
@@ -305,7 +305,9 @@
// Reg or a super-reg is read, and perhaps killed also.
PRI.Reads = true;
PRI.Kills = MO.isKill();
- } if (IsRegOrOverlapping && MO.readsReg()) {
+ }
+
+ if (IsRegOrOverlapping && MO.readsReg()) {
PRI.ReadsOverlap = true;// Reg or an overlapping register is read.
}
Modified: llvm/trunk/test/CodeGen/ARM/domain-conv-vmovs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/domain-conv-vmovs.ll?rev=168360&r1=168359&r2=168360&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/domain-conv-vmovs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/domain-conv-vmovs.ll Tue Nov 20 03:56:11 2012
@@ -98,3 +98,23 @@
ret i32 %resi
}
+
+
+; The point of this test is:
+; + Make sure s1 is live before the BL
+; + Make sure s1 is clobbered by the BL
+; + Convince LLVM to emit a VMOV to S0
+; + Convince LLVM to domain-convert this.
+
+; When all of those are satisfied, LLVM should *not* mark s1 as an implicit-use
+; because it's dead.
+
+declare float @clobbers_s1(float, float)
+
+define <2 x float> @test_clobbers_recognised(<2 x float> %invec, float %val) {
+ %elt = call float @clobbers_s1(float %val, float %val)
+
+ %vec = insertelement <2 x float> %invec, float %elt, i32 0
+ %res = fadd <2 x float> %vec, %vec
+ ret <2 x float> %res
+}
More information about the llvm-commits
mailing list