[llvm-commits] [llvm] r168076 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp
Jakub Staszak
kubastaszak at gmail.com
Thu Nov 15 11:40:30 PST 2012
Author: kuba
Date: Thu Nov 15 13:40:29 2012
New Revision: 168076
URL: http://llvm.org/viewvc/llvm-project?rev=168076&view=rev
Log:
Return 0 instead of false.
Modified:
llvm/trunk/lib/Target/X86/X86FastISel.cpp
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=168076&r1=168075&r2=168076&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Nov 15 13:40:29 2012
@@ -2154,13 +2154,13 @@
unsigned X86FastISel::TargetMaterializeFloatZero(const ConstantFP *CF) {
MVT VT;
if (!isTypeLegal(CF->getType(), VT))
- return false;
+ return 0;
// Get opcode and regclass for the given zero.
unsigned Opc = 0;
const TargetRegisterClass *RC = NULL;
switch (VT.SimpleTy) {
- default: return false;
+ default: return 0;
case MVT::f32:
if (X86ScalarSSEf32) {
Opc = X86::FsFLD0SS;
@@ -2181,7 +2181,7 @@
break;
case MVT::f80:
// No f80 support yet.
- return false;
+ return 0;
}
unsigned ResultReg = createResultReg(RC);
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