[llvm-commits] [Clang] Clean up and fix X86 CPU features

[Craig Topper]

Also this mail went to the wrong list. You want clang-commits.

On Wed, Nov 14, 2012 at 11:10 PM, Craig Topper <craig.topper at gmail.com>wrote:

> I'd rather not enable CLMUL and AES with AVX. The current behavior was
> consistent with gcc.
>
> On Wed, Nov 14, 2012 at 4:09 PM, Jung-uk Kim <jkim at freebsd.org> wrote:
>
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>> [Copied from PR14344 and edited for Sean Silva <silvas at purdue.edu>]
>>
>> I have an AMD Family 10h processor and I realized that LZCNT and
>> POPCNT are not enabled by default.  Then, I looked at clang's
>> lib/Basic/Targets.cpp and found it needs some love. :-)
>>
>> Please see the attached patch.
>>
>> - - AMD SSE4A capable processors have LZCNT, POPCNT, and SSE3
>> instructions.
>> - - AMD Piledriver("bdver2") processors have BMI and FMA instructions.
>> - - All SSE levels enable MMX by default.
>> - - All AVX capable processors have AES and PCLMUL instructions.
>> - - Sync. F16C feature with LLVM's X86.td.
>>
>> Thanks!
>>
>> Jung-uk Kim
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>>
>
>
> --
> ~Craig
>



-- 
~Craig
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