[llvm-commits] [llvm] r167826 - in /llvm/trunk: include/llvm/Target/TargetSubtargetInfo.h lib/CodeGen/MachineScheduler.cpp lib/CodeGen/Passes.cpp lib/CodeGen/RegisterCoalescer.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Target/TargetSubtargetInfo.cpp
Andrew Trick
atrick at apple.com
Tue Nov 13 00:47:29 PST 2012
Author: atrick
Date: Tue Nov 13 02:47:29 2012
New Revision: 167826
URL: http://llvm.org/viewvc/llvm-project?rev=167826&view=rev
Log:
misched: Allow subtargets to enable misched and dependent options.
This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.
Disabling PostRA sched may follow for some subtargets.
Modified:
llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/CodeGen/Passes.cpp
llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=167826&r1=167825&r2=167826&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Tue Nov 13 02:47:29 2012
@@ -54,6 +54,13 @@
return 0;
}
+ /// \brief True if the subtarget should run MachineScheduler after aggressive
+ /// coalescing.
+ ///
+ /// This currently replaces the SelectionDAG scheduler with the "source" order
+ /// scheduler. It does not yet disable the postRA scheduler.
+ virtual bool enableMachineScheduler() const;
+
// enablePostRAScheduler - If the target can benefit from post-regalloc
// scheduling and the specified optimization level meets the requirement
// return true to enable post-register-allocation scheduling. In
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=167826&r1=167825&r2=167826&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Tue Nov 13 02:47:29 2012
@@ -60,11 +60,11 @@
// Experimental heuristics
static cl::opt<bool> EnableLoadCluster("misched-cluster", cl::Hidden,
- cl::desc("Enable load clustering."));
+ cl::desc("Enable load clustering."), cl::init(true));
// Experimental heuristics
static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
- cl::desc("Enable scheduling for macro fusion."));
+ cl::desc("Enable scheduling for macro fusion."), cl::init(true));
//===----------------------------------------------------------------------===//
// Machine Instruction Scheduling Pass and Registry
Modified: llvm/trunk/lib/CodeGen/Passes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=167826&r1=167825&r2=167826&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Passes.cpp (original)
+++ llvm/trunk/lib/CodeGen/Passes.cpp Tue Nov 13 02:47:29 2012
@@ -22,6 +22,7 @@
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/Assembly/PrintModulePass.h"
#include "llvm/Support/CommandLine.h"
@@ -241,7 +242,9 @@
disablePass(&EarlyIfConverterID);
// Temporarily disable experimental passes.
- substitutePass(&MachineSchedulerID, 0);
+ const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
+ if (!ST.enableMachineScheduler())
+ disablePass(&MachineSchedulerID);
}
/// Insert InsertedPassID pass after TargetPassID.
Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=167826&r1=167825&r2=167826&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Nov 13 02:47:29 2012
@@ -45,6 +45,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cmath>
using namespace llvm;
@@ -64,16 +65,16 @@
cl::init(true));
// Temporary flag to test critical edge unsplitting.
-static cl::opt<bool>
+static cl::opt<cl::boolOrDefault>
EnableJoinSplits("join-splitedges",
- cl::desc("Coalesce copies on split edges (default=false)"),
- cl::init(false), cl::Hidden);
+ cl::desc("Coalesce copies on split edges (default=subtarget)"),
+ cl::init(cl::BOU_UNSET), cl::Hidden);
// Temporary flag to test global copy optimization.
-static cl::opt<bool>
+static cl::opt<cl::boolOrDefault>
EnableGlobalCopies("join-globalcopies",
- cl::desc("Coalesce copies that don't locally define an lrg"),
- cl::init(false));
+ cl::desc("Coalesce copies that span blocks (default=subtarget)"),
+ cl::init(cl::BOU_UNSET), cl::Hidden);
static cl::opt<bool>
VerifyCoalescing("verify-coalescing",
@@ -94,6 +95,14 @@
AliasAnalysis *AA;
RegisterClassInfo RegClassInfo;
+ /// \brief True if the coalescer should aggressively coalesce global copies
+ /// in favor of keeping local copies.
+ bool JoinGlobalCopies;
+
+ /// \brief True if the coalescer should aggressively coalesce fall-thru
+ /// blocks exclusively containing copies.
+ bool JoinSplitEdges;
+
/// WorkList - Copy instructions yet to be coalesced.
SmallVector<MachineInstr*, 8> WorkList;
SmallVector<MachineInstr*, 8> LocalWorkList;
@@ -1943,6 +1952,10 @@
//
// EnableGlobalCopies assumes that the primary sort key is loop depth.
struct MBBPriorityCompare {
+ bool JoinSplitEdges;
+
+ MBBPriorityCompare(bool joinsplits): JoinSplitEdges(joinsplits) {}
+
bool operator()(const MBBPriorityInfo &LHS,
const MBBPriorityInfo &RHS) const {
// Deeper loops first
@@ -1950,7 +1963,7 @@
return LHS.Depth > RHS.Depth;
// Try to unsplit critical edges next.
- if (EnableJoinSplits && LHS.IsSplit != RHS.IsSplit)
+ if (JoinSplitEdges && LHS.IsSplit != RHS.IsSplit)
return LHS.IsSplit;
// Prefer blocks that are more connected in the CFG. This takes care of
@@ -2011,7 +2024,7 @@
// Collect all copy-like instructions in MBB. Don't start coalescing anything
// yet, it might invalidate the iterator.
const unsigned PrevSize = WorkList.size();
- if (EnableGlobalCopies) {
+ if (JoinGlobalCopies) {
// Coalesce copies bottom-up to coalesce local defs before local uses. They
// are not inherently easier to resolve, but slightly preferable until we
// have local live range splitting. In particular this is required by
@@ -2061,13 +2074,13 @@
MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
isSplitEdge(MBB)));
}
- std::sort(MBBs.begin(), MBBs.end(), MBBPriorityCompare());
+ std::sort(MBBs.begin(), MBBs.end(), MBBPriorityCompare(JoinSplitEdges));
// Coalesce intervals in MBB priority order.
unsigned CurrDepth = UINT_MAX;
for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
// Try coalescing the collected local copies for deeper loops.
- if (EnableGlobalCopies && MBBs[i].Depth < CurrDepth)
+ if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth)
coalesceLocals();
copyCoalesceInMBB(MBBs[i].MBB);
}
@@ -2097,6 +2110,17 @@
AA = &getAnalysis<AliasAnalysis>();
Loops = &getAnalysis<MachineLoopInfo>();
+ const TargetSubtargetInfo &ST = TM->getSubtarget<TargetSubtargetInfo>();
+ if (EnableGlobalCopies == cl::BOU_UNSET)
+ JoinGlobalCopies = ST.enableMachineScheduler();
+ else
+ JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
+
+ if (EnableJoinSplits == cl::BOU_UNSET)
+ JoinSplitEdges = ST.enableMachineScheduler();
+ else
+ JoinSplitEdges = (EnableJoinSplits == cl::BOU_TRUE);
+
DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
<< "********** Function: " << MF->getName() << '\n');
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=167826&r1=167825&r2=167826&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Nov 13 02:47:29 2012
@@ -45,6 +45,7 @@
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
@@ -216,8 +217,9 @@
ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
CodeGenOpt::Level OptLevel) {
const TargetLowering &TLI = IS->getTargetLowering();
+ const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
- if (OptLevel == CodeGenOpt::None ||
+ if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
TLI.getSchedulingPreference() == Sched::Source)
return createSourceListDAGScheduler(IS, OptLevel);
if (TLI.getSchedulingPreference() == Sched::RegPressure)
Modified: llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSubtargetInfo.cpp?rev=167826&r1=167825&r2=167826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetSubtargetInfo.cpp Tue Nov 13 02:47:29 2012
@@ -22,6 +22,10 @@
TargetSubtargetInfo::~TargetSubtargetInfo() {}
+bool TargetSubtargetInfo::enableMachineScheduler() const {
+ return false;
+}
+
bool TargetSubtargetInfo::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
AntiDepBreakMode& Mode,
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