[llvm-commits] [llvm] r167671 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Craig Topper]

Author: ctopper
Date: Sat Nov 10 03:02:47 2012
New Revision: 167671

URL: http://llvm.org/viewvc/llvm-project?rev=167671&view=rev
Log:
Tidy up spacing. No functional change.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=167671&r1=167670&r2=167671&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Nov 10 03:02:47 2012
@@ -12840,8 +12840,8 @@
 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
 // or XMM0_V32I8 in AVX all of this code can be replaced with that
 // in the .td file.
-static MachineBasicBlock * EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
-                                        const TargetInstrInfo *TII) {
+static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
+                                       const TargetInstrInfo *TII) {
   unsigned Opc;
   switch (MI->getOpcode()) {
   default: llvm_unreachable("illegal opcode!");
@@ -12877,8 +12877,8 @@
 
 // FIXME: Custom handling because TableGen doesn't support multiple implicit
 // defs in an instruction pattern
-static MachineBasicBlock * EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
-                                        const TargetInstrInfo *TII) {
+static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
+                                       const TargetInstrInfo *TII) {
   unsigned Opc;
   switch (MI->getOpcode()) {
   default: llvm_unreachable("illegal opcode!");