[llvm-commits] [llvm] r167153 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/remat-immed-load.ll
Akira Hatanaka
ahatanaka at mips.com
Wed Oct 31 11:37:56 PDT 2012
Author: ahatanak
Date: Wed Oct 31 13:37:55 2012
New Revision: 167153
URL: http://llvm.org/viewvc/llvm-project?rev=167153&view=rev
Log:
[mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables
re-materialization of immediate loads.
Added:
llvm/trunk/test/CodeGen/Mips/remat-immed-load.ll
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=167153&r1=167152&r2=167153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Wed Oct 31 13:37:55 2012
@@ -86,7 +86,7 @@
def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16,
CPU64Regs>;
def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16,
- CPU64Regs>;
+ CPU64Regs>, IsAsCheapAsAMove;
def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>;
def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=167153&r1=167152&r2=167153&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Oct 31 13:37:55 2012
@@ -200,6 +200,10 @@
bit isCodeGenOnly = 1;
}
+class IsAsCheapAsAMove {
+ bit isAsCheapAsAMove = 1;
+}
+
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
@@ -925,7 +929,8 @@
//===----------------------------------------------------------------------===//
/// Arithmetic Instructions (ALU Immediate)
-def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
+def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>,
+ IsAsCheapAsAMove;
def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
Added: llvm/trunk/test/CodeGen/Mips/remat-immed-load.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/remat-immed-load.ll?rev=167153&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/remat-immed-load.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/remat-immed-load.ll Wed Oct 31 13:37:55 2012
@@ -0,0 +1,26 @@
+; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
+; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=64
+
+define void @f0() nounwind {
+entry:
+; 32: addiu $4, $zero, 1
+; 32: addiu $4, $zero, 1
+
+ tail call void @foo1(i32 1) nounwind
+ tail call void @foo1(i32 1) nounwind
+ ret void
+}
+
+declare void @foo1(i32)
+
+define void @f3() nounwind {
+entry:
+; 64: daddiu $4, $zero, 1
+; 64: daddiu $4, $zero, 1
+
+ tail call void @foo2(i64 1) nounwind
+ tail call void @foo2(i64 1) nounwind
+ ret void
+}
+
+declare void @foo2(i64)
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