[llvm-commits] [llvm] r166990 - in /llvm/trunk: lib/Target/Mips/Mips16InstrInfo.cpp lib/Target/Mips/Mips16InstrInfo.td test/CodeGen/Mips/helloworld.ll test/CodeGen/Mips/null.ll

[Reed Kotler]

Author: rkotler
Date: Mon Oct 29 19:54:49 2012
New Revision: 166990

URL: http://llvm.org/viewvc/llvm-project?rev=166990&view=rev
Log:
Change mips16 delay slot jumps to non delay slot forms by default.
We will make them delay slot forms if there is something that can be
placed in the delay slot during a separate pass. Mips16 extended instructions
cannot be placed in delay slots.


Modified:
    llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
    llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
    llvm/trunk/test/CodeGen/Mips/helloworld.ll
    llvm/trunk/test/CodeGen/Mips/null.ll

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp?rev=166990&r1=166989&r2=166990&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp Mon Oct 29 19:54:49 2012
@@ -126,7 +126,7 @@
   default:
     return false;
   case Mips::RetRA16:
-    ExpandRetRA16(MBB, MI, Mips::JrRa16);
+    ExpandRetRA16(MBB, MI, Mips::JrcRa16);
     break;
   }
 

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=166990&r1=166989&r2=166990&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Mon Oct 29 19:54:49 2012
@@ -515,6 +515,13 @@
   let isBarrier=1;
 }
 
+def JrcRa16: FRR16_JALRC_RA_only_ins<0, 0, "jrc", IIAlu> {
+  let isBranch = 1;
+  let isIndirectBranch = 1;
+  let isTerminator=1;
+  let isBarrier=1;
+}
+
 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
   let isBranch = 1;
   let isIndirectBranch = 1;
@@ -1011,10 +1018,10 @@
 
 
 // Jump and Link (Call)
-let isCall=1, hasDelaySlot=1 in
+let isCall=1, hasDelaySlot=0 in
 def JumpLinkReg16:
   FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
-              "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
+              "jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
 
 // Mips16 pseudos
 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,

Modified: llvm/trunk/test/CodeGen/Mips/helloworld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/helloworld.ll?rev=166990&r1=166989&r2=166990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/helloworld.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/helloworld.ll Mon Oct 29 19:54:49 2012
@@ -24,10 +24,10 @@
 ; C1:	addiu	${{[0-9]+}}, %lo($.str)
 ; C2:	move	$25, ${{[0-9]+}}
 ; C1:	move 	$gp, ${{[0-9]+}}
-; C1:	jalr 	${{[0-9]+}}
+; C1:	jalrc 	${{[0-9]+}}
 ; SR:	restore 	$ra, [[FS]]
 ; PE:	li	$2, 0
-; PE:	jr 	$ra
+; PE:	jrc 	$ra
 
 }
 

Modified: llvm/trunk/test/CodeGen/Mips/null.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/null.ll?rev=166990&r1=166989&r2=166990&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/null.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/null.ll Mon Oct 29 19:54:49 2012
@@ -8,6 +8,6 @@
 ; 16: 	.set	mips16                  # @main
 
 
-; 16:	jr	$ra
+; 16:	jrc	$ra
 
 }