[llvm-commits] [llvm] r166903 - in /llvm/trunk: lib/Target/Mips/Mips16InstrInfo.td test/CodeGen/Mips/brind.ll

[Reed Kotler]

Author: rkotler
Date: Sun Oct 28 18:08:07 2012
New Revision: 166903

URL: http://llvm.org/viewvc/llvm-project?rev=166903&view=rev
Log:
Implement brind operator for mips16.


Added:
    llvm/trunk/test/CodeGen/Mips/brind.ll
Modified:
    llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=166903&r1=166902&r2=166903&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Sun Oct 28 18:08:07 2012
@@ -250,6 +250,12 @@
   FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
               [], itin> ;
 
+
+class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
+                      string asmstr, InstrItinClass itin>:
+  FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx), 
+              !strconcat(asmstr, "\t $rx"), [], itin> ;
+
 //
 // RRR-type instruction format
 //
@@ -508,6 +514,13 @@
   let isTerminator=1;
   let isBarrier=1;
 }
+
+def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
+  let isBranch = 1;
+  let isIndirectBranch = 1;
+  let isTerminator=1;
+  let isBarrier=1;
+}
 //
 // Format: LB ry, offset(rx) MIPS16e
 // Purpose: Load Byte (Extended)
@@ -991,6 +1004,12 @@
     let Predicates = [RelocPIC, InMips16Mode];
   }
 
+// Indirect branch
+def: Mips16Pat<
+  (brind CPU16Regs:$rs), 
+  (JrcRx16 CPU16Regs:$rs)>;  
+
+
 // Jump and Link (Call)
 let isCall=1, hasDelaySlot=1 in
 def JumpLinkReg16:

Added: llvm/trunk/test/CodeGen/Mips/brind.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/brind.ll?rev=166903&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/brind.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/brind.ll Sun Oct 28 18:08:07 2012
@@ -0,0 +1,40 @@
+; RUN: llc  -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at main.L = internal unnamed_addr constant [5 x i8*] [i8* blockaddress(@main, %L1), i8* blockaddress(@main, %L2), i8* blockaddress(@main, %L3), i8* blockaddress(@main, %L4), i8* null], align 4
+ at str = private unnamed_addr constant [2 x i8] c"A\00"
+ at str5 = private unnamed_addr constant [2 x i8] c"B\00"
+ at str6 = private unnamed_addr constant [2 x i8] c"C\00"
+ at str7 = private unnamed_addr constant [2 x i8] c"D\00"
+ at str8 = private unnamed_addr constant [2 x i8] c"E\00"
+
+define i32 @main() nounwind {
+entry:
+  %puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str, i32 0, i32 0))
+  br label %L1
+
+L1:                                               ; preds = %entry, %L3
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %L3 ]
+  %puts5 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str5, i32 0, i32 0))
+  br label %L2
+
+L2:                                               ; preds = %L1, %L3
+  %i.1 = phi i32 [ %i.0, %L1 ], [ %inc, %L3 ]
+  %puts6 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str6, i32 0, i32 0))
+  br label %L3
+
+L3:                                               ; preds = %L2, %L3
+  %i.2 = phi i32 [ %i.1, %L2 ], [ %inc, %L3 ]
+  %puts7 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str7, i32 0, i32 0))
+  %inc = add i32 %i.2, 1
+  %arrayidx = getelementptr inbounds [5 x i8*]* @main.L, i32 0, i32 %i.2
+  %0 = load i8** %arrayidx, align 4
+  indirectbr i8* %0, [label %L1, label %L2, label %L3, label %L4]
+; 16: 	jrc	 ${{[0-9]+}}
+L4:                                               ; preds = %L3
+  %puts8 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str8, i32 0, i32 0))
+  ret i32 0
+}
+
+declare i32 @puts(i8* nocapture) nounwind
+
+