[llvm-commits] Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM

[Andrew Trick]

CriticalAntiDependenceBreaking will not be relevant much longer. I think this patch can go in and we can deal with any performance impact that shows up.

Background:
  misched should eventually perform virtual register antidep breaking. I haven't implemented that yet.
  misched tracks phys reg dependencies correctly, so shouldn't be affected by this patch. (It still uses MCAliasIterator for historical reasons)
  If we need to break physreg antideps after regalloc, we should just implement a utility that tracks register units within a range of instructions.

-Andy

On Oct 26, 2012, at 8:48 AM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:

> Andy, what are we planning for anti-dependency breaking?
> 
> /jakob
> 
> On Oct 25, 2012, at 6:33 PM, "Weiming Zhao" <weimingz at codeaurora.org> wrote:
> 
>> I figured out the reason.
>> After we added the following to td file:
>> def Tuples2R : RegisterTuples<[gsub_0, gsub_1],
>>                             [(add R0, R2, R4, R6, R8, R10, R12),
>>                              (add R1, R3, R5, R7, R9, R11, SP)]>;
>> We make those GPRs alias the new Reg Class. 
>> 
>> Then, in CriticalAntiDepBreaker.cpp::PrescanInstruction(), it thinks R1 has
>> alias, so gives up for breaking anti-dep:
>> for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
>>     // If an alias of the reg is used during the live range, give up.
>>     // Note that this allows us to skip checking if AntiDepReg
>>     // overlaps with any of the aliases, among other things.
>>     unsigned AliasReg = *AI;
>>     if (Classes[AliasReg]) {
>>       Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
>>       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
>>     }
>> 
>> 
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
>> The Linux Foundation
>> 
>> 
>> -----Original Message-----
>> From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
>> Sent: Thursday, October 25, 2012 1:14 PM
>> To: weimingz at codeaurora.org
>> Cc: 'Jim Grosbach'; llvm-commits at cs.uiuc.edu; zinob at codeaurora.org
>> Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm
>> with 64-bit data on ARM
>> 
>> 
>> On Oct 25, 2012, at 12:25 PM, Weiming Zhao <weimingz at codeaurora.org> wrote:
>> 
>>> Hi Jakob,
>>> 
>>> Now, all the CodeGen fails are gone (there were 4 before I correct my
>>> mistake) except for Thumb2/thumb2-uxtb.ll. 
>>> It is caused by the change to ARMRegisterInfo.td alone  (I reverted 
>>> the changes to the other two files and it still occurs).  I'm not 
>>> clear about the cause, but it's NOT a real fail, just different 
>>> (actually better) scheduling/reg alloc:
>> 
>> I don't like that adding a completely unused register class affects code
>> generation.
>> 
>> Please at least figure out why it is happening.
>> 
>> /jakob
>> 
>> 
>