[llvm-commits] [LLVMdev] ABI: how to let the backend know that an aggregate should be allocated on stack

[manman ren]

On Oct 26, 2012, at 11:50 AM, Duncan Sands <baldrick at free.fr> wrote:

> Hi manman,
> 
>>> The current definition of the byval attribute in LangRef says nothing about requiring passing the argument on the stack.  It just says it "should really be passed by value".  When discussing the alignment, it does refer to a stack slot, but it isn't at all clear that it is required to be on the stack.
>> 
>> it needs to be addressable.  The "byval" parameter is a pointer, and that
>> pointer can be passed to any old routine as an ordinary pointer, and they
>> may read or write the memory it points to.  So while you could pass in
>> registers, the callee would still need to construct a stack object using
>> those values, then use the address of the stack object for all references
>> to the byval parameter.  (That said, if the callee doesn't ever dereference
>> the byval pointer then you could not bother constructing the stack object).
> > That's true, for ARM, we construct a stack object for the register-portion of the byval and it is right next to the stack-portion of the byval.
>> It did cause some problem with tail call if address of the byval argument is passed to a call (see r165853).
> 
> I don't understand why you don't just have byval mean "pass on the stack" and
> require front-ends to break up arguments into register parts and on the stack
> parts.  I'm pretty sure that the original intent was that byval should have the
> same simple meaning everywhere: pass on the stack.  Maybe I'm misunderstanding
> what you are doing for ARM, but it sounds like you are teaching the backend to
> do ABI conformance, having it break byval objects up into register bits and non
> register bits (and having to do this kind of "put the registers back on the
> stack" dance as a consequence).

Hi Duncan,

That part of the implementation was not implemented by me. I was stating the current state of byval for ARM.
And I believe it is true for Mips and PowerPC as well.

I think the implementation tries to conform to the ABI standard:
If the NCRN is less than r4 and the NSAA is equal to the SP, the argument is split between core registers and the stack. The first part of the argument is copied into the core registers starting at the NCRN up to and including r3. The remainder of the argument is copied onto the stack, starting at the NSAA.

We can change how backend handles byval to make all these simpler.

Thanks,
Manman 
> 
> Ciao, Duncan.

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