[llvm-commits] [llvm] r166770 - /llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td

[Will Schmidt]

On Fri, 2012-10-26 at 11:35 -0200, Adhemerval Zanella wrote:
> I'd like too, but currently PPC does not have a working assemble/dissassembler
> (because we don't have an functional asm parser). I'm accepting suggestion 
> how to accomplish it.

For reference, on the asmparser front, I only got far enough to get hung
up on PointerLikeRegClass support within tablegen.   (i.e.
http://llvm.org/bugs/show_bug.cgi?id=14011 "tblgen support for ptr_rc /
PointerLikeRegClass incomplete for gen-asm-matcher " ).   Attempts to
work around that by wrapping the ptr_rc references within something
Operand derived led to other errors, so I wasn't sure that was the right
approach.
( http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-September/053566.html
)

Thanks, 
-Will


> 
> 
> On 10/26/2012 11:03 AM, Rafael Espíndola wrote:
> > This needs a testcase.
> >
> > On 26 October 2012 08:09, Adhemerval Zanella
> > <azanella at linux.vnet.ibm.com> wrote:
> >> Author: azanella
> >> Date: Fri Oct 26 07:09:58 2012
> >> New Revision: 166770
> >>
> >> URL: http://llvm.org/viewvc/llvm-project?rev=166770&view=rev
> >> Log:
> >> PowerPC: Fix for rldcl/rldicl/rldicr MC emission
> >>
> >> This patch fixes the rldcl/rldicl/rldicr instruction emission. The issue is
> >> the MDForm_1 instruction defines the PowerISA MB field from 'rldicl'
> >> with the name MBE, but RLDCL/RLDICL/RLDICR definition uses as 'MB'.
> >>
> >> It end up by generatint the 'rldicl' enconding at
> >> 'lib/Target/PowerPC/PPCGenMCCodeEmitter.inc' to use the fourth argument as the
> >> third. The patch changes it by adjusting to use the fourth argument as
> >> intended.
> >>
> >> Fixes PR14180.
> >>
> >>
> >> Modified:
> >>     llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> >>
> >> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
> >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=166770&r1=166769&r2=166770&view=diff
> >> ==============================================================================
> >> --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
> >> +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Fri Oct 26 07:09:58 2012
> >> @@ -494,16 +494,16 @@
> >>
> >>  // Rotate instructions.
> >>  def RLDCL  : MDForm_1<30, 0,
> >> -                      (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
> >> -                      "rldcl $rA, $rS, $rB, $MB", IntRotateD,
> >> +                      (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
> >> +                      "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
> >>                        []>, isPPC64;
> >>  def RLDICL : MDForm_1<30, 0,
> >> -                      (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
> >> -                      "rldicl $rA, $rS, $SH, $MB", IntRotateDI,
> >> +                      (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
> >> +                      "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
> >>                        []>, isPPC64;
> >>  def RLDICR : MDForm_1<30, 1,
> >> -                      (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
> >> -                      "rldicr $rA, $rS, $SH, $ME", IntRotateDI,
> >> +                      (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
> >> +                      "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
> >>                        []>, isPPC64;
> >>
> >>  def RLWINM8 : MForm_2<21,
> >>
> >>
> >> _______________________________________________
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> >> llvm-commits at cs.uiuc.edu
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