[llvm-commits] Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM

[Weiming Zhao]

Hi Jakob,

Now, all the CodeGen fails are gone (there were 4 before I correct my
mistake) except for Thumb2/thumb2-uxtb.ll. 
It is caused by the change to ARMRegisterInfo.td alone  (I reverted the
changes to the other two files and it still occurs).  I'm not clear about
the cause, but it's NOT a real fail, just different (actually better)
scheduling/reg alloc:

Original test:
define i32 @test10(i32 %p0) {
; ARMv7M: test10
; ARMv7M: mov.w r1, #16253176
; ARMv7M: mov.w r2, #458759
; ARMv7M: and.w r0, r1, r0, lsr #7
; ARMv7M: and.w r1, r2, r0, lsr #5
; ARMv7M: orrs r0, r1
	%tmp1 = lshr i32 %p0, 7		; <i32> [#uses=1]
	%tmp2 = and i32 %tmp1, 16253176		; <i32> [#uses=2]
	%tmp4 = lshr i32 %tmp2, 5		; <i32> [#uses=1]
	%tmp5 = and i32 %tmp4, 458759		; <i32> [#uses=1]
	%tmp7 = or i32 %tmp5, %tmp2		; <i32> [#uses=1]

Current output:
test10:
@ BB#0:
	mov.w	r1, #16253176
	and.w	r0, r1, r0, lsr #7
	mov.w	r1, #458759
	and.w	r1, r1, r0, lsr #5
	orrs	r0, r1
	bx	lr

We replacing "r2"  with "r2" because r1 is dead after the first "and.w"

I'm attaching a new patch that includes the change to this test case.  
Please help to review.

Thanks,
Weiming

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation


-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
Sent: Thursday, October 25, 2012 9:31 AM
To: weimingz at codeaurora.org
Cc: 'Jim Grosbach'; llvm-commits at cs.uiuc.edu; zinob at codeaurora.org
Subject: Re: [llvm-commits] Fixing Bug 13662: paired register for inline asm
with 64-bit data on ARM


On Oct 23, 2012, at 2:57 PM, Weiming Zhao <weimingz at codeaurora.org> wrote:

> When I run "make check", even without my patch, I still see 93 
> unexpected failures. So maybe I ignored that failure.

Please get that fixed before sending more patches. I can't do basic checking
for you.

/jakob

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