[llvm-commits] [llvm] r166459 - in /llvm/trunk: lib/Target/Mips/Mips16InstrInfo.td test/CodeGen/Mips/seteq.ll test/CodeGen/Mips/seteqz.ll test/CodeGen/Mips/setge.ll test/CodeGen/Mips/setgek.ll test/CodeGen/Mips/setle.ll test/CodeGen/Mips/setlt.ll
Chandler Carruth
chandlerc at google.com
Mon Oct 22 18:47:19 PDT 2012
On Mon, Oct 22, 2012 at 6:35 PM, Reed Kotler <rkotler at mips.com> wrote:
> Author: rkotler
> Date: Mon Oct 22 20:35:48 2012
> New Revision: 166459
>
> URL: http://llvm.org/viewvc/llvm-project?rev=166459&view=rev
> Log:
> implement setXX patterns
>
>
> Added:
> llvm/trunk/test/CodeGen/Mips/seteq.ll
> llvm/trunk/test/CodeGen/Mips/seteqz.ll
> llvm/trunk/test/CodeGen/Mips/setge.ll
> llvm/trunk/test/CodeGen/Mips/setgek.ll
> llvm/trunk/test/CodeGen/Mips/setle.ll
> llvm/trunk/test/CodeGen/Mips/setlt.ll
> llvm/trunk/test/CodeGen/Mips/setltk.ll
> llvm/trunk/test/CodeGen/Mips/setne.ll
> llvm/trunk/test/CodeGen/Mips/setuge.ll
> llvm/trunk/test/CodeGen/Mips/setugt.ll
> llvm/trunk/test/CodeGen/Mips/setule.ll
> llvm/trunk/test/CodeGen/Mips/setult.ll
> llvm/trunk/test/CodeGen/Mips/setultk.ll
Please fold tests into a few aggregate test files rather than having
one file per small function. All of the test running strategies impose
a fixed cost per test, and FileCheck allows an aggregation of tests to
still provide precise granularity of failures.
(This has come up quite a few times in recent patch review, although
not likely your patches...)
> Modified:
> llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
>
> Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=166459&r1=166458&r2=166459&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Mon Oct 22 20:35:48 2012
> @@ -21,6 +21,19 @@
> }
>
> //
> +// Compare a register and immediate and place result in CC
> +// Implicit use of T8
> +//
> +// EXT-CCRR Instruction format
> +//
> +class FEXT_CCRXI16_ins<bits<5> _op, string asmstr,
> + InstrItinClass itin>:
> + FEXT_RI16<_op, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
> + !strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), [], itin> {
> + let isCodeGenOnly=1;
> +}
> +
> +//
> // EXT-I instruction format
> //
> class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
> @@ -44,6 +57,17 @@
> // Assembler formats in alphabetical order.
> // Natural and pseudos are mixed together.
> //
> +// Compare two registers and place result in CC
> +// Implicit use of T8
> +//
> +// CC-RR Instruction format
> +//
> +class FCCRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
> + FRR16<f, (outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
> + !strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), [], itin> {
> + let isCodeGenOnly=1;
> +}
> +
> //
> // EXT-RI instruction format
> //
> @@ -562,8 +586,37 @@
> //
> def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
>
> +//
> +// Format: SLTI rx, immediate MIPS16e
> +// Purpose: Set on Less Than Immediate (Extended)
> +// To record the result of a less-than comparison with a constant.
> +//
> +def SltiCCRxImmX16: FEXT_CCRXI16_ins<0b01010, "slti", IIAlu>;
> +
> +//
> +// Format: SLTIU rx, immediate MIPS16e
> +// Purpose: Set on Less Than Immediate Unsigned (Extended)
> +// To record the result of a less-than comparison with a constant.
> +//
> +def SltiuCCRxImmX16: FEXT_CCRXI16_ins<0b01011, "sltiu", IIAlu>;
>
> //
> +// Format: SLT rx, ry MIPS16e
> +// Purpose: Set on Less Than
> +// To record the result of a less-than comparison.
> +//
> +def SltRxRy16: FRR16_ins<0b00010, "slt", IIAlu>;
> +
> +def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
> +
> +// Format: SLTU rx, ry MIPS16e
> +// Purpose: Set on Less Than Unsigned
> +// To record the result of an unsigned less-than comparison.
> +//
> +
> +
> +def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
> +//
> // Format: SRAV ry, rx MIPS16e
> // Purpose: Shift Word Right Arithmetic Variable
> // To execute an arithmetic right-shift of a word by a variable
> @@ -705,6 +758,17 @@
> def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
>
>
> +// setcc patterns
> +
> +class SetCC_R16<PatFrag cond_op, Instruction I>:
> + Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
> + (I CPU16Regs:$rx, CPU16Regs:$ry)>;
> +
> +class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
> + Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
> + (I CPU16Regs:$rx, imm_type:$imm16)>;
> +
> +
> //
> // Some branch conditional patterns are not generated by llvm at this time.
> // Some are for seemingly arbitrary reasons not used: i.e. with signed number
> @@ -757,10 +821,10 @@
>
> //
> // never called because compiler transforms a >= k to a > (k-1)
> -//def: Mips16Pat
> -// <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
> -// (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
> -// >;
> +def: Mips16Pat
> + <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
> + (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
> + >;
>
> //
> // bcond-setlt
> @@ -859,5 +923,118 @@
> (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
>
>
> +//
> +// When writing C code to test setxx these patterns,
> +// some will be transformed into
> +// other things. So we test using C code but using -O3 and -O0
> +//
> +// seteq
> +//
> +def : Mips16Pat
> + <(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
> + (SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
> +
> +def : Mips16Pat
> + <(seteq CPU16Regs:$lhs, 0),
> + (SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
> +
> +
> +//
> +// setge
> +//
> +
> +def: Mips16Pat
> + <(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
> + (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
> + (LiRxImmX16 1))>;
> +
> +//
> +// For constants, llvm transforms this to:
> +// x > (k -1) and then reverses the operands to use setlt. So this pattern
> +// is not used now by the compiler. (Presumably checking that k-1 does not
> +// overflow). The compiler never uses this at a the current time, due to
> +// other optimizations.
> +//
> +//def: Mips16Pat
> +// <(setge CPU16Regs:$lhs, immSExt16:$rhs),
> +// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
> +// (LiRxImmX16 1))>;
> +
> +// This catches the x >= -32768 case by transforming it to x > -32769
> +//
> +def: Mips16Pat
> + <(setgt CPU16Regs:$lhs, -32769),
> + (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
> + (LiRxImmX16 1))>;
> +
> +//
> +// setgt
> +//
> +//
> +
> +def: Mips16Pat
> + <(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
> + (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
> +
> +//
> +// setle
> +//
> +def: Mips16Pat
> + <(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
> + (XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
> +
> +//
> +// setlt
> +//
> +def: SetCC_R16<setlt, SltCCRxRy16>;
> +
> +def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
> +
> +//
> +// setne
> +//
> +def : Mips16Pat
> + <(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
> + (SltuCCRxRy16 (LiRxImmX16 0),
> + (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
> +
> +
> +//
> +// setuge
> +//
> +def: Mips16Pat
> + <(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
> + (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
> + (LiRxImmX16 1))>;
> +
> +// this pattern will never be used because the compiler will transform
> +// x >= k to x > (k - 1) and then use SLT
> +//
> +//def: Mips16Pat
> +// <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
> +// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
> +// (LiRxImmX16 1))>;
> +
> +//
> +// setugt
> +//
> +def: Mips16Pat
> + <(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
> + (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
> +
> +//
> +// setule
> +//
> +def: Mips16Pat
> + <(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
> + (XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
> +
> +//
> +// setult
> +//
> +def: SetCC_R16<setult, SltuCCRxRy16>;
> +
> +def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
> +
> def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
> (AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
>
> Added: llvm/trunk/test/CodeGen/Mips/seteq.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/seteq.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/seteq.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/seteq.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,21 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at i = global i32 1, align 4
> + at j = global i32 10, align 4
> + at k = global i32 1, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @i, align 4
> + %1 = load i32* @k, align 4
> + %cmp = icmp eq i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
> +; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
> +; 16: move ${{[0-9]+}}, $t8
> + ret void
> +}
> +
>
> Added: llvm/trunk/test/CodeGen/Mips/seteqz.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/seteqz.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/seteqz.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/seteqz.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,24 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at i = global i32 0, align 4
> + at j = global i32 99, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @i, align 4
> + %cmp = icmp eq i32 %0, 0
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: sltiu ${{[0-9]+}}, 1
> +; 16: move ${{[0-9]+}}, $t8
> + %1 = load i32* @j, align 4
> + %cmp1 = icmp eq i32 %1, 99
> + %conv2 = zext i1 %cmp1 to i32
> + store i32 %conv2, i32* @r2, align 4
> +; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
> +; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
> +; 16: move ${{[0-9]+}}, $t8
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setge.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setge.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setge.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setge.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,27 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 -5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> + at .str = private unnamed_addr constant [22 x i8] c"1 = %i\0A1 = %i\0A0 = %i\0A\00", align 1
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @k, align 4
> + %1 = load i32* @j, align 4
> + %cmp = icmp sge i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
> +; 16: move $[[REGISTER:[0-9]+]], $t8
> +; 16: xor $[[REGISTER]], ${{[0-9]+}}
> + %2 = load i32* @m, align 4
> + %cmp1 = icmp sge i32 %0, %2
> + %conv2 = zext i1 %cmp1 to i32
> + store i32 %conv2, i32* @r2, align 4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setgek.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setgek.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setgek.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setgek.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,18 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at k = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @k, align 4
> + %cmp = icmp sgt i32 %0, -32769
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: slti ${{[0-9]+}}, -32768
> +; 16: move $[[REGISTER:[0-9]+]], $t8
> +; 16: xor ${{[0-9]+}}, $[[REGISTER]]
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setle.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setle.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setle.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setle.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,26 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 -5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @j, align 4
> + %1 = load i32* @k, align 4
> + %cmp = icmp sle i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
> +; 16: move $[[REGISTER:[0-9]+]], $t8
> +; 16: xor $[[REGISTER]], ${{[0-9]+}}
> + %2 = load i32* @m, align 4
> + %cmp1 = icmp sle i32 %2, %1
> + %conv2 = zext i1 %cmp1 to i32
> + store i32 %conv2, i32* @r2, align 4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setlt.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setlt.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setlt.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setlt.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,21 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 -5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @j, align 4
> + %1 = load i32* @k, align 4
> + %cmp = icmp slt i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
> +; 16: move ${{[0-9]+}}, $t8
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setltk.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setltk.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setltk.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setltk.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,20 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 -5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @j, align 4
> + %cmp = icmp slt i32 %0, 10
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: slti $[[REGISTER:[0-9]+]], 10
> +; 16: move $[[REGISTER]], $t8
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setne.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setne.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setne.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setne.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,20 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at i = global i32 1, align 4
> + at j = global i32 10, align 4
> + at k = global i32 1, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @i, align 4
> + %1 = load i32* @k, align 4
> + %cmp = icmp ne i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
> +; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
> +; 16: move ${{[0-9]+}}, $t8
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setuge.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setuge.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setuge.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setuge.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,26 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @k, align 4
> + %1 = load i32* @j, align 4
> + %cmp = icmp uge i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
> +; 16: move $[[REGISTER:[0-9]+]], $t8
> +; 16: xor $[[REGISTER]], ${{[0-9]+}}
> + %2 = load i32* @m, align 4
> + %cmp1 = icmp uge i32 %0, %2
> + %conv2 = zext i1 %cmp1 to i32
> + store i32 %conv2, i32* @r2, align 4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setugt.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setugt.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setugt.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setugt.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,21 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @k, align 4
> + %1 = load i32* @j, align 4
> + %cmp = icmp ugt i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
> +; 16: move ${{[0-9]+}}, $t8
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setule.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setule.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setule.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setule.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,26 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @j, align 4
> + %1 = load i32* @k, align 4
> + %cmp = icmp ule i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
> +; 16: move $[[REGISTER:[0-9]+]], $t8
> +; 16: xor $[[REGISTER]], ${{[0-9]+}}
> + %2 = load i32* @m, align 4
> + %cmp1 = icmp ule i32 %2, %1
> + %conv2 = zext i1 %cmp1 to i32
> + store i32 %conv2, i32* @r2, align 4
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setult.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setult.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setult.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setult.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,21 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @j, align 4
> + %1 = load i32* @k, align 4
> + %cmp = icmp ult i32 %0, %1
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
> +; 16: move ${{[0-9]+}}, $t8
> + ret void
> +}
>
> Added: llvm/trunk/test/CodeGen/Mips/setultk.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/setultk.ll?rev=166459&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/setultk.ll (added)
> +++ llvm/trunk/test/CodeGen/Mips/setultk.ll Mon Oct 22 20:35:48 2012
> @@ -0,0 +1,20 @@
> +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
> +
> + at j = global i32 5, align 4
> + at k = global i32 10, align 4
> + at l = global i32 20, align 4
> + at m = global i32 10, align 4
> + at r1 = common global i32 0, align 4
> + at r2 = common global i32 0, align 4
> + at r3 = common global i32 0, align 4
> +
> +define void @test() nounwind {
> +entry:
> + %0 = load i32* @j, align 4
> + %cmp = icmp ult i32 %0, 10
> + %conv = zext i1 %cmp to i32
> + store i32 %conv, i32* @r1, align 4
> +; 16: sltiu $[[REGISTER:[0-9]+]], 10
> +; 16: move $[[REGISTER]], $t8
> + ret void
> +}
>
>
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