[llvm-commits] [llvm] r166445 - in /llvm/trunk: include/llvm-c/Disassembler.h include/llvm/MC/MCInstPrinter.h lib/MC/MCDisassembler/Disassembler.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp test/MC/Disassembler/ARM/marked-up-thumb.txt test/MC/Disassembler/X86/marked-up.txt tools/llvm-mc/llvm-mc.cpp tools/lto/lto.exports
Jim Grosbach
grosbach at apple.com
Mon Oct 22 18:14:29 PDT 2012
Hi Alex,
To recap what we covered in IRC (for the benefit of those who don't hang out there):
1) Sorry I didn't get an explicit response to you sooner on your previous email. That's my fault.
2) This is a first step. We need to get docs included as well, for example. Specifically, we wanted this patch out sooner rather than later so folks can review things and we can talk about and review actual code.
To respond briefly to your specific interest in something like YAML, XML or JSON, I thought I had covered that already in my responses to Sean. Sounds like from your perspective that's not correct, though, and there's additional territory you'd like to go over. That's fine; let's keep talking. I think most of what you (and we) are looking for in lots of those cases is related but orthogonal to this interface, however, and are things we can add incrementally.
-Jim
On Oct 22, 2012, at 5:24 PM, Alex Rosenberg <alexr at leftfield.org> wrote:
> I thought that this design was still being discussed?!
>
> Sent from my iPad
>
> On Oct 22, 2012, at 3:31 PM, Kevin Enderby <enderby at apple.com> wrote:
>
>> Author: enderby
>> Date: Mon Oct 22 17:31:46 2012
>> New Revision: 166445
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=166445&view=rev
>> Log:
>> Add support for annotated disassembly output for X86 and arm.
>>
>> Per the October 12, 2012 Proposal for annotated disassembly output sent out by
>> Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc
>> tool now has a -mdis option to produced the marked up disassembly and a couple
>> of small example test cases have been added.
>>
>> rdar://11764962
>>
>> Added:
>> llvm/trunk/test/MC/Disassembler/ARM/marked-up-thumb.txt
>> llvm/trunk/test/MC/Disassembler/X86/marked-up.txt
>> Modified:
>> llvm/trunk/include/llvm-c/Disassembler.h
>> llvm/trunk/include/llvm/MC/MCInstPrinter.h
>> llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
>> llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>> llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
>> llvm/trunk/tools/llvm-mc/llvm-mc.cpp
>> llvm/trunk/tools/lto/lto.exports
>>
>> Modified: llvm/trunk/include/llvm-c/Disassembler.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Disassembler.h?rev=166445&r1=166444&r2=166445&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm-c/Disassembler.h (original)
>> +++ llvm/trunk/include/llvm-c/Disassembler.h Mon Oct 22 17:31:46 2012
>> @@ -146,6 +146,15 @@
>> LLVMSymbolLookupCallback SymbolLookUp);
>>
>> /**
>> + * Set the disassembler's options. Returns 1 if it can set the Options and 0
>> + * otherwise.
>> + */
>> +int LLVMSetDisasmOptions(LLVMDisasmContextRef DC, uint64_t Options);
>> +
>> +/* The option to produce marked up assembly. */
>> +#define LLVMDisassembler_Option_UseMarkup 1
>> +
>> +/**
>> * Dispose of a disassembler context.
>> */
>> void LLVMDisasmDispose(LLVMDisasmContextRef DC);
>>
>> Modified: llvm/trunk/include/llvm/MC/MCInstPrinter.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstPrinter.h?rev=166445&r1=166444&r2=166445&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/MC/MCInstPrinter.h (original)
>> +++ llvm/trunk/include/llvm/MC/MCInstPrinter.h Mon Oct 22 17:31:46 2012
>> @@ -33,12 +33,16 @@
>> /// The current set of available features.
>> unsigned AvailableFeatures;
>>
>> + /// True if we are printing marked up assembly.
>> + bool UseMarkup;
>> +
>> /// Utility function for printing annotations.
>> void printAnnotation(raw_ostream &OS, StringRef Annot);
>> public:
>> MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
>> const MCRegisterInfo &mri)
>> - : CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0) {}
>> + : CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0),
>> + UseMarkup(0) {}
>>
>> virtual ~MCInstPrinter();
>>
>> @@ -59,6 +63,9 @@
>>
>> unsigned getAvailableFeatures() const { return AvailableFeatures; }
>> void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
>> +
>> + bool getUseMarkup() const { return UseMarkup; }
>> + void setUseMarkup(bool Value) { UseMarkup = Value; }
>> };
>>
>> } // namespace llvm
>>
>> Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=166445&r1=166444&r2=166445&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original)
>> +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Mon Oct 22 17:31:46 2012
>> @@ -184,3 +184,17 @@
>> }
>> llvm_unreachable("Invalid DecodeStatus!");
>> }
>> +
>> +//
>> +// LLVMSetDisasmOptions() sets the disassembler's options. It returns 1 if it
>> +// can set all the Options and 0 otherwise.
>> +//
>> +int LLVMSetDisasmOptions(LLVMDisasmContextRef DCR, uint64_t Options){
>> + if (Options & LLVMDisassembler_Option_UseMarkup){
>> + LLVMDisasmContext *DC = (LLVMDisasmContext *)DCR;
>> + MCInstPrinter *IP = DC->getIP();
>> + IP->setUseMarkup(1);
>> + Options &= ~LLVMDisassembler_Option_UseMarkup;
>> + }
>> + return (Options == 0);
>> +}
>>
>> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=166445&r1=166444&r2=166445&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Oct 22 17:31:46 2012
>> @@ -39,7 +39,7 @@
>>
>> /// Prints the shift value with an immediate value.
>> static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
>> - unsigned ShImm) {
>> + unsigned ShImm, bool UseMarkup) {
>> if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
>> return;
>> O << ", ";
>> @@ -47,8 +47,14 @@
>> assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
>> O << getShiftOpcStr(ShOpc);
>>
>> - if (ShOpc != ARM_AM::rrx)
>> - O << " #" << translateShiftImm(ShImm);
>> + if (ShOpc != ARM_AM::rrx){
>> + O << " ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << translateShiftImm(ShImm);
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> }
>>
>> ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
>> @@ -61,7 +67,11 @@
>> }
>>
>> void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
>> + if (UseMarkup)
>> + OS << "<reg:";
>> OS << getRegisterName(RegNo);
>> + if (UseMarkup)
>> + OS << ">";
>> }
>>
>> void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
>> @@ -101,10 +111,13 @@
>> printSBitModifierOperand(MI, 6, O);
>> printPredicateOperand(MI, 4, O);
>>
>> - O << '\t' << getRegisterName(Dst.getReg())
>> - << ", " << getRegisterName(MO1.getReg());
>> + O << '\t';
>> + printRegName(O, Dst.getReg());
>> + O << ", ";
>> + printRegName(O, MO1.getReg());
>>
>> - O << ", " << getRegisterName(MO2.getReg());
>> + O << ", ";
>> + printRegName(O, MO2.getReg());
>> assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
>> printAnnotation(O, Annot);
>> return;
>> @@ -120,15 +133,22 @@
>> printSBitModifierOperand(MI, 5, O);
>> printPredicateOperand(MI, 3, O);
>>
>> - O << '\t' << getRegisterName(Dst.getReg())
>> - << ", " << getRegisterName(MO1.getReg());
>> + O << '\t';
>> + printRegName(O, Dst.getReg());
>> + O << ", ";
>> + printRegName(O, MO1.getReg());
>>
>> if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
>> printAnnotation(O, Annot);
>> return;
>> }
>>
>> - O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
>> + if (UseMarkup)
>> + O << ">";
>> printAnnotation(O, Annot);
>> return;
>> }
>> @@ -152,7 +172,9 @@
>> MI->getOperand(3).getImm() == -4) {
>> O << '\t' << "push";
>> printPredicateOperand(MI, 4, O);
>> - O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
>> + O << "\t{";
>> + printRegName(O, MI->getOperand(1).getReg());
>> + O << "}";
>> printAnnotation(O, Annot);
>> return;
>> }
>> @@ -175,7 +197,9 @@
>> MI->getOperand(4).getImm() == 4) {
>> O << '\t' << "pop";
>> printPredicateOperand(MI, 5, O);
>> - O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
>> + O << "\t{";
>> + printRegName(O, MI->getOperand(0).getReg());
>> + O << "}";
>> printAnnotation(O, Annot);
>> return;
>> }
>> @@ -214,7 +238,8 @@
>> O << "\tldm";
>>
>> printPredicateOperand(MI, 1, O);
>> - O << '\t' << getRegisterName(BaseReg);
>> + O << '\t';
>> + printRegName(O, BaseReg);
>> if (Writeback) O << "!";
>> O << ", ";
>> printRegisterList(MI, 3, O);
>> @@ -240,9 +265,13 @@
>> const MCOperand &Op = MI->getOperand(OpNo);
>> if (Op.isReg()) {
>> unsigned Reg = Op.getReg();
>> - O << getRegisterName(Reg);
>> + printRegName(O, Reg);
>> } else if (Op.isImm()) {
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << '#' << Op.getImm();
>> + if (UseMarkup)
>> + O << ">";
>> } else {
>> assert(Op.isExpr() && "unknown operand kind in printOperand");
>> // If a symbolic branch target was added as a constant expression then print
>> @@ -265,8 +294,20 @@
>> const MCOperand &MO1 = MI->getOperand(OpNum);
>> if (MO1.isExpr())
>> O << *MO1.getExpr();
>> - else if (MO1.isImm())
>> - O << "[pc, #" << MO1.getImm() << "]";
>> + else if (MO1.isImm()) {
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[pc, ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#";
>> + O << MO1.getImm();
>> + if (UseMarkup)
>> + O << ">";
>> + O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> else
>> llvm_unreachable("Unknown LDR label operand?");
>> }
>> @@ -282,7 +323,7 @@
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>> const MCOperand &MO3 = MI->getOperand(OpNum+2);
>>
>> - O << getRegisterName(MO1.getReg());
>> + printRegName(O, MO1.getReg());
>>
>> // Print the shift opc.
>> ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
>> @@ -290,7 +331,8 @@
>> if (ShOpc == ARM_AM::rrx)
>> return;
>>
>> - O << ' ' << getRegisterName(MO2.getReg());
>> + O << ' ';
>> + printRegName(O, MO2.getReg());
>> assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
>> }
>>
>> @@ -299,11 +341,11 @@
>> const MCOperand &MO1 = MI->getOperand(OpNum);
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>>
>> - O << getRegisterName(MO1.getReg());
>> + printRegName(O, MO1.getReg());
>>
>> // Print the shift opc.
>> printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
>> - ARM_AM::getSORegOffset(MO2.getImm()));
>> + ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
>> }
>>
>>
>> @@ -317,40 +359,73 @@
>> const MCOperand &MO2 = MI->getOperand(Op+1);
>> const MCOperand &MO3 = MI->getOperand(Op+2);
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>>
>> if (!MO2.getReg()) {
>> - if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
>> - O << ", #"
>> - << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
>> - << ARM_AM::getAM2Offset(MO3.getImm());
>> + if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#";
>> + O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
>> + O << ARM_AM::getAM2Offset(MO3.getImm());
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> return;
>> }
>>
>> - O << ", "
>> - << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
>> - << getRegisterName(MO2.getReg());
>> + O << ", ";
>> + O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
>> + printRegName(O, MO2.getReg());
>>
>> printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
>> - ARM_AM::getAM2Offset(MO3.getImm()));
>> + ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
>> raw_ostream &O) {
>> const MCOperand &MO1 = MI->getOperand(Op);
>> const MCOperand &MO2 = MI->getOperand(Op+1);
>> - O << "[" << getRegisterName(MO1.getReg()) << ", "
>> - << getRegisterName(MO2.getReg()) << "]";
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>> + O << ", ";
>> + printRegName(O, MO2.getReg());
>> + O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
>> raw_ostream &O) {
>> const MCOperand &MO1 = MI->getOperand(Op);
>> const MCOperand &MO2 = MI->getOperand(Op+1);
>> - O << "[" << getRegisterName(MO1.getReg()) << ", "
>> - << getRegisterName(MO2.getReg()) << ", lsl #1]";
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>> + O << ", ";
>> + printRegName(O, MO2.getReg());
>> + O << ", lsl ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#1";
>> + if (UseMarkup)
>> + O << ">";
>> + O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
>> @@ -380,17 +455,21 @@
>>
>> if (!MO1.getReg()) {
>> unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << '#'
>> << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
>> << ImmOffs;
>> + if (UseMarkup)
>> + O << ">";
>> return;
>> }
>>
>> - O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
>> - << getRegisterName(MO1.getReg());
>> + O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
>> + printRegName(O, MO1.getReg());
>>
>> printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
>> - ARM_AM::getAM2Offset(MO2.getImm()));
>> + ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
>> }
>>
>> //===--------------------------------------------------------------------===//
>> @@ -403,18 +482,28 @@
>> const MCOperand &MO2 = MI->getOperand(Op+1);
>> const MCOperand &MO3 = MI->getOperand(Op+2);
>>
>> - O << "[" << getRegisterName(MO1.getReg()) << "], ";
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>> + O << "], ";
>> + if (UseMarkup)
>> + O << ">";
>>
>> if (MO2.getReg()) {
>> - O << (char)ARM_AM::getAM3Op(MO3.getImm())
>> - << getRegisterName(MO2.getReg());
>> + O << (char)ARM_AM::getAM3Op(MO3.getImm());
>> + printRegName(O, MO2.getReg());
>> return;
>> }
>>
>> unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << '#'
>> << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
>> << ImmOffs;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
>> @@ -423,11 +512,18 @@
>> const MCOperand &MO2 = MI->getOperand(Op+1);
>> const MCOperand &MO3 = MI->getOperand(Op+2);
>>
>> - O << '[' << getRegisterName(MO1.getReg());
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << '[';
>> + printRegName(O, MO1.getReg());
>>
>> if (MO2.getReg()) {
>> - O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
>> - << getRegisterName(MO2.getReg()) << ']';
>> + O << ", ";
>> + O << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
>> + printRegName(O, MO2.getReg());
>> + O << ']';
>> + if (UseMarkup)
>> + O << ">";
>> return;
>> }
>>
>> @@ -435,11 +531,19 @@
>> unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
>> ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
>>
>> - if (ImmOffs || (op == ARM_AM::sub))
>> - O << ", #"
>> + if (ImmOffs || (op == ARM_AM::sub)) {
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#"
>> << ARM_AM::getAddrOpcStr(op)
>> << ImmOffs;
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> O << ']';
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
>> @@ -467,15 +571,19 @@
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>>
>> if (MO1.getReg()) {
>> - O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
>> - << getRegisterName(MO1.getReg());
>> + O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
>> + printRegName(O, MO1.getReg());
>> return;
>> }
>>
>> unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << '#'
>> << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
>> << ImmOffs;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
>> @@ -483,7 +591,11 @@
>> raw_ostream &O) {
>> const MCOperand &MO = MI->getOperand(OpNum);
>> unsigned Imm = MO.getImm();
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
>> @@ -491,7 +603,8 @@
>> const MCOperand &MO1 = MI->getOperand(OpNum);
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>>
>> - O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
>> + O << (MO2.getImm() ? "" : "-");
>> + printRegName(O, MO1.getReg());
>> }
>>
>> void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
>> @@ -499,7 +612,11 @@
>> raw_ostream &O) {
>> const MCOperand &MO = MI->getOperand(OpNum);
>> unsigned Imm = MO.getImm();
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>>
>> @@ -520,16 +637,26 @@
>> return;
>> }
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>>
>> unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
>> unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
>> if (ImmOffs || Op == ARM_AM::sub) {
>> - O << ", #"
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#"
>> << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
>> << ImmOffs * 4;
>> + if (UseMarkup)
>> + O << ">";
>> }
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
>> @@ -537,18 +664,29 @@
>> const MCOperand &MO1 = MI->getOperand(OpNum);
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>> if (MO2.getImm()) {
>> // FIXME: Both darwin as and GNU as violate ARM docs here.
>> O << ", :" << (MO2.getImm() << 3);
>> }
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> const MCOperand &MO1 = MI->getOperand(OpNum);
>> - O << "[" << getRegisterName(MO1.getReg()) << "]";
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>> + O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
>> @@ -557,8 +695,10 @@
>> const MCOperand &MO = MI->getOperand(OpNum);
>> if (MO.getReg() == 0)
>> O << "!";
>> - else
>> - O << ", " << getRegisterName(MO.getReg());
>> + else {
>> + O << ", ";
>> + printRegName(O, MO.getReg());
>> + }
>> }
>>
>> void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
>> @@ -569,7 +709,17 @@
>> int32_t lsb = CountTrailingZeros_32(v);
>> int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
>> assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
>> - O << '#' << lsb << ", #" << width;
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << '#' << lsb;
>> + if (UseMarkup)
>> + O << ">";
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << '#' << width;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
>> @@ -583,10 +733,22 @@
>> unsigned ShiftOp = MI->getOperand(OpNum).getImm();
>> bool isASR = (ShiftOp & (1 << 5)) != 0;
>> unsigned Amt = ShiftOp & 0x1f;
>> - if (isASR)
>> - O << ", asr #" << (Amt == 0 ? 32 : Amt);
>> - else if (Amt)
>> - O << ", lsl #" << Amt;
>> + if (isASR) {
>> + O << ", asr ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << (Amt == 0 ? 32 : Amt);
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> + else if (Amt) {
>> + O << ", lsl ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << Amt;
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> }
>>
>> void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
>> @@ -595,7 +757,12 @@
>> if (Imm == 0)
>> return;
>> assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
>> - O << ", lsl #" << Imm;
>> + O << ", lsl ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << Imm;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
>> @@ -605,7 +772,12 @@
>> if (Imm == 0)
>> Imm = 32;
>> assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
>> - O << ", asr #" << Imm;
>> + O << ", asr ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << Imm;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
>> @@ -613,7 +785,7 @@
>> O << "{";
>> for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
>> if (i != OpNum) O << ", ";
>> - O << getRegisterName(MI->getOperand(i).getReg());
>> + printRegName(O, MI->getOperand(i).getReg());
>> }
>> O << "}";
>> }
>> @@ -787,23 +959,35 @@
>>
>> int32_t OffImm = (int32_t)MO.getImm();
>>
>> + if (UseMarkup)
>> + O << "<imm:";
>> if (OffImm == INT32_MIN)
>> O << "#-0";
>> else if (OffImm < 0)
>> O << "#-" << -OffImm;
>> else
>> O << "#" << OffImm;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << "#" << MI->getOperand(OpNum).getImm() * 4;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> unsigned Imm = MI->getOperand(OpNum).getImm();
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << "#" << (Imm == 0 ? 32 : Imm);
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
>> @@ -833,10 +1017,17 @@
>> return;
>> }
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> - if (unsigned RegNum = MO2.getReg())
>> - O << ", " << getRegisterName(RegNum);
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>> + if (unsigned RegNum = MO2.getReg()) {
>> + O << ", ";
>> + printRegName(O, RegNum);
>> + }
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
>> @@ -851,10 +1042,21 @@
>> return;
>> }
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> - if (unsigned ImmOffs = MO2.getImm())
>> - O << ", #" << ImmOffs * Scale;
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>> + if (unsigned ImmOffs = MO2.getImm()) {
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << ImmOffs * Scale;
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
>> @@ -890,12 +1092,12 @@
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>>
>> unsigned Reg = MO1.getReg();
>> - O << getRegisterName(Reg);
>> + printRegName(O, Reg);
>>
>> // Print the shift opc.
>> assert(MO2.isImm() && "Not a valid t2_so_reg value!");
>> printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
>> - ARM_AM::getSORegOffset(MO2.getImm()));
>> + ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
>> }
>>
>> void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
>> @@ -908,18 +1110,35 @@
>> return;
>> }
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>>
>> int32_t OffImm = (int32_t)MO2.getImm();
>> bool isSub = OffImm < 0;
>> // Special value for #-0. All others are normal.
>> if (OffImm == INT32_MIN)
>> OffImm = 0;
>> - if (isSub)
>> - O << ", #-" << -OffImm;
>> - else if (OffImm > 0)
>> - O << ", #" << OffImm;
>> + if (isSub) {
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#-" << -OffImm;
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> + else if (OffImm > 0) {
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << OffImm;
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
>> @@ -928,17 +1147,28 @@
>> const MCOperand &MO1 = MI->getOperand(OpNum);
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>>
>> int32_t OffImm = (int32_t)MO2.getImm();
>> // Don't print +0.
>> + if (OffImm != 0)
>> + O << ", ";
>> + if (OffImm != 0 && UseMarkup)
>> + O << "<imm:";
>> if (OffImm == INT32_MIN)
>> - O << ", #-0";
>> + O << "#-0";
>> else if (OffImm < 0)
>> - O << ", #-" << -OffImm;
>> + O << "#-" << -OffImm;
>> else if (OffImm > 0)
>> - O << ", #" << OffImm;
>> + O << "#" << OffImm;
>> + if (OffImm != 0 && UseMarkup)
>> + O << ">";
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
>> @@ -952,20 +1182,31 @@
>> return;
>> }
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>>
>> int32_t OffImm = (int32_t)MO2.getImm();
>>
>> assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
>>
>> // Don't print +0.
>> + if (OffImm != 0)
>> + O << ", ";
>> + if (OffImm != 0 && UseMarkup)
>> + O << "<imm:";
>> if (OffImm == INT32_MIN)
>> - O << ", #-0";
>> + O << "#-0";
>> else if (OffImm < 0)
>> - O << ", #-" << -OffImm;
>> + O << "#-" << -OffImm;
>> else if (OffImm > 0)
>> - O << ", #" << OffImm;
>> + O << "#" << OffImm;
>> + if (OffImm != 0 && UseMarkup)
>> + O << ">";
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
>> @@ -974,10 +1215,21 @@
>> const MCOperand &MO1 = MI->getOperand(OpNum);
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> - if (MO2.getImm())
>> - O << ", #" << MO2.getImm() * 4;
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>> + if (MO2.getImm()) {
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << MO2.getImm() * 4;
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
>> @@ -985,11 +1237,15 @@
>> raw_ostream &O) {
>> const MCOperand &MO1 = MI->getOperand(OpNum);
>> int32_t OffImm = (int32_t)MO1.getImm();
>> - // Don't print +0.
>> + O << ", ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> if (OffImm < 0)
>> - O << ", #-" << -OffImm;
>> + O << "#-" << -OffImm;
>> else
>> - O << ", #" << OffImm;
>> + O << "#" << OffImm;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
>> @@ -1001,12 +1257,18 @@
>> assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
>>
>> // Don't print +0.
>> + if (OffImm != 0)
>> + O << ", ";
>> + if (OffImm != 0 && UseMarkup)
>> + O << "<imm:";
>> if (OffImm == INT32_MIN)
>> - O << ", #-0";
>> + O << "#-0";
>> else if (OffImm < 0)
>> - O << ", #-" << -OffImm;
>> + O << "#-" << -OffImm;
>> else if (OffImm > 0)
>> - O << ", #" << OffImm;
>> + O << "#" << OffImm;
>> + if (OffImm != 0 && UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
>> @@ -1016,23 +1278,38 @@
>> const MCOperand &MO2 = MI->getOperand(OpNum+1);
>> const MCOperand &MO3 = MI->getOperand(OpNum+2);
>>
>> - O << "[" << getRegisterName(MO1.getReg());
>> + if (UseMarkup)
>> + O << "<mem:";
>> + O << "[";
>> + printRegName(O, MO1.getReg());
>>
>> assert(MO2.getReg() && "Invalid so_reg load / store address!");
>> - O << ", " << getRegisterName(MO2.getReg());
>> + O << ", ";
>> + printRegName(O, MO2.getReg());
>>
>> unsigned ShAmt = MO3.getImm();
>> if (ShAmt) {
>> assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
>> - O << ", lsl #" << ShAmt;
>> + O << ", lsl ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#" << ShAmt;
>> + if (UseMarkup)
>> + O << ">";
>> }
>> O << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> const MCOperand &MO = MI->getOperand(OpNum);
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
>> @@ -1040,14 +1317,22 @@
>> unsigned EncodedImm = MI->getOperand(OpNum).getImm();
>> unsigned EltBits;
>> uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << "#0x";
>> O.write_hex(Val);
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> unsigned Imm = MI->getOperand(OpNum).getImm();
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << "#" << Imm + 1;
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
>> @@ -1055,33 +1340,52 @@
>> unsigned Imm = MI->getOperand(OpNum).getImm();
>> if (Imm == 0)
>> return;
>> - O << ", ror #";
>> + O << ", ror ";
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << "#";
>> switch (Imm) {
>> default: assert (0 && "illegal ror immediate!");
>> case 1: O << "8"; break;
>> case 2: O << "16"; break;
>> case 3: O << "24"; break;
>> }
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << "#" << 16 - MI->getOperand(OpNum).getImm();
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << "#" << 32 - MI->getOperand(OpNum).getImm();
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> + if (UseMarkup)
>> + O << "<mem:";
>> O << "[" << MI->getOperand(OpNum).getImm() << "]";
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
>> raw_ostream &O) {
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << "}";
>> }
>>
>> void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
>> @@ -1089,7 +1393,11 @@
>> unsigned Reg = MI->getOperand(OpNum).getReg();
>> unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
>> unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
>> - O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
>> + O << "{";
>> + printRegName(O, Reg0);
>> + O << ", ";
>> + printRegName(O, Reg1);
>> + O << "}";
>> }
>>
>> void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
>> @@ -1098,7 +1406,11 @@
>> unsigned Reg = MI->getOperand(OpNum).getReg();
>> unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
>> unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
>> - O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
>> + O << "{";
>> + printRegName(O, Reg0);
>> + O << ", ";
>> + printRegName(O, Reg1);
>> + O << "}";
>> }
>>
>> void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
>> @@ -1106,9 +1418,13 @@
>> // Normally, it's not safe to use register enum values directly with
>> // addition to get the next register, but for VFP registers, the
>> // sort order is guaranteed because they're all of the form D<n>.
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 1);
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 2);
>> + O << "}";
>> }
>>
>> void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
>> @@ -1116,16 +1432,23 @@
>> // Normally, it's not safe to use register enum values directly with
>> // addition to get the next register, but for VFP registers, the
>> // sort order is guaranteed because they're all of the form D<n>.
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 1);
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 2);
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 3);
>> + O << "}";
>> }
>>
>> void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
>> unsigned OpNum,
>> raw_ostream &O) {
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << "[]}";
>> }
>>
>> void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
>> @@ -1134,7 +1457,11 @@
>> unsigned Reg = MI->getOperand(OpNum).getReg();
>> unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
>> unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
>> - O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
>> + O << "{";
>> + printRegName(O, Reg0);
>> + O << "[], ";
>> + printRegName(O, Reg1);
>> + O << "[]}";
>> }
>>
>> void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
>> @@ -1143,9 +1470,13 @@
>> // Normally, it's not safe to use register enum values directly with
>> // addition to get the next register, but for VFP registers, the
>> // sort order is guaranteed because they're all of the form D<n>.
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 1);
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 2);
>> + O << "[]}";
>> }
>>
>> void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
>> @@ -1154,10 +1485,15 @@
>> // Normally, it's not safe to use register enum values directly with
>> // addition to get the next register, but for VFP registers, the
>> // sort order is guaranteed because they're all of the form D<n>.
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 1);
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 2);
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 3);
>> + O << "[]}";
>> }
>>
>> void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
>> @@ -1166,7 +1502,11 @@
>> unsigned Reg = MI->getOperand(OpNum).getReg();
>> unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
>> unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
>> - O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
>> + O << "{";
>> + printRegName(O, Reg0);
>> + O << "[], ";
>> + printRegName(O, Reg1);
>> + O << "[]}";
>> }
>>
>> void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
>> @@ -1175,9 +1515,13 @@
>> // Normally, it's not safe to use register enum values directly with
>> // addition to get the next register, but for VFP registers, the
>> // sort order is guaranteed because they're all of the form D<n>.
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 2);
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 4);
>> + O << "[]}";
>> }
>>
>> void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
>> @@ -1186,10 +1530,15 @@
>> // Normally, it's not safe to use register enum values directly with
>> // addition to get the next register, but for VFP registers, the
>> // sort order is guaranteed because they're all of the form D<n>.
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 2);
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 4);
>> + O << "[], ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 6);
>> + O << "[]}";
>> }
>>
>> void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
>> @@ -1198,9 +1547,13 @@
>> // Normally, it's not safe to use register enum values directly with
>> // addition to get the next register, but for VFP registers, the
>> // sort order is guaranteed because they're all of the form D<n>.
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 2);
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 4);
>> + O << "}";
>> }
>>
>> void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
>> @@ -1209,8 +1562,13 @@
>> // Normally, it's not safe to use register enum values directly with
>> // addition to get the next register, but for VFP registers, the
>> // sort order is guaranteed because they're all of the form D<n>.
>> - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", "
>> - << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}";
>> + O << "{";
>> + printRegName(O, MI->getOperand(OpNum).getReg());
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 2);
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 4);
>> + O << ", ";
>> + printRegName(O, MI->getOperand(OpNum).getReg() + 6);
>> + O << "}";
>> }
>>
>> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=166445&r1=166444&r2=166445&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Mon Oct 22 17:31:46 2012
>> @@ -34,7 +34,11 @@
>>
>> void X86ATTInstPrinter::printRegName(raw_ostream &OS,
>> unsigned RegNo) const {
>> + if (UseMarkup)
>> + OS << "<reg:";
>> OS << '%' << getRegisterName(RegNo);
>> + if (UseMarkup)
>> + OS << ">";
>> }
>>
>> void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
>> @@ -151,17 +155,29 @@
>> raw_ostream &O) {
>> const MCOperand &Op = MI->getOperand(OpNo);
>> if (Op.isReg()) {
>> + if (UseMarkup)
>> + O << "<reg:";
>> O << '%' << getRegisterName(Op.getReg());
>> + if (UseMarkup)
>> + O << ">";
>> } else if (Op.isImm()) {
>> + if (UseMarkup)
>> + O << "<imm:";
>> // Print X86 immediates as signed values.
>> O << '$' << (int64_t)Op.getImm();
>> + if (UseMarkup)
>> + O << ">";
>>
>> if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
>> *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
>>
>> } else {
>> assert(Op.isExpr() && "unknown operand kind in printOperand");
>> + if (UseMarkup)
>> + O << "<imm:";
>> O << '$' << *Op.getExpr();
>> + if (UseMarkup)
>> + O << ">";
>> }
>> }
>>
>> @@ -172,6 +188,9 @@
>> const MCOperand &DispSpec = MI->getOperand(Op+3);
>> const MCOperand &SegReg = MI->getOperand(Op+4);
>>
>> + if (UseMarkup)
>> + O << "<mem:";
>> +
>> // If this has a segment register, print it.
>> if (SegReg.getReg()) {
>> printOperand(MI, Op+4, O);
>> @@ -196,9 +215,18 @@
>> O << ',';
>> printOperand(MI, Op+2, O);
>> unsigned ScaleVal = MI->getOperand(Op+1).getImm();
>> - if (ScaleVal != 1)
>> - O << ',' << ScaleVal;
>> + if (ScaleVal != 1) {
>> + O << ',';
>> + if (UseMarkup)
>> + O << "<imm:";
>> + O << ScaleVal;
>> + if (UseMarkup)
>> + O << ">";
>> + }
>> }
>> O << ')';
>> }
>> +
>> + if (UseMarkup)
>> + O << ">";
>> }
>>
>> Added: llvm/trunk/test/MC/Disassembler/ARM/marked-up-thumb.txt
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/marked-up-thumb.txt?rev=166445&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/MC/Disassembler/ARM/marked-up-thumb.txt (added)
>> +++ llvm/trunk/test/MC/Disassembler/ARM/marked-up-thumb.txt Mon Oct 22 17:31:46 2012
>> @@ -0,0 +1,7 @@
>> +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -mdis < %s | FileCheck %s
>> +# CHECK: ldr <reg:r4>, <imm:#32>
>> +0x08 0x4c
>> +# CHECK: push {<reg:r1>, <reg:r2>, <reg:r7>}
>> +0x86 0xb4
>> +# CHECK: sub <reg:sp>, <imm:#132>
>> +0xa1 0xb0
>>
>> Added: llvm/trunk/test/MC/Disassembler/X86/marked-up.txt
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/marked-up.txt?rev=166445&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/MC/Disassembler/X86/marked-up.txt (added)
>> +++ llvm/trunk/test/MC/Disassembler/X86/marked-up.txt Mon Oct 22 17:31:46 2012
>> @@ -0,0 +1,6 @@
>> +# RUN: llvm-mc --mdis %s -triple=x86_64-apple-darwin9 2>&1 | FileCheck %s
>> +
>> +# CHECK: movq <mem:<reg:%gs>:8>, <reg:%rcx>
>> +0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00
>> +# CHECK: xorps <reg:%xmm1>, <reg:%xmm2>
>> +0x0f 0x57 0xd1
>>
>> Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=166445&r1=166444&r2=166445&view=diff
>> ==============================================================================
>> --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original)
>> +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Mon Oct 22 17:31:46 2012
>> @@ -158,7 +158,8 @@
>> AC_AsLex,
>> AC_Assemble,
>> AC_Disassemble,
>> - AC_EDisassemble
>> + AC_EDisassemble,
>> + AC_MDisassemble
>> };
>>
>> static cl::opt<ActionType>
>> @@ -172,6 +173,8 @@
>> "Disassemble strings of hex bytes"),
>> clEnumValN(AC_EDisassemble, "edis",
>> "Enhanced disassembly of strings of hex bytes"),
>> + clEnumValN(AC_MDisassemble, "mdis",
>> + "Marked up disassembly of strings of hex bytes"),
>> clEnumValEnd));
>>
>> static const Target *GetTarget(const char *ProgName) {
>> @@ -402,8 +405,9 @@
>> OwningPtr<MCSubtargetInfo>
>> STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
>>
>> + MCInstPrinter *IP;
>> if (FileType == OFT_AssemblyFile) {
>> - MCInstPrinter *IP =
>> + IP =
>> TheTarget->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI, *STI);
>> MCCodeEmitter *CE = 0;
>> MCAsmBackend *MAB = 0;
>> @@ -436,6 +440,9 @@
>> case AC_Assemble:
>> Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI);
>> break;
>> + case AC_MDisassemble:
>> + IP->setUseMarkup(1);
>> + // Fall through to do disassembly.
>> case AC_Disassemble:
>> Res = Disassembler::disassemble(*TheTarget, TripleName, *STI, *Str,
>> *Buffer, SrcMgr, Out->os());
>>
>> Modified: llvm/trunk/tools/lto/lto.exports
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/lto.exports?rev=166445&r1=166444&r2=166445&view=diff
>> ==============================================================================
>> --- llvm/trunk/tools/lto/lto.exports (original)
>> +++ llvm/trunk/tools/lto/lto.exports Mon Oct 22 17:31:46 2012
>> @@ -30,3 +30,4 @@
>> LLVMCreateDisasm
>> LLVMDisasmDispose
>> LLVMDisasmInstruction
>> +LLVMSetDisasmOptions
>>
>>
>> _______________________________________________
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>> llvm-commits at cs.uiuc.edu
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