[llvm-commits] [llvm] r166260 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Michael Liao]

Author: hliao
Date: Thu Oct 18 22:17:00 2012
New Revision: 166260

URL: http://llvm.org/viewvc/llvm-project?rev=166260&view=rev
Log:
Simplify condition checking as CONCAT assume all inputs of the same type.


Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=166260&r1=166259&r2=166260&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Oct 18 22:17:00 2012
@@ -8629,9 +8629,9 @@
     //    (extract_subvec (concat V1, V2, ...), i)
     // Into:
     //    Vi if possible
-    for (unsigned i = 0, e = V->getNumOperands(); i != e; ++i)
-      if (V->getOperand(i).getValueType() != NVT)
-        return SDValue();
+    // Only operand 0 is checked as 'concat' assumes all inputs of the same type.
+    if (V->getOperand(0).getValueType() != NVT)
+      return SDValue();
     unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
     unsigned NumElems = NVT.getVectorNumElements();
     assert((Idx % NumElems) == 0 &&