[llvm-commits] [llvm] r166086 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Michael Liao]

Author: hliao
Date: Tue Oct 16 22:59:18 2012
New Revision: 166086

URL: http://llvm.org/viewvc/llvm-project?rev=166086&view=rev
Log:
Check SSSE3 instead of SSE4.1

- All shuffle insns required, especially PSHUB, are added in SSSE3.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=166086&r1=166085&r2=166086&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Oct 16 22:59:18 2012
@@ -15477,11 +15477,11 @@
   ISD::LoadExtType Ext = Ld->getExtensionType();
 
   // If this is a vector EXT Load then attempt to optimize it using a
-  // shuffle. We need SSE4 for the shuffles.
+  // shuffle. We need SSSE3 shuffles.
   // TODO: It is possible to support ZExt by zeroing the undef values
   // during the shuffle phase or after the shuffle.
   if (RegVT.isVector() && RegVT.isInteger() &&
-      Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
+      Ext == ISD::EXTLOAD && Subtarget->hasSSSE3()) {
     assert(MemVT != RegVT && "Cannot extend to the same type");
     assert(MemVT.isVector() && "Must load a vector from memory");