[llvm-commits] [ARM] Fix for blocking PR13790. AAPCS byval params issue.

[manman ren]

Hi Stepan,

Is it possible for you to have another testing case with byval as a fixed argument?

Why do we still need to store r1? I thought after the fix, only r2 and r3 are used :]

+; CHECK: stm     r0, {r1, r2, r3}
+  %g = alloca i8*
+  %g1 = bitcast i8** %g to i8*
+  call void @llvm.va_start(i8* %g1)

Otherwise LGTM,

Thanks,
Manman

On Oct 11, 2012, at 7:25 AM, Stepan Dyatkovskiy <stpworld at narod.ru> wrote:

> Hi Anton,
> 
> > How will you patch influence APCS?
> 
> To make all clear, I updated patch and made it fixing AAPCS case only.
> 
> I can't get codegen to emit 8 bytes aligned structure parameter, and I can't get to use 8-bytes aligned stack. ARM target ignores --stack-alignment option.
> 
> But if some people can get llc to use 8 bytes alignment for APCS, I'm 90% sure that this issue fires again.
> 
> Relative to APCS:
> 
> In APCS we can found the next statement:
> "The APCS does not define:
> - the layout in store of records, arrays, as so forth, used by ARM-targeted compilers
> for C and C++
> ..."
> and a bit below:
> "This means that, the mapping from language-level data types and arguments to APCS
> words is defined by each language implementation, not by the APCS."
> (APCS, 9.2.7 Data representation and argument passing)
> 
> APCS was defined in ARM Software Development Toolkit, ARM DUI 0041C.
> 
> In this document I also found next recommendation for compiler developers:
> "The alignment of a non-packed structure is the larger of:
> - The maximum alignment required by any of its fields
> ... "
> (3.2.4 Structured data types)
> 
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